1 /* 2 * HND Run Time Environment ioctl. 3 * 4 * Portions of this code are copyright (c) 2021 Cypress Semiconductor Corporation 5 * 6 * Copyright (C) 1999-2017, Broadcom Corporation 7 * 8 * Unless you and Broadcom execute a separate written software license 9 * agreement governing use of this software, this software is licensed to you 10 * under the terms of the GNU General Public License version 2 (the "GPL"), 11 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 12 * following added to such license: 13 * 14 * As a special exception, the copyright holders of this software give you 15 * permission to link this software with independent modules, and to copy and 16 * distribute the resulting executable under terms of your choice, provided that 17 * you also meet, for each linked independent module, the terms and conditions of 18 * the license of that module. An independent module is a module which is not 19 * derived from this software. The special exception does not apply to any 20 * modifications of the software. 21 * 22 * Notwithstanding the above, under no circumstances may you combine this 23 * software in any way with any other Broadcom software provided under a license 24 * other than the GPL, without Broadcom's express prior written consent. 25 * 26 * 27 * <<Broadcom-WL-IPTag/Open:>> 28 * 29 * $Id: rte_ioctl.h 699094 2017-05-11 22:41:10Z $ 30 */ 31 32 #ifndef _rte_ioctl_h_ 33 #define _rte_ioctl_h_ 34 35 /* RTE IOCTL definitions for generic ether devices */ 36 #define RTEGHWADDR 0x8901 37 #define RTESHWADDR 0x8902 38 #define RTEGMTU 0x8903 39 #define RTEGSTATS 0x8904 40 #define RTEGALLMULTI 0x8905 41 #define RTESALLMULTI 0x8906 42 #define RTEGPROMISC 0x8907 43 #define RTESPROMISC 0x8908 44 #define RTESMULTILIST 0x8909 45 #define RTEGUP 0x890A 46 #define RTEGPERMADDR 0x890B 47 #define RTEDEVPWRSTCHG 0x890C /* Device pwr state change for PCIedev */ 48 #define RTEDEVPMETOGGLE 0x890D /* Toggle PME# to wake up the host */ 49 #define RTEDEVTIMESYNC 0x890E /* Device TimeSync */ 50 #define RTEDEVDSNOTIFY 0x890F /* Bus DS state notification */ 51 #define RTED11DMALPBK_INIT 0x8910 /* D11 DMA loopback init */ 52 #define RTED11DMALPBK_UNINIT 0x8911 /* D11 DMA loopback uninit */ 53 #define RTED11DMALPBK_RUN 0x8912 /* D11 DMA loopback run */ 54 #define RTEDEVTSBUFPOST 0x8913 /* Async interface for tsync buffer post */ 55 56 #define RTE_IOCTL_QUERY 0x00 57 #define RTE_IOCTL_SET 0x01 58 #define RTE_IOCTL_OVL_IDX_MASK 0x1e 59 #define RTE_IOCTL_OVL_RSV 0x20 60 #define RTE_IOCTL_OVL 0x40 61 #define RTE_IOCTL_OVL_IDX_SHIFT 1 62 63 enum hnd_ioctl_cmd { 64 HND_RTE_DNGL_IS_SS = 1, /* true if device connected at super speed */ 65 66 /* PCIEDEV specific wl <--> bus ioctls */ 67 BUS_GET_VAR = 2, 68 BUS_SET_VAR = 3, 69 BUS_FLUSH_RXREORDER_Q = 4, 70 BUS_SET_LTR_STATE = 5, 71 BUS_FLUSH_CHAINED_PKTS = 6, 72 BUS_SET_COPY_COUNT = 7, 73 BUS_UPDATE_FLOW_PKTS_MAX = 8, 74 BUS_UPDATE_EXTRA_TXLFRAGS = 9, 75 BUS_UPDATE_FRWD_RESRV_BUFCNT = 10, 76 BUS_PCIE_CONFIG_ACCESS = 11 77 }; 78 79 #define SDPCMDEV_SET_MAXTXPKTGLOM 1 80 #define RTE_MEMUSEINFO_VER 0x00 81 82 typedef struct memuse_info { 83 uint16 ver; /* version of this struct */ 84 uint16 len; /* length in bytes of this structure */ 85 uint32 tot; /* Total memory */ 86 uint32 text_len; /* Size of Text segment memory */ 87 uint32 data_len; /* Size of Data segment memory */ 88 uint32 bss_len; /* Size of BSS segment memory */ 89 90 uint32 arena_size; /* Total Heap size */ 91 uint32 arena_free; /* Heap memory available or free */ 92 uint32 inuse_size; /* Heap memory currently in use */ 93 uint32 inuse_hwm; /* High watermark of memory - reclaimed memory */ 94 uint32 inuse_overhead; /* tally of allocated mem_t blocks */ 95 uint32 inuse_total; /* Heap in-use + Heap overhead memory */ 96 uint32 free_lwm; /* Least free size since reclaim */ 97 uint32 mf_count; /* Malloc failure count */ 98 } memuse_info_t; 99 100 /* For D11 DMA loopback test */ 101 typedef struct d11_dmalpbk_args { 102 uint8 *buf; 103 int32 len; 104 } d11_dmalpbk_args_t; 105 #endif /* _rte_ioctl_h_ */ 106