1 /* 2 * Broadcom HND chip & on-chip-interconnect-related definitions. 3 * 4 * Portions of this code are copyright (c) 2021 Cypress Semiconductor Corporation 5 * 6 * Copyright (C) 1999-2017, Broadcom Corporation 7 * 8 * Unless you and Broadcom execute a separate written software license 9 * agreement governing use of this software, this software is licensed to you 10 * under the terms of the GNU General Public License version 2 (the "GPL"), 11 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 12 * following added to such license: 13 * 14 * As a special exception, the copyright holders of this software give you 15 * permission to link this software with independent modules, and to copy and 16 * distribute the resulting executable under terms of your choice, provided that 17 * you also meet, for each linked independent module, the terms and conditions of 18 * the license of that module. An independent module is a module which is not 19 * derived from this software. The special exception does not apply to any 20 * modifications of the software. 21 * 22 * Notwithstanding the above, under no circumstances may you combine this 23 * software in any way with any other Broadcom software provided under a license 24 * other than the GPL, without Broadcom's express prior written consent. 25 * 26 * 27 * <<Broadcom-WL-IPTag/Open:>> 28 * 29 * $Id: hndsoc.h 672520 2016-11-28 23:30:55Z $ 30 */ 31 32 #ifndef _HNDSOC_H 33 #define _HNDSOC_H 34 35 /* Include the soci specific files */ 36 #include <sbconfig.h> 37 #include <aidmp.h> 38 39 /* 40 * SOC Interconnect Address Map. 41 * All regions may not exist on all chips. 42 */ 43 #define SI_SDRAM_BASE 0x00000000 /* Physical SDRAM */ 44 #define SI_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */ 45 #define SI_PCI_MEM_SZ (64 * 1024 * 1024) 46 #define SI_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */ 47 #define SI_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */ 48 #define SI_SDRAM_R2 0x80000000 /* Region 2 for sdram (512 MB) */ 49 50 #ifdef STB_SOC_WIFI 51 #define SI_REG_BASE_SIZE 0xB000 /* size from 0xf1800000 to 0xf180AFFF (44KB) */ 52 #define SI_ENUM_BASE_DEFAULT 0xF1800000 /* Enumeration space base */ 53 #define SI_WRAP_BASE_DEFAULT 0xF1900000 /* Wrapper space base */ 54 #endif /* STB_SOC_WIFI */ 55 56 #ifndef SI_ENUM_BASE_DEFAULT 57 #define SI_ENUM_BASE_DEFAULT 0x18000000 /* Enumeration space base */ 58 #endif // endif 59 60 #ifndef SI_WRAP_BASE_DEFAULT 61 #define SI_WRAP_BASE_DEFAULT 0x18100000 /* Wrapper space base */ 62 #endif // endif 63 64 #ifndef SI_ENUM_PCIE2_BASE 65 #define SI_ENUM_PCIE2_BASE 0x18003000 /* PCIE Enumeration space base */ 66 #endif // endif 67 68 /** new(er) chips started locating their chipc core at a different BP address than 0x1800_0000 */ 69 // NIC and DHD driver binaries should support both old(er) and new(er) chips at the same time 70 #define SI_ENUM_BASE(sih) ((sih)->enum_base) 71 #define SI_WRAP_BASE(sih) (SI_ENUM_BASE(sih) + 0x00100000) 72 73 #define SI_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */ 74 75 #define SI_NIC400_GPV_BASE 0x18200000 /* NIC-400 Global Programmers View (GPV) */ 76 #define SI_GPV_WR_CAP_ADDR 0x4008 /* WR-CAP offset */ 77 #define SI_GPV_RD_CAP_EN 0x1 /* issue read */ 78 #define SI_GPV_WR_CAP_EN 0x2 /* issue write */ 79 80 #ifndef SI_MAXCORES 81 #define SI_MAXCORES 32 /* NorthStar has more cores */ 82 #endif /* SI_MAXCORES */ 83 84 #define SI_MAXBR 4 /* Max bridges (this is arbitrary, for software 85 * convenience and could be changed if we 86 * make any larger chips 87 */ 88 89 #define SI_FASTRAM 0x19000000 /* On-chip RAM on chips that also have DDR */ 90 #define SI_FASTRAM_SWAPPED 0x19800000 91 92 #define SI_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */ 93 #define SI_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */ 94 #define SI_ARMCM3_ROM 0x1e000000 /* ARM Cortex-M3 ROM */ 95 #define SI_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */ 96 #define SI_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */ 97 #define SI_FLASH_WINDOW 0x01000000 /* Flash XIP Window */ 98 99 #define SI_NS_NANDFLASH 0x1c000000 /* NorthStar NAND flash base */ 100 #define SI_NS_NORFLASH 0x1e000000 /* NorthStar NOR flash base */ 101 #define SI_NS_ROM 0xfffd0000 /* NorthStar ROM */ 102 #define SI_NS_FLASH_WINDOW 0x02000000 /* Flash XIP Window */ 103 104 #define SI_ARM7S_ROM 0x20000000 /* ARM7TDMI-S ROM */ 105 #define SI_ARMCR4_ROM 0x000f0000 /* ARM Cortex-R4 ROM */ 106 #define SI_ARMCM3_SRAM2 0x60000000 /* ARM Cortex-M3 SRAM Region 2 */ 107 #define SI_ARM7S_SRAM2 0x80000000 /* ARM7TDMI-S SRAM Region 2 */ 108 #define SI_ARMCA7_ROM 0x00000000 /* ARM Cortex-A7 ROM */ 109 #ifndef SI_ARMCA7_RAM 110 #define SI_ARMCA7_RAM 0x00200000 /* ARM Cortex-A7 RAM */ 111 #endif // endif 112 #define SI_ARM_FLASH1 0xffff0000 /* ARM Flash Region 1 */ 113 #define SI_ARM_FLASH1_SZ 0x00010000 /* ARM Size of Flash Region 1 */ 114 115 #define SI_SFLASH 0x14000000 116 #define SI_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */ 117 #define SI_PCI_DMA2 0x80000000 /* Client Mode sb2pcitranslation2 (1 GB) */ 118 #define SI_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */ 119 #define SI_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2 120 * (2 ZettaBytes), low 32 bits 121 */ 122 #define SI_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2 123 * (2 ZettaBytes), high 32 bits 124 */ 125 126 #define SI_BCM53573_NANDFLASH 0x30000000 /* 53573 NAND flash base */ 127 #define SI_BCM53573_NORFLASH 0x1c000000 /* 53573 NOR flash base */ 128 #define SI_BCM53573_FLASH2_SZ 0x04000000 /* 53573 NOR flash2 size */ 129 130 #define SI_BCM53573_NORFLASH_WINDOW 0x01000000 /* only support 16M direct access for 131 * 3-byte address modes in spi flash 132 */ 133 #define SI_BCM53573_BOOTDEV_MASK 0x3 134 #define SI_BCM53573_BOOTDEV_NOR 0x0 135 136 #define SI_BCM53573_NAND_PRE_MASK 0x100 /* 53573 NAND present mask */ 137 138 #define SI_BCM53573_DDRTYPE_MASK 0x10 139 #define SI_BCM53573_DDRTYPE_DDR3 0x10 140 141 #define SI_BCM47189_RGMII_VDD_MASK 0x3 142 #define SI_BCM47189_RGMII_VDD_SHIFT 21 143 #define SI_BCM47189_RGMII_VDD_3_3V 0 144 #define SI_BCM47189_RGMII_VDD_2_5V 1 145 #define SI_BCM47189_RGMII_VDD_1_5V 1 146 147 #define SI_BCM53573_LOCKED_CPUPLL 0x1 148 149 /* APB bridge code */ 150 #define APB_BRIDGE_ID 0x135 /* APB Bridge 0, 1, etc. */ 151 152 /* core codes */ 153 #define NODEV_CORE_ID 0x700 /* Invalid coreid */ 154 #define CC_CORE_ID 0x800 /* chipcommon core */ 155 #define ILINE20_CORE_ID 0x801 /* iline20 core */ 156 #define SRAM_CORE_ID 0x802 /* sram core */ 157 #define SDRAM_CORE_ID 0x803 /* sdram core */ 158 #define PCI_CORE_ID 0x804 /* pci core */ 159 #define MIPS_CORE_ID 0x805 /* mips core */ 160 #define ENET_CORE_ID 0x806 /* enet mac core */ 161 #define CODEC_CORE_ID 0x807 /* v90 codec core */ 162 #define USB_CORE_ID 0x808 /* usb 1.1 host/device core */ 163 #define ADSL_CORE_ID 0x809 /* ADSL core */ 164 #define ILINE100_CORE_ID 0x80a /* iline100 core */ 165 #define IPSEC_CORE_ID 0x80b /* ipsec core */ 166 #define UTOPIA_CORE_ID 0x80c /* utopia core */ 167 #define PCMCIA_CORE_ID 0x80d /* pcmcia core */ 168 #define SOCRAM_CORE_ID 0x80e /* internal memory core */ 169 #define MEMC_CORE_ID 0x80f /* memc sdram core */ 170 #define OFDM_CORE_ID 0x810 /* OFDM phy core */ 171 #define EXTIF_CORE_ID 0x811 /* external interface core */ 172 #define D11_CORE_ID 0x812 /* 802.11 MAC core */ 173 #define APHY_CORE_ID 0x813 /* 802.11a phy core */ 174 #define BPHY_CORE_ID 0x814 /* 802.11b phy core */ 175 #define GPHY_CORE_ID 0x815 /* 802.11g phy core */ 176 #define MIPS33_CORE_ID 0x816 /* mips3302 core */ 177 #define USB11H_CORE_ID 0x817 /* usb 1.1 host core */ 178 #define USB11D_CORE_ID 0x818 /* usb 1.1 device core */ 179 #define USB20H_CORE_ID 0x819 /* usb 2.0 host core */ 180 #define USB20D_CORE_ID 0x81a /* usb 2.0 device core */ 181 #define SDIOH_CORE_ID 0x81b /* sdio host core */ 182 #define ROBO_CORE_ID 0x81c /* roboswitch core */ 183 #define ATA100_CORE_ID 0x81d /* parallel ATA core */ 184 #define SATAXOR_CORE_ID 0x81e /* serial ATA & XOR DMA core */ 185 #define GIGETH_CORE_ID 0x81f /* gigabit ethernet core */ 186 #define PCIE_CORE_ID 0x820 /* pci express core */ 187 #define NPHY_CORE_ID 0x821 /* 802.11n 2x2 phy core */ 188 #define SRAMC_CORE_ID 0x822 /* SRAM controller core */ 189 #define MINIMAC_CORE_ID 0x823 /* MINI MAC/phy core */ 190 #define ARM11_CORE_ID 0x824 /* ARM 1176 core */ 191 #define ARM7S_CORE_ID 0x825 /* ARM7tdmi-s core */ 192 #define LPPHY_CORE_ID 0x826 /* 802.11a/b/g phy core */ 193 #define PMU_CORE_ID 0x827 /* PMU core */ 194 #define SSNPHY_CORE_ID 0x828 /* 802.11n single-stream phy core */ 195 #define SDIOD_CORE_ID 0x829 /* SDIO device core */ 196 #define ARMCM3_CORE_ID 0x82a /* ARM Cortex M3 core */ 197 #define HTPHY_CORE_ID 0x82b /* 802.11n 4x4 phy core */ 198 #define MIPS74K_CORE_ID 0x82c /* mips 74k core */ 199 #define GMAC_CORE_ID 0x82d /* Gigabit MAC core */ 200 #define DMEMC_CORE_ID 0x82e /* DDR1/2 memory controller core */ 201 #define PCIERC_CORE_ID 0x82f /* PCIE Root Complex core */ 202 #define OCP_CORE_ID 0x830 /* OCP2OCP bridge core */ 203 #define SC_CORE_ID 0x831 /* shared common core */ 204 #define AHB_CORE_ID 0x832 /* OCP2AHB bridge core */ 205 #define SPIH_CORE_ID 0x833 /* SPI host core */ 206 #define I2S_CORE_ID 0x834 /* I2S core */ 207 #define DMEMS_CORE_ID 0x835 /* SDR/DDR1 memory controller core */ 208 #define DEF_SHIM_COMP 0x837 /* SHIM component in ubus/6362 */ 209 210 #define ACPHY_CORE_ID 0x83b /* Dot11 ACPHY */ 211 #define PCIE2_CORE_ID 0x83c /* pci express Gen2 core */ 212 #define USB30D_CORE_ID 0x83d /* usb 3.0 device core */ 213 #define ARMCR4_CORE_ID 0x83e /* ARM CR4 CPU */ 214 #define GCI_CORE_ID 0x840 /* GCI Core */ 215 #define SR_CORE_ID 0x841 /* SR_CORE ID */ 216 #define M2MDMA_CORE_ID 0x844 /* memory to memory dma */ 217 #define CMEM_CORE_ID 0x846 /* CNDS DDR2/3 memory controller */ 218 #define ARMCA7_CORE_ID 0x847 /* ARM CA7 CPU */ 219 #define SYSMEM_CORE_ID 0x849 /* System memory core */ 220 #define HUB_CORE_ID 0x84b /* Hub core ID */ 221 #define HND_OOBR_CORE_ID 0x85c /* Hnd oob router core ID */ 222 #define APB_BRIDGE_CORE_ID 0x135 /* APB bridge core ID */ 223 #define AXI_CORE_ID 0x301 /* AXI/GPV core ID */ 224 #define EROM_CORE_ID 0x366 /* EROM core ID */ 225 #define OOB_ROUTER_CORE_ID 0x367 /* OOB router core ID */ 226 #define DEF_AI_COMP 0xfff /* Default component, in ai chips it maps all 227 * unused address ranges 228 */ 229 230 #define NS_PCIEG2_CORE_ID 0x501 /* PCIE Gen 2 core */ 231 #define NS_DMA_CORE_ID 0x502 /* DMA core */ 232 #define NS_SDIO3_CORE_ID 0x503 /* SDIO3 core */ 233 #define NS_USB20_CORE_ID 0x504 /* USB2.0 core */ 234 #define NS_USB30_CORE_ID 0x505 /* USB3.0 core */ 235 #define NS_A9JTAG_CORE_ID 0x506 /* ARM Cortex A9 JTAG core */ 236 #define NS_DDR23_CORE_ID 0x507 /* Denali DDR2/DDR3 memory controller */ 237 #define NS_ROM_CORE_ID 0x508 /* ROM core */ 238 #define NS_NAND_CORE_ID 0x509 /* NAND flash controller core */ 239 #define NS_QSPI_CORE_ID 0x50a /* SPI flash controller core */ 240 #define NS_CCB_CORE_ID 0x50b /* ChipcommonB core */ 241 #define NS_SOCRAM_CORE_ID 0x50e /* internal memory core */ 242 #define ARMCA9_CORE_ID 0x510 /* ARM Cortex A9 core (ihost) */ 243 #define NS_IHOST_CORE_ID ARMCA9_CORE_ID /* ARM Cortex A9 core (ihost) */ 244 #define AMEMC_CORE_ID 0x52e /* DDR1/2 memory controller core */ 245 #define ALTA_CORE_ID 0x534 /* I2S core */ 246 #define DDR23_PHY_CORE_ID 0x5dd 247 248 #define SI_PCI1_MEM 0x40000000 /* Host Mode sb2pcitranslation0 (64 MB) */ 249 #define SI_PCI1_CFG 0x44000000 /* Host Mode sb2pcitranslation1 (64 MB) */ 250 #define SI_PCIE1_DMA_H32 0xc0000000 /* PCIE Client Mode sb2pcitranslation2 251 * (2 ZettaBytes), high 32 bits 252 */ 253 #define NS_PCIEG2_CORE_REV_B0 0x7 /* NS-B0 PCIE Gen 2 core rev */ 254 255 /* There are TWO constants on all HND chips: SI_ENUM_BASE_DEFAULT above, 256 * and chipcommon being the first core: 257 */ 258 #define SI_CC_IDX 0 259 /* SOC Interconnect types (aka chip types) */ 260 #define SOCI_SB 0 261 #define SOCI_AI 1 262 #define SOCI_UBUS 2 263 #define SOCI_NAI 3 264 #define SOCI_DVTBUS 4 /* BCM7XXX Digital Video Tech bus */ 265 266 /* Common core control flags */ 267 #define SICF_BIST_EN 0x8000 268 #define SICF_PME_EN 0x4000 269 #define SICF_CORE_BITS 0x3ffc 270 #define SICF_FGC 0x0002 271 #define SICF_CLOCK_EN 0x0001 272 273 /* Common core status flags */ 274 #define SISF_BIST_DONE 0x8000 275 #define SISF_BIST_ERROR 0x4000 276 #define SISF_GATED_CLK 0x2000 277 #define SISF_DMA64 0x1000 278 #define SISF_CORE_BITS 0x0fff 279 280 /* Norstar core status flags */ 281 #define SISF_NS_BOOTDEV_MASK 0x0003 /* ROM core */ 282 #define SISF_NS_BOOTDEV_NOR 0x0000 /* ROM core */ 283 #define SISF_NS_BOOTDEV_NAND 0x0001 /* ROM core */ 284 #define SISF_NS_BOOTDEV_ROM 0x0002 /* ROM core */ 285 #define SISF_NS_BOOTDEV_OFFLOAD 0x0003 /* ROM core */ 286 #define SISF_NS_SKUVEC_MASK 0x000c /* ROM core */ 287 288 /* dot11 core-specific status flags */ 289 #define SISF_MINORREV_D11_SHIFT 16 290 #define SISF_MINORREV_D11_MASK 0xF /**< minor corerev (corerev == 61) */ 291 292 /* A register that is common to all cores to 293 * communicate w/PMU regarding clock control. 294 */ 295 #define SI_CLK_CTL_ST 0x1e0 /* clock control and status */ 296 #define SI_PWR_CTL_ST 0x1e8 /* For memory clock gating */ 297 298 /* clk_ctl_st register */ 299 #define CCS_FORCEALP 0x00000001 /* force ALP request */ 300 #define CCS_FORCEHT 0x00000002 /* force HT request */ 301 #define CCS_FORCEILP 0x00000004 /* force ILP request */ 302 #define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */ 303 #define CCS_HTAREQ 0x00000010 /* HT Avail Request */ 304 #define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */ 305 #define CCS_HQCLKREQ 0x00000040 /* HQ Clock Required */ 306 #define CCS_USBCLKREQ 0x00000100 /* USB Clock Req */ 307 #define CCS_SECICLKREQ 0x00000100 /* SECI Clock Req */ 308 #define CCS_ARMFASTCLOCKREQ 0x00000100 /* ARM CR4/CA7 fast clock request */ 309 #define CCS_SFLASH_CLKREQ 0x00000200 /* Sflash clk request */ 310 #define CCS_AVBCLKREQ 0x00000400 /* AVB Clock enable request */ 311 #define CCS_ERSRC_REQ_MASK 0x00000700 /* external resource requests */ 312 #define CCS_ERSRC_REQ_SHIFT 8 313 #define CCS_ALPAVAIL 0x00010000 /* ALP is available */ 314 #define CCS_HTAVAIL 0x00020000 /* HT is available */ 315 #define CCS_BP_ON_APL 0x00040000 /* RO: Backplane is running on ALP clock */ 316 #define CCS_BP_ON_HT 0x00080000 /* RO: Backplane is running on HT clock */ 317 #define CCS_ARMFASTCLOCKSTATUS 0x01000000 /* Fast CPU clock is running */ 318 #define CCS_ERSRC_STS_MASK 0x07000000 /* external resource status */ 319 #define CCS_ERSRC_STS_SHIFT 24 320 #define CCS_SECI_AVAIL 0x01000000 /* RO: SECI is available */ 321 322 /* Not really related to SOC Interconnect, but a couple of software 323 * conventions for the use the flash space: 324 */ 325 326 /* Minumum amount of flash we support */ 327 #define FLASH_MIN 0x00020000 /* Minimum flash size */ 328 329 /* A boot/binary may have an embedded block that describes its size */ 330 #define BISZ_OFFSET 0x3e0 /* At this offset into the binary */ 331 #define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */ 332 #define BISZ_MAGIC_IDX 0 /* Word 0: magic */ 333 #define BISZ_TXTST_IDX 1 /* 1: text start */ 334 #define BISZ_TXTEND_IDX 2 /* 2: text end */ 335 #define BISZ_DATAST_IDX 3 /* 3: data start */ 336 #define BISZ_DATAEND_IDX 4 /* 4: data end */ 337 #define BISZ_BSSST_IDX 5 /* 5: bss start */ 338 #define BISZ_BSSEND_IDX 6 /* 6: bss end */ 339 #define BISZ_SIZE 7 /* descriptor size in 32-bit integers */ 340 341 /* Boot/Kernel related defintion and functions */ 342 #define SOC_BOOTDEV_ROM 0x00000001 343 #define SOC_BOOTDEV_PFLASH 0x00000002 344 #define SOC_BOOTDEV_SFLASH 0x00000004 345 #define SOC_BOOTDEV_NANDFLASH 0x00000008 346 347 #define SOC_KNLDEV_NORFLASH 0x00000002 348 #define SOC_KNLDEV_NANDFLASH 0x00000004 349 350 #if !defined(_LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLY__) 351 int soc_boot_dev(void *sih); 352 int soc_knl_dev(void *sih); 353 #endif /* !defined(_LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLY__) */ 354 355 #define PMU_BASE_OFFSET 0x00012000 /* PMU offset is changed for ccrev >= 56 */ 356 #endif /* _HNDSOC_H */ 357