1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * HND SiliconBackplane PMU support. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Portions of this code are copyright (c) 2021 Cypress Semiconductor Corporation 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 1999-2017, Broadcom Corporation 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Unless you and Broadcom execute a separate written software license 9*4882a593Smuzhiyun * agreement governing use of this software, this software is licensed to you 10*4882a593Smuzhiyun * under the terms of the GNU General Public License version 2 (the "GPL"), 11*4882a593Smuzhiyun * available at http://www.broadcom.com/licenses/GPLv2.php, with the 12*4882a593Smuzhiyun * following added to such license: 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * As a special exception, the copyright holders of this software give you 15*4882a593Smuzhiyun * permission to link this software with independent modules, and to copy and 16*4882a593Smuzhiyun * distribute the resulting executable under terms of your choice, provided that 17*4882a593Smuzhiyun * you also meet, for each linked independent module, the terms and conditions of 18*4882a593Smuzhiyun * the license of that module. An independent module is a module which is not 19*4882a593Smuzhiyun * derived from this software. The special exception does not apply to any 20*4882a593Smuzhiyun * modifications of the software. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * Notwithstanding the above, under no circumstances may you combine this 23*4882a593Smuzhiyun * software in any way with any other Broadcom software provided under a license 24*4882a593Smuzhiyun * other than the GPL, without Broadcom's express prior written consent. 25*4882a593Smuzhiyun * 26*4882a593Smuzhiyun * 27*4882a593Smuzhiyun * <<Broadcom-WL-IPTag/Open:>> 28*4882a593Smuzhiyun * 29*4882a593Smuzhiyun * $Id: hndpmu.h 700376 2017-05-18 22:55:43Z $ 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #ifndef _hndpmu_h_ 33*4882a593Smuzhiyun #define _hndpmu_h_ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #include <typedefs.h> 36*4882a593Smuzhiyun #include <osl_decl.h> 37*4882a593Smuzhiyun #include <siutils.h> 38*4882a593Smuzhiyun #include <sbchipc.h> 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun extern uint32 si_pmu_rsrc_macphy_clk_deps(si_t *sih, osl_t *osh, int maccore_index); 41*4882a593Smuzhiyun extern uint32 si_pmu_rsrc_ht_avail_clk_deps(si_t *sih, osl_t *osh); 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun extern void si_pmu_otp_power(si_t *sih, osl_t *osh, bool on, uint32* min_res_mask); 44*4882a593Smuzhiyun extern void si_sdiod_drive_strength_init(si_t *sih, osl_t *osh, uint32 drivestrength); 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun extern void si_pmu_slow_clk_reinit(si_t *sih, osl_t *osh); 47*4882a593Smuzhiyun extern void si_pmu_avbtimer_enable(si_t *sih, osl_t *osh, bool set_flag); 48*4882a593Smuzhiyun extern uint32 si_pmu_dump_pmucap_binary(si_t *sih, uchar *p); 49*4882a593Smuzhiyun extern uint32 si_pmu_dump_buf_size_pmucap(si_t *sih); 50*4882a593Smuzhiyun extern int si_pmu_wait_for_steady_state(si_t *sih, osl_t *osh, pmuregs_t *pmu); 51*4882a593Smuzhiyun extern uint32 si_pmu_wake_bit_offset(si_t *sih); 52*4882a593Smuzhiyun #if defined(BCMULP) 53*4882a593Smuzhiyun int si_pmu_ulp_register(si_t *sih); 54*4882a593Smuzhiyun extern void si_pmu_ulp_chipconfig(si_t *sih, osl_t *osh); 55*4882a593Smuzhiyun extern void si_pmu_ulp_ilp_config(si_t *sih, osl_t *osh, uint32 ilp_period); 56*4882a593Smuzhiyun extern void si_pmu_ds1_res_init(si_t *sih, osl_t *osh); 57*4882a593Smuzhiyun #endif /* BCMULP */ 58*4882a593Smuzhiyun extern uint32 si_pmu_get_pmutimer(si_t *sih); 59*4882a593Smuzhiyun extern void si_switch_pmu_dependency(si_t *sih, uint mode); 60*4882a593Smuzhiyun extern void si_pmu_set_min_res_mask(si_t *sih, osl_t *osh, uint min_res_mask); 61*4882a593Smuzhiyun extern void si_pmu_set_mac_rsrc_req(si_t *sih, int macunit); 62*4882a593Smuzhiyun extern bool si_pmu_fast_lpo_enable_pcie(si_t *sih); 63*4882a593Smuzhiyun extern bool si_pmu_fast_lpo_enable_pmu(si_t *sih); 64*4882a593Smuzhiyun extern void si_pmu_chipcontrol_xtal_settings_4369(si_t *sih); 65*4882a593Smuzhiyun extern uint32 si_cur_pmu_time(si_t *sih); 66*4882a593Smuzhiyun extern bool si_pmu_cap_fast_lpo(si_t *sih); 67*4882a593Smuzhiyun extern int si_pmu_fast_lpo_disable(si_t *sih); 68*4882a593Smuzhiyun #ifdef BCMPMU_STATS 69*4882a593Smuzhiyun extern void si_pmustatstimer_init(si_t *sih); 70*4882a593Smuzhiyun extern void si_pmustatstimer_dump(si_t *sih); 71*4882a593Smuzhiyun extern void si_pmustatstimer_start(si_t *sih, uint8 timerid); 72*4882a593Smuzhiyun extern void si_pmustatstimer_stop(si_t *sih, uint8 timerid); 73*4882a593Smuzhiyun extern void si_pmustatstimer_clear(si_t *sih, uint8 timerid); 74*4882a593Smuzhiyun extern void si_pmustatstimer_clear_overflow(si_t *sih); 75*4882a593Smuzhiyun extern uint32 si_pmustatstimer_read(si_t *sih, uint8 timerid); 76*4882a593Smuzhiyun extern void si_pmustatstimer_cfg_src_num(si_t *sih, uint8 src_num, uint8 timerid); 77*4882a593Smuzhiyun extern void si_pmustatstimer_cfg_cnt_mode(si_t *sih, uint8 cnt_mode, uint8 timerid); 78*4882a593Smuzhiyun extern void si_pmustatstimer_int_enable(si_t *sih); 79*4882a593Smuzhiyun extern void si_pmustatstimer_int_disable(si_t *sih); 80*4882a593Smuzhiyun #endif /* BCMPMU_STATS */ 81*4882a593Smuzhiyun #endif /* _hndpmu_h_ */ 82