xref: /OK3568_Linux_fs/external/rkwifibt/drivers/infineon/include/dhdioctl.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Definitions for ioctls to access DHD iovars.
3*4882a593Smuzhiyun  * Based on wlioctl.h (for Broadcom 802.11abg driver).
4*4882a593Smuzhiyun  * (Moves towards generic ioctls for BCM drivers/iovars.)
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Definitions subject to change without notice.
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * Portions of this code are copyright (c) 2021 Cypress Semiconductor Corporation
9*4882a593Smuzhiyun  *
10*4882a593Smuzhiyun  * Copyright (C) 1999-2017, Broadcom Corporation
11*4882a593Smuzhiyun  *
12*4882a593Smuzhiyun  *      Unless you and Broadcom execute a separate written software license
13*4882a593Smuzhiyun  * agreement governing use of this software, this software is licensed to you
14*4882a593Smuzhiyun  * under the terms of the GNU General Public License version 2 (the "GPL"),
15*4882a593Smuzhiyun  * available at http://www.broadcom.com/licenses/GPLv2.php, with the
16*4882a593Smuzhiyun  * following added to such license:
17*4882a593Smuzhiyun  *
18*4882a593Smuzhiyun  *      As a special exception, the copyright holders of this software give you
19*4882a593Smuzhiyun  * permission to link this software with independent modules, and to copy and
20*4882a593Smuzhiyun  * distribute the resulting executable under terms of your choice, provided that
21*4882a593Smuzhiyun  * you also meet, for each linked independent module, the terms and conditions of
22*4882a593Smuzhiyun  * the license of that module.  An independent module is a module which is not
23*4882a593Smuzhiyun  * derived from this software.  The special exception does not apply to any
24*4882a593Smuzhiyun  * modifications of the software.
25*4882a593Smuzhiyun  *
26*4882a593Smuzhiyun  *      Notwithstanding the above, under no circumstances may you combine this
27*4882a593Smuzhiyun  * software in any way with any other Broadcom software provided under a license
28*4882a593Smuzhiyun  * other than the GPL, without Broadcom's express prior written consent.
29*4882a593Smuzhiyun  *
30*4882a593Smuzhiyun  *
31*4882a593Smuzhiyun  * <<Broadcom-WL-IPTag/Open:>>
32*4882a593Smuzhiyun  *
33*4882a593Smuzhiyun  * $Id: dhdioctl.h 697634 2017-05-04 11:02:38Z $
34*4882a593Smuzhiyun  */
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #ifndef _dhdioctl_h_
37*4882a593Smuzhiyun #define	_dhdioctl_h_
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #include <typedefs.h>
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun /* Linux network driver ioctl encoding */
42*4882a593Smuzhiyun typedef struct dhd_ioctl {
43*4882a593Smuzhiyun 	uint32 cmd;	/* common ioctl definition */
44*4882a593Smuzhiyun 	void *buf;	/* pointer to user buffer */
45*4882a593Smuzhiyun 	uint32 len;	/* length of user buffer */
46*4882a593Smuzhiyun 	uint32 set;	/* get or set request boolean (optional) */
47*4882a593Smuzhiyun 	uint32 used;	/* bytes read or written (optional) */
48*4882a593Smuzhiyun 	uint32 needed;	/* bytes needed (optional) */
49*4882a593Smuzhiyun 	uint32 driver;	/* to identify target driver */
50*4882a593Smuzhiyun } dhd_ioctl_t;
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun /* Underlying BUS definition */
53*4882a593Smuzhiyun enum {
54*4882a593Smuzhiyun 	BUS_TYPE_USB = 0, /* for USB dongles */
55*4882a593Smuzhiyun 	BUS_TYPE_SDIO, /* for SDIO dongles */
56*4882a593Smuzhiyun 	BUS_TYPE_PCIE /* for PCIE dongles */
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun typedef enum {
60*4882a593Smuzhiyun 	DMA_XFER_SUCCESS = 0,
61*4882a593Smuzhiyun 	DMA_XFER_IN_PROGRESS,
62*4882a593Smuzhiyun 	DMA_XFER_FAILED
63*4882a593Smuzhiyun } dma_xfer_status_t;
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun typedef enum d11_lpbk_type {
66*4882a593Smuzhiyun 	M2M_DMA_LPBK = 0,
67*4882a593Smuzhiyun 	D11_LPBK = 1,
68*4882a593Smuzhiyun 	BMC_LPBK = 2,
69*4882a593Smuzhiyun 	M2M_NON_DMA_LPBK = 3,
70*4882a593Smuzhiyun 	D11_HOST_MEM_LPBK = 4,
71*4882a593Smuzhiyun 	BMC_HOST_MEM_LPBK = 5,
72*4882a593Smuzhiyun 	MAX_LPBK = 6
73*4882a593Smuzhiyun } dma_xfer_type_t;
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun typedef struct dmaxfer_info {
76*4882a593Smuzhiyun 	uint16 version;
77*4882a593Smuzhiyun 	uint16 length;
78*4882a593Smuzhiyun 	dma_xfer_status_t status;
79*4882a593Smuzhiyun 	dma_xfer_type_t type;
80*4882a593Smuzhiyun 	uint src_delay;
81*4882a593Smuzhiyun 	uint dest_delay;
82*4882a593Smuzhiyun 	uint should_wait;
83*4882a593Smuzhiyun 	uint core_num;
84*4882a593Smuzhiyun 	int error_code;
85*4882a593Smuzhiyun 	uint32 num_bytes;
86*4882a593Smuzhiyun 	uint64 time_taken;
87*4882a593Smuzhiyun 	uint64 tput;
88*4882a593Smuzhiyun } dma_xfer_info_t;
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun #define DHD_DMAXFER_VERSION 0x1
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun typedef struct tput_test {
93*4882a593Smuzhiyun 	uint16 version;
94*4882a593Smuzhiyun 	uint16 length;
95*4882a593Smuzhiyun 	uint8 direction;
96*4882a593Smuzhiyun 	uint8 tput_test_running;
97*4882a593Smuzhiyun 	uint8 mac_sta[6];
98*4882a593Smuzhiyun 	uint8 mac_ap[6];
99*4882a593Smuzhiyun 	uint8 PAD[2];
100*4882a593Smuzhiyun 	uint32 payload_size;
101*4882a593Smuzhiyun 	uint32 num_pkts;
102*4882a593Smuzhiyun 	uint32 timeout_ms;
103*4882a593Smuzhiyun 	uint32 flags;
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	uint32 pkts_good;
106*4882a593Smuzhiyun 	uint32 pkts_bad;
107*4882a593Smuzhiyun 	uint32 pkts_cmpl;
108*4882a593Smuzhiyun 	uint64 time_ms;
109*4882a593Smuzhiyun 	uint64 tput_bps;
110*4882a593Smuzhiyun } tput_test_t;
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun typedef enum {
113*4882a593Smuzhiyun 	TPUT_DIR_TX = 0,
114*4882a593Smuzhiyun 	TPUT_DIR_RX
115*4882a593Smuzhiyun } tput_dir_t;
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun #define TPUT_TEST_T_VER 1
118*4882a593Smuzhiyun #define TPUT_TEST_T_LEN 68
119*4882a593Smuzhiyun #define TPUT_TEST_MIN_PAYLOAD_SIZE 16
120*4882a593Smuzhiyun #define TPUT_TEST_USE_ETHERNET_HDR 0x1
121*4882a593Smuzhiyun #define TPUT_TEST_USE_802_11_HDR 0x2
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun /* per-driver magic numbers */
124*4882a593Smuzhiyun #define DHD_IOCTL_MAGIC		0x00444944
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun /* bump this number if you change the ioctl interface */
127*4882a593Smuzhiyun #define DHD_IOCTL_VERSION	1
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun /*
130*4882a593Smuzhiyun  * Increase the DHD_IOCTL_MAXLEN to 16K for supporting download of NVRAM files of size
131*4882a593Smuzhiyun  * > 8K. In the existing implementation when NVRAM is to be downloaded via the "vars"
132*4882a593Smuzhiyun  * DHD IOVAR, the NVRAM is copied to the DHD Driver memory. Later on when "dwnldstate" is
133*4882a593Smuzhiyun  * invoked with FALSE option, the NVRAM gets copied from the DHD driver to the Dongle
134*4882a593Smuzhiyun  * memory. The simple way to support this feature without modifying the DHD application,
135*4882a593Smuzhiyun  * driver logic is to increase the DHD_IOCTL_MAXLEN size. This macro defines the "size"
136*4882a593Smuzhiyun  * of the buffer in which data is exchanged between the DHD App and DHD driver.
137*4882a593Smuzhiyun  */
138*4882a593Smuzhiyun #define	DHD_IOCTL_MAXLEN	(16384)	/* max length ioctl buffer required */
139*4882a593Smuzhiyun #define	DHD_IOCTL_SMLEN		256		/* "small" length ioctl buffer required */
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun /* common ioctl definitions */
142*4882a593Smuzhiyun #define DHD_GET_MAGIC				0
143*4882a593Smuzhiyun #define DHD_GET_VERSION				1
144*4882a593Smuzhiyun #define DHD_GET_VAR				2
145*4882a593Smuzhiyun #define DHD_SET_VAR				3
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun /* message levels */
148*4882a593Smuzhiyun #define DHD_ERROR_VAL	0x0001
149*4882a593Smuzhiyun #define DHD_TRACE_VAL	0x0002
150*4882a593Smuzhiyun #define DHD_INFO_VAL	0x0004
151*4882a593Smuzhiyun #define DHD_DATA_VAL	0x0008
152*4882a593Smuzhiyun #define DHD_CTL_VAL	0x0010
153*4882a593Smuzhiyun #define DHD_TIMER_VAL	0x0020
154*4882a593Smuzhiyun #define DHD_HDRS_VAL	0x0040
155*4882a593Smuzhiyun #define DHD_BYTES_VAL	0x0080
156*4882a593Smuzhiyun #define DHD_INTR_VAL	0x0100
157*4882a593Smuzhiyun #define DHD_LOG_VAL	0x0200
158*4882a593Smuzhiyun #define DHD_GLOM_VAL	0x0400
159*4882a593Smuzhiyun #define DHD_EVENT_VAL	0x0800
160*4882a593Smuzhiyun #define DHD_BTA_VAL	0x1000
161*4882a593Smuzhiyun #define DHD_ISCAN_VAL	0x2000
162*4882a593Smuzhiyun #define DHD_ARPOE_VAL	0x4000
163*4882a593Smuzhiyun #define DHD_REORDER_VAL	0x8000
164*4882a593Smuzhiyun #define DHD_WL_VAL		0x10000
165*4882a593Smuzhiyun #define DHD_NOCHECKDIED_VAL		0x20000 /* UTF WAR */
166*4882a593Smuzhiyun #define DHD_WL_VAL2		0x40000
167*4882a593Smuzhiyun #define DHD_PNO_VAL		0x80000
168*4882a593Smuzhiyun #define DHD_RTT_VAL		0x100000
169*4882a593Smuzhiyun #define DHD_MSGTRACE_VAL	0x200000
170*4882a593Smuzhiyun #define DHD_FWLOG_VAL		0x400000
171*4882a593Smuzhiyun #define DHD_DBGIF_VAL		0x800000
172*4882a593Smuzhiyun #ifdef DHD_PCIE_NATIVE_RUNTIMEPM
173*4882a593Smuzhiyun #define DHD_RPM_VAL		0x1000000
174*4882a593Smuzhiyun #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
175*4882a593Smuzhiyun #define DHD_PKT_MON_VAL		0x2000000
176*4882a593Smuzhiyun #define DHD_PKT_MON_DUMP_VAL	0x4000000
177*4882a593Smuzhiyun #define DHD_ERROR_MEM_VAL	0x8000000
178*4882a593Smuzhiyun #define DHD_DNGL_IOVAR_SET_VAL	0x10000000 /**< logs the setting of dongle iovars */
179*4882a593Smuzhiyun #define DHD_LPBKDTDUMP_VAL	0x20000000
180*4882a593Smuzhiyun #define DHD_PRSRV_MEM_VAL	0x40000000
181*4882a593Smuzhiyun #define DHD_IOVAR_MEM_VAL	0x80000000
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun #ifdef SDTEST
184*4882a593Smuzhiyun /* For pktgen iovar */
185*4882a593Smuzhiyun typedef struct dhd_pktgen {
186*4882a593Smuzhiyun 	uint32 version;		/* To allow structure change tracking */
187*4882a593Smuzhiyun 	uint32 freq;		/* Max ticks between tx/rx attempts */
188*4882a593Smuzhiyun 	uint32 count;		/* Test packets to send/rcv each attempt */
189*4882a593Smuzhiyun 	uint32 print;		/* Print counts every <print> attempts */
190*4882a593Smuzhiyun 	uint32 total;		/* Total packets (or bursts) */
191*4882a593Smuzhiyun 	uint32 minlen;		/* Minimum length of packets to send */
192*4882a593Smuzhiyun 	uint32 maxlen;		/* Maximum length of packets to send */
193*4882a593Smuzhiyun 	uint32 numsent;		/* Count of test packets sent */
194*4882a593Smuzhiyun 	uint32 numrcvd;		/* Count of test packets received */
195*4882a593Smuzhiyun 	uint32 numfail;		/* Count of test send failures */
196*4882a593Smuzhiyun 	uint32 mode;		/* Test mode (type of test packets) */
197*4882a593Smuzhiyun 	uint32 stop;		/* Stop after this many tx failures */
198*4882a593Smuzhiyun } dhd_pktgen_t;
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun /* Version in case structure changes */
201*4882a593Smuzhiyun #define DHD_PKTGEN_VERSION 2
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun /* Type of test packets to use */
204*4882a593Smuzhiyun #define DHD_PKTGEN_ECHO		1 /* Send echo requests */
205*4882a593Smuzhiyun #define DHD_PKTGEN_SEND 	2 /* Send discard packets */
206*4882a593Smuzhiyun #define DHD_PKTGEN_RXBURST	3 /* Request dongle send N packets */
207*4882a593Smuzhiyun #define DHD_PKTGEN_RECV		4 /* Continuous rx from continuous tx dongle */
208*4882a593Smuzhiyun #endif /* SDTEST */
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun /* Enter idle immediately (no timeout) */
211*4882a593Smuzhiyun #define DHD_IDLE_IMMEDIATE	(-1)
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun /* Values for idleclock iovar: other values are the sd_divisor to use when idle */
214*4882a593Smuzhiyun #define DHD_IDLE_ACTIVE	0	/* Do not request any SD clock change when idle */
215*4882a593Smuzhiyun #define DHD_IDLE_STOP   (-1)	/* Request SD clock be stopped (and use SD1 mode) */
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun enum dhd_maclist_xtlv_type {
218*4882a593Smuzhiyun 	DHD_MACLIST_XTLV_R = 0x1,
219*4882a593Smuzhiyun 	DHD_MACLIST_XTLV_X = 0x2,
220*4882a593Smuzhiyun 	DHD_SVMPLIST_XTLV = 0x3
221*4882a593Smuzhiyun };
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun typedef struct _dhd_maclist_t {
224*4882a593Smuzhiyun 	uint16 version;		/* Version */
225*4882a593Smuzhiyun 	uint16 bytes_len;	/* Total bytes length of lists, XTLV headers and paddings */
226*4882a593Smuzhiyun 	uint8 plist[1];		/* Pointer to the first list */
227*4882a593Smuzhiyun } dhd_maclist_t;
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun typedef struct _dhd_pd11regs_param {
230*4882a593Smuzhiyun 	uint16 start_idx;
231*4882a593Smuzhiyun 	uint8 verbose;
232*4882a593Smuzhiyun 	uint8 pad;
233*4882a593Smuzhiyun 	uint8 plist[1];
234*4882a593Smuzhiyun } dhd_pd11regs_param;
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun typedef struct _dhd_pd11regs_buf {
237*4882a593Smuzhiyun 	uint16 idx;
238*4882a593Smuzhiyun 	uint8 pad[2];
239*4882a593Smuzhiyun 	uint8 pbuf[1];
240*4882a593Smuzhiyun } dhd_pd11regs_buf;
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun /* BT logging and memory dump */
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun #define BT_LOG_BUF_MAX_SIZE		(DHD_IOCTL_MAXLEN - (2 * sizeof(int)))
245*4882a593Smuzhiyun #define BT_LOG_BUF_NOT_AVAILABLE	0
246*4882a593Smuzhiyun #define BT_LOG_NEXT_BUF_NOT_AVAIL	1
247*4882a593Smuzhiyun #define BT_LOG_NEXT_BUF_AVAIL		2
248*4882a593Smuzhiyun #define BT_LOG_NOT_READY		3
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun typedef struct bt_log_buf_info {
251*4882a593Smuzhiyun 	int availability;
252*4882a593Smuzhiyun 	int size;
253*4882a593Smuzhiyun 	char buf[BT_LOG_BUF_MAX_SIZE];
254*4882a593Smuzhiyun } bt_log_buf_info_t;
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun /* request BT memory in chunks */
257*4882a593Smuzhiyun typedef struct bt_mem_req {
258*4882a593Smuzhiyun 	int offset;	/* offset from BT memory start */
259*4882a593Smuzhiyun 	int buf_size;	/* buffer size per chunk */
260*4882a593Smuzhiyun } bt_mem_req_t;
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun /* max dest supported */
263*4882a593Smuzhiyun #define DEBUG_BUF_DEST_MAX	4
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun /* debug buf dest stat */
266*4882a593Smuzhiyun typedef struct debug_buf_dest_stat {
267*4882a593Smuzhiyun 	uint32 stat[DEBUG_BUF_DEST_MAX];
268*4882a593Smuzhiyun } debug_buf_dest_stat_t;
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun #endif /* _dhdioctl_h_ */
271