1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Broadcom device-specific manifest constants. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Portions of this code are copyright (c) 2021 Cypress Semiconductor Corporation 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 1999-2017, Broadcom Corporation 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Unless you and Broadcom execute a separate written software license 9*4882a593Smuzhiyun * agreement governing use of this software, this software is licensed to you 10*4882a593Smuzhiyun * under the terms of the GNU General Public License version 2 (the "GPL"), 11*4882a593Smuzhiyun * available at http://www.broadcom.com/licenses/GPLv2.php, with the 12*4882a593Smuzhiyun * following added to such license: 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * As a special exception, the copyright holders of this software give you 15*4882a593Smuzhiyun * permission to link this software with independent modules, and to copy and 16*4882a593Smuzhiyun * distribute the resulting executable under terms of your choice, provided that 17*4882a593Smuzhiyun * you also meet, for each linked independent module, the terms and conditions of 18*4882a593Smuzhiyun * the license of that module. An independent module is a module which is not 19*4882a593Smuzhiyun * derived from this software. The special exception does not apply to any 20*4882a593Smuzhiyun * modifications of the software. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * Notwithstanding the above, under no circumstances may you combine this 23*4882a593Smuzhiyun * software in any way with any other Broadcom software provided under a license 24*4882a593Smuzhiyun * other than the GPL, without Broadcom's express prior written consent. 25*4882a593Smuzhiyun * 26*4882a593Smuzhiyun * 27*4882a593Smuzhiyun * <<Broadcom-WL-IPTag/Open:>> 28*4882a593Smuzhiyun * 29*4882a593Smuzhiyun * $Id: bcmdevs.h 701163 2017-05-23 22:21:03Z $ 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #ifndef _BCMDEVS_H 33*4882a593Smuzhiyun #define _BCMDEVS_H 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* PCI vendor IDs */ 36*4882a593Smuzhiyun #define VENDOR_EPIGRAM 0xfeda 37*4882a593Smuzhiyun #define VENDOR_BROADCOM 0x14e4 38*4882a593Smuzhiyun #define VENDOR_3COM 0x10b7 39*4882a593Smuzhiyun #define VENDOR_NETGEAR 0x1385 40*4882a593Smuzhiyun #define VENDOR_DIAMOND 0x1092 41*4882a593Smuzhiyun #define VENDOR_INTEL 0x8086 42*4882a593Smuzhiyun #define VENDOR_DELL 0x1028 43*4882a593Smuzhiyun #define VENDOR_HP 0x103c 44*4882a593Smuzhiyun #define VENDOR_HP_COMPAQ 0x0e11 45*4882a593Smuzhiyun #define VENDOR_APPLE 0x106b 46*4882a593Smuzhiyun #define VENDOR_SI_IMAGE 0x1095 /* Silicon Image, used by Arasan SDIO Host */ 47*4882a593Smuzhiyun #define VENDOR_BUFFALO 0x1154 /* Buffalo vendor id */ 48*4882a593Smuzhiyun #define VENDOR_TI 0x104c /* Texas Instruments */ 49*4882a593Smuzhiyun #define VENDOR_RICOH 0x1180 /* Ricoh */ 50*4882a593Smuzhiyun #define VENDOR_JMICRON 0x197b 51*4882a593Smuzhiyun #define VENDOR_CYPRESS 0x12BE 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* PCMCIA vendor IDs */ 54*4882a593Smuzhiyun #define VENDOR_BROADCOM_PCMCIA 0x02d0 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* SDIO vendor IDs */ 57*4882a593Smuzhiyun #define VENDOR_BROADCOM_SDIO 0x00BF 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* DONGLE VID/PIDs */ 60*4882a593Smuzhiyun #define CY_DNGL_VID 0x04b4 61*4882a593Smuzhiyun #define BCM_DNGL_VID 0x0a5c 62*4882a593Smuzhiyun #define BCM_DNGL_BL_PID_4328 0xbd12 63*4882a593Smuzhiyun #define BCM_DNGL_BL_PID_4322 0xbd13 64*4882a593Smuzhiyun #define BCM_DNGL_BL_PID_4319 0xbd16 65*4882a593Smuzhiyun #define BCM_DNGL_BL_PID_43236 0xbd17 66*4882a593Smuzhiyun #define BCM_DNGL_BL_PID_4332 0xbd18 67*4882a593Smuzhiyun #define BCM_DNGL_BL_PID_4360 0xbd1d 68*4882a593Smuzhiyun #define BCM_DNGL_BL_PID_43143 0xbd1e 69*4882a593Smuzhiyun #define BCM_DNGL_BL_PID_4335 0xbd20 70*4882a593Smuzhiyun #define BCM_DNGL_BL_PID_4350 0xbd23 71*4882a593Smuzhiyun #define BCM_DNGL_BL_PID_4345 0xbd24 72*4882a593Smuzhiyun #define BCM_DNGL_BL_PID_4349 0xbd25 73*4882a593Smuzhiyun #define BCM_DNGL_BL_PID_4354 0xbd26 74*4882a593Smuzhiyun #define BCM_DNGL_BL_PID_43569 0xbd27 75*4882a593Smuzhiyun #define BCM_DNGL_BL_PID_4373 0xbd29 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define BCM_DNGL_BDC_PID 0x0bdc 78*4882a593Smuzhiyun #define BCM_DNGL_JTAG_PID 0x4a44 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #ifdef DEPRECATED 81*4882a593Smuzhiyun #define BCM_DNGL_BL_PID_43239 0xbd1b 82*4882a593Smuzhiyun #define BCM_DNGL_BL_PID_4324 0xbd1c 83*4882a593Smuzhiyun #define BCM_DNGL_BL_PID_43242 0xbd1f 84*4882a593Smuzhiyun #define BCM_DNGL_BL_PID_43909 0xbd28 85*4882a593Smuzhiyun #endif // endif 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* PCI Device IDs */ 88*4882a593Smuzhiyun #ifdef DEPRECATED /* These products have been deprecated */ 89*4882a593Smuzhiyun #define BCM4210_DEVICE_ID 0x1072 /* never used */ 90*4882a593Smuzhiyun #define BCM4230_DEVICE_ID 0x1086 /* never used */ 91*4882a593Smuzhiyun #define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */ 92*4882a593Smuzhiyun #define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */ 93*4882a593Smuzhiyun #define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */ 94*4882a593Smuzhiyun #define BCM4211_DEVICE_ID 0x4211 95*4882a593Smuzhiyun #define BCM4231_DEVICE_ID 0x4231 96*4882a593Smuzhiyun #define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */ 97*4882a593Smuzhiyun #define BCM4311_D11G_ID 0x4311 /* 4311 802.11b/g id */ 98*4882a593Smuzhiyun #define BCM4311_D11DUAL_ID 0x4312 /* 4311 802.11a/b/g id */ 99*4882a593Smuzhiyun #define BCM4311_D11A_ID 0x4313 /* 4311 802.11a id */ 100*4882a593Smuzhiyun #define BCM4328_D11DUAL_ID 0x4314 /* 4328/4312 802.11a/g id */ 101*4882a593Smuzhiyun #define BCM4328_D11G_ID 0x4315 /* 4328/4312 802.11g id */ 102*4882a593Smuzhiyun #define BCM4328_D11A_ID 0x4316 /* 4328/4312 802.11a id */ 103*4882a593Smuzhiyun #define BCM4318_D11A_ID 0x431a /* 4318 802.11a id */ 104*4882a593Smuzhiyun #define BCM4325_D11DUAL_ID 0x431b /* 4325 802.11a/g id */ 105*4882a593Smuzhiyun #define BCM4325_D11G_ID 0x431c /* 4325 802.11g id */ 106*4882a593Smuzhiyun #define BCM4325_D11A_ID 0x431d /* 4325 802.11a id */ 107*4882a593Smuzhiyun #define BCM4306_UART_ID 0x4322 /* 4306 uart */ 108*4882a593Smuzhiyun #define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */ 109*4882a593Smuzhiyun #define BCM4306_D11G_ID2 0x4325 /* BCM4306_D11G_ID; INF w/loose binding war */ 110*4882a593Smuzhiyun #define BCM4321_D11N_ID 0x4328 /* 4321 802.11n dualband id */ 111*4882a593Smuzhiyun #define BCM4321_D11N2G_ID 0x4329 /* 4321 802.11n 2.4Ghz band id */ 112*4882a593Smuzhiyun #define BCM4321_D11N5G_ID 0x432a /* 4321 802.11n 5Ghz band id */ 113*4882a593Smuzhiyun #define BCM4322_D11N_ID 0x432b /* 4322 802.11n dualband device */ 114*4882a593Smuzhiyun #define BCM4322_D11N2G_ID 0x432c /* 4322 802.11n 2.4GHz device */ 115*4882a593Smuzhiyun #define BCM4322_D11N5G_ID 0x432d /* 4322 802.11n 5GHz device */ 116*4882a593Smuzhiyun #define BCM4329_D11N_ID 0x432e /* 4329 802.11n dualband device */ 117*4882a593Smuzhiyun #define BCM4329_D11N2G_ID 0x432f /* 4329 802.11n 2.4G device */ 118*4882a593Smuzhiyun #define BCM4329_D11N5G_ID 0x4330 /* 4329 802.11n 5G device */ 119*4882a593Smuzhiyun #define BCM4314_D11N2G_ID 0x4364 /* 4314 802.11n 2.4G device */ 120*4882a593Smuzhiyun #define BCM43143_D11N2G_ID 0x4366 /* 43143 802.11n 2.4G device */ 121*4882a593Smuzhiyun #define BCM4315_D11DUAL_ID 0x4334 /* 4315 802.11a/g id */ 122*4882a593Smuzhiyun #define BCM4315_D11G_ID 0x4335 /* 4315 802.11g id */ 123*4882a593Smuzhiyun #define BCM4315_D11A_ID 0x4336 /* 4315 802.11a id */ 124*4882a593Smuzhiyun #define BCM4319_D11N_ID 0x4337 /* 4319 802.11n dualband device */ 125*4882a593Smuzhiyun #define BCM4319_D11N2G_ID 0x4338 /* 4319 802.11n 2.4G device */ 126*4882a593Smuzhiyun #define BCM4319_D11N5G_ID 0x4339 /* 4319 802.11n 5G device */ 127*4882a593Smuzhiyun #define BCM43221_D11N2G_ID 0x4341 /* 43221 802.11n 2.4GHz device */ 128*4882a593Smuzhiyun #define BCM43222_D11N_ID 0x4350 /* 43222 802.11n dualband device */ 129*4882a593Smuzhiyun #define BCM43222_D11N2G_ID 0x4351 /* 43222 802.11n 2.4GHz device */ 130*4882a593Smuzhiyun #define BCM43222_D11N5G_ID 0x4352 /* 43222 802.11n 5GHz device */ 131*4882a593Smuzhiyun #define BCM43225_D11N2G_ID 0x4357 /* 43225 802.11n 2.4GHz device */ 132*4882a593Smuzhiyun #define BCM43226_D11N_ID 0x4354 /* 43226 802.11n dualband device */ 133*4882a593Smuzhiyun #define BCM43228_D11N5G_ID 0x435a /* 43228 802.11n 5GHz device */ 134*4882a593Smuzhiyun #define BCM43231_D11N2G_ID 0x4340 /* 43231 802.11n 2.4GHz device */ 135*4882a593Smuzhiyun #define BCM43237_D11N_ID 0x4355 /* 43237 802.11n dualband device */ 136*4882a593Smuzhiyun #define BCM43237_D11N5G_ID 0x4356 /* 43237 802.11n 5GHz device */ 137*4882a593Smuzhiyun #define BCM43239_D11N_ID 0x4370 /* 43239 802.11n dualband device */ 138*4882a593Smuzhiyun #define BCM4324_D11N_ID 0x4374 /* 4324 802.11n dualband device */ 139*4882a593Smuzhiyun #define BCM43242_D11N_ID 0x4367 /* 43242 802.11n dualband device */ 140*4882a593Smuzhiyun #define BCM43242_D11N2G_ID 0x4368 /* 43242 802.11n 2.4G device */ 141*4882a593Smuzhiyun #define BCM43242_D11N5G_ID 0x4369 /* 43242 802.11n 5G device */ 142*4882a593Smuzhiyun #define BCM4330_D11N_ID 0x4360 /* 4330 802.11n dualband device */ 143*4882a593Smuzhiyun #define BCM4330_D11N2G_ID 0x4361 /* 4330 802.11n 2.4G device */ 144*4882a593Smuzhiyun #define BCM4330_D11N5G_ID 0x4362 /* 4330 802.11n 5G device */ 145*4882a593Smuzhiyun #define BCM4334_D11N_ID 0x4380 /* 4334 802.11n dualband device */ 146*4882a593Smuzhiyun #define BCM4334_D11N2G_ID 0x4381 /* 4334 802.11n 2.4G device */ 147*4882a593Smuzhiyun #define BCM4334_D11N5G_ID 0x4382 /* 4334 802.11n 5G device */ 148*4882a593Smuzhiyun #define BCM43342_D11N_ID 0x4383 /* 43342 802.11n dualband device */ 149*4882a593Smuzhiyun #define BCM43342_D11N2G_ID 0x4384 /* 43342 802.11n 2.4G device */ 150*4882a593Smuzhiyun #define BCM43342_D11N5G_ID 0x4385 /* 43342 802.11n 5G device */ 151*4882a593Smuzhiyun #define BCM43341_D11N_ID 0x4386 /* 43341 802.11n dualband device */ 152*4882a593Smuzhiyun #define BCM43341_D11N2G_ID 0x4387 /* 43341 802.11n 2.4G device */ 153*4882a593Smuzhiyun #define BCM43341_D11N5G_ID 0x4388 /* 43341 802.11n 5G device */ 154*4882a593Smuzhiyun #define BCM4336_D11N_ID 0x4343 /* 4336 802.11n 2.4GHz device */ 155*4882a593Smuzhiyun #define BCM43362_D11N_ID 0x4363 /* 43362 802.11n 2.4GHz device */ 156*4882a593Smuzhiyun #define BCM43421_D11N_ID 0xA99D /* 43421 802.11n dualband device */ 157*4882a593Smuzhiyun #define BCM43909_D11AC_ID 0x43d0 /* 43909 802.11ac dualband device */ 158*4882a593Smuzhiyun #define BCM43909_D11AC2G_ID 0x43d1 /* 43909 802.11ac 2.4G device */ 159*4882a593Smuzhiyun #define BCM43909_D11AC5G_ID 0x43d2 /* 43909 802.11ac 5G device */ 160*4882a593Smuzhiyun #endif /* DEPRECATED */ 161*4882a593Smuzhiyun /* DEPRECATED but used */ 162*4882a593Smuzhiyun #define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */ 163*4882a593Smuzhiyun #define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */ 164*4882a593Smuzhiyun #define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */ 165*4882a593Smuzhiyun #define BCM43142_D11N2G_ID 0x4365 /* 43142 802.11n 2.4G device */ 166*4882a593Smuzhiyun #define BCM4313_D11N2G_ID 0x4727 /* 4313 802.11n 2.4G device */ 167*4882a593Smuzhiyun #define BCM4318_D11G_ID 0x4318 /* 4318 802.11b/g id */ 168*4882a593Smuzhiyun #define BCM4318_D11DUAL_ID 0x4319 /* 4318 802.11a/b/g id */ 169*4882a593Smuzhiyun #define BCM43224_D11N_ID 0x4353 /* 43224 802.11n dualband device */ 170*4882a593Smuzhiyun #define BCM43224_D11N_ID_VEN1 0x0576 /* Vendor specific 43224 802.11n db device */ 171*4882a593Smuzhiyun #define BCM43227_D11N2G_ID 0x4358 /* 43228 802.11n 2.4GHz device */ 172*4882a593Smuzhiyun #define BCM43228_D11N_ID 0x4359 /* 43228 802.11n DualBand device */ 173*4882a593Smuzhiyun #define BCM4331_D11N_ID 0x4331 /* 4331 802.11n dualband id */ 174*4882a593Smuzhiyun #define BCM4331_D11N2G_ID 0x4332 /* 4331 802.11n 2.4Ghz band id */ 175*4882a593Smuzhiyun #define BCM4331_D11N5G_ID 0x4333 /* 4331 802.11n 5Ghz band id */ 176*4882a593Smuzhiyun /* DEPRECATED */ 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun #define BCM43236_D11N_ID 0x4346 /* 43236 802.11n dualband device */ 179*4882a593Smuzhiyun #define BCM43236_D11N2G_ID 0x4347 /* 43236 802.11n 2.4GHz device */ 180*4882a593Smuzhiyun #define BCM43236_D11N5G_ID 0x4348 /* 43236 802.11n 5GHz device */ 181*4882a593Smuzhiyun #define BCM6362_D11N_ID 0x435f /* 6362 802.11n dualband device */ 182*4882a593Smuzhiyun #define BCM6362_D11N2G_ID 0x433f /* 6362 802.11n 2.4Ghz band id */ 183*4882a593Smuzhiyun #define BCM6362_D11N5G_ID 0x434f /* 6362 802.11n 5Ghz band id */ 184*4882a593Smuzhiyun #define BCM43217_D11N2G_ID 0x43a9 /* 43217 802.11n 2.4GHz device */ 185*4882a593Smuzhiyun #define BCM43131_D11N2G_ID 0x43aa /* 43131 802.11n 2.4GHz device */ 186*4882a593Smuzhiyun #define BCM4360_D11AC_ID 0x43a0 187*4882a593Smuzhiyun #define BCM4360_D11AC2G_ID 0x43a1 188*4882a593Smuzhiyun #define BCM4360_D11AC5G_ID 0x43a2 189*4882a593Smuzhiyun #define BCM4345_D11AC_ID 0x43ab /* 4345 802.11ac dualband device */ 190*4882a593Smuzhiyun #define BCM4345_D11AC2G_ID 0x43ac /* 4345 802.11ac 2.4G device */ 191*4882a593Smuzhiyun #define BCM4345_D11AC5G_ID 0x43ad /* 4345 802.11ac 5G device */ 192*4882a593Smuzhiyun #define BCM43455_D11AC_ID 0x43e3 /* 43455 802.11ac dualband device */ 193*4882a593Smuzhiyun #define BCM43455_D11AC2G_ID 0x43e4 /* 43455 802.11ac 2.4G device */ 194*4882a593Smuzhiyun #define BCM43455_D11AC5G_ID 0x43e5 /* 43455 802.11ac 5G device */ 195*4882a593Smuzhiyun #define BCM4335_D11AC_ID 0x43ae 196*4882a593Smuzhiyun #define BCM4335_D11AC2G_ID 0x43af 197*4882a593Smuzhiyun #define BCM4335_D11AC5G_ID 0x43b0 198*4882a593Smuzhiyun #define BCM4352_D11AC_ID 0x43b1 /* 4352 802.11ac dualband device */ 199*4882a593Smuzhiyun #define BCM4352_D11AC2G_ID 0x43b2 /* 4352 802.11ac 2.4G device */ 200*4882a593Smuzhiyun #define BCM4352_D11AC5G_ID 0x43b3 /* 4352 802.11ac 5G device */ 201*4882a593Smuzhiyun #define BCM43602_D11AC_ID 0x43ba /* ac dualband PCI devid SPROM programmed */ 202*4882a593Smuzhiyun #define BCM43602_D11AC2G_ID 0x43bb /* 43602 802.11ac 2.4G device */ 203*4882a593Smuzhiyun #define BCM43602_D11AC5G_ID 0x43bc /* 43602 802.11ac 5G device */ 204*4882a593Smuzhiyun #define BCM4349_D11AC_ID 0x4349 /* 4349 802.11ac dualband device */ 205*4882a593Smuzhiyun #define BCM4349_D11AC2G_ID 0x43dd /* 4349 802.11ac 2.4G device */ 206*4882a593Smuzhiyun #define BCM4349_D11AC5G_ID 0x43de /* 4349 802.11ac 5G device */ 207*4882a593Smuzhiyun #define BCM53573_D11AC_ID 0x43b4 /* 53573 802.11ac dualband device */ 208*4882a593Smuzhiyun #define BCM53573_D11AC2G_ID 0x43b5 /* 53573 802.11ac 2.4G device */ 209*4882a593Smuzhiyun #define BCM53573_D11AC5G_ID 0x43b6 /* 53573 802.11ac 5G device */ 210*4882a593Smuzhiyun #define BCM47189_D11AC_ID 0x43c6 /* 47189 802.11ac dualband device */ 211*4882a593Smuzhiyun #define BCM47189_D11AC2G_ID 0x43c7 /* 47189 802.11ac 2.4G device */ 212*4882a593Smuzhiyun #define BCM47189_D11AC5G_ID 0x43c8 /* 47189 802.11ac 5G device */ 213*4882a593Smuzhiyun #define BCM4355_D11AC_ID 0x43dc /* 4355 802.11ac dualband device */ 214*4882a593Smuzhiyun #define BCM4355_D11AC2G_ID 0x43fc /* 4355 802.11ac 2.4G device */ 215*4882a593Smuzhiyun #define BCM4355_D11AC5G_ID 0x43fd /* 4355 802.11ac 5G device */ 216*4882a593Smuzhiyun #define BCM4359_D11AC_ID 0x43ef /* 4359 802.11ac dualband device */ 217*4882a593Smuzhiyun #define BCM4359_D11AC2G_ID 0x43fe /* 4359 802.11ac 2.4G device */ 218*4882a593Smuzhiyun #define BCM4359_D11AC5G_ID 0x43ff /* 4359 802.11ac 5G device */ 219*4882a593Smuzhiyun #define BCM43596_D11AC_ID 0x4415 /* 43596 802.11ac dualband device */ 220*4882a593Smuzhiyun #define BCM43596_D11AC2G_ID 0x4416 /* 43596 802.11ac 2.4G device */ 221*4882a593Smuzhiyun #define BCM43596_D11AC5G_ID 0x4417 /* 43596 802.11ac 5G device */ 222*4882a593Smuzhiyun #define BCM43597_D11AC_ID 0x441c /* 43597 802.11ac dualband device */ 223*4882a593Smuzhiyun #define BCM43597_D11AC2G_ID 0x441d /* 43597 802.11ac 2.4G device */ 224*4882a593Smuzhiyun #define BCM43597_D11AC5G_ID 0x441e /* 43597 802.11ac 5G device */ 225*4882a593Smuzhiyun #define BCM43012_D11N_ID 0xA804 /* 43012 802.11n dualband device */ 226*4882a593Smuzhiyun #define BCM43012_D11N2G_ID 0xA805 /* 43012 802.11n 2.4G device */ 227*4882a593Smuzhiyun #define BCM43012_D11N5G_ID 0xA806 /* 43012 802.11n 5G device */ 228*4882a593Smuzhiyun #define BCM43014_D11N_ID 0x4495 /* 43014 802.11n dualband device */ 229*4882a593Smuzhiyun #define BCM43014_D11N2G_ID 0x4496 /* 43014 802.11n 2.4G device */ 230*4882a593Smuzhiyun #define BCM43014_D11N5G_ID 0x4497 /* 43014 802.11n 5G device */ 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun /* PCI Subsystem ID */ 233*4882a593Smuzhiyun #define BCM94313HMGBL_SSID_VEN1 0x0608 234*4882a593Smuzhiyun #define BCM94313HMG_SSID_VEN1 0x0609 235*4882a593Smuzhiyun #define BCM943142HM_SSID_VEN1 0x0611 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun #define BCM4350_D11AC_ID 0x43a3 238*4882a593Smuzhiyun #define BCM4350_D11AC2G_ID 0x43a4 239*4882a593Smuzhiyun #define BCM4350_D11AC5G_ID 0x43a5 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun #define BCM43556_D11AC_ID 0x43b7 242*4882a593Smuzhiyun #define BCM43556_D11AC2G_ID 0x43b8 243*4882a593Smuzhiyun #define BCM43556_D11AC5G_ID 0x43b9 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun #define BCM43558_D11AC_ID 0x43c0 246*4882a593Smuzhiyun #define BCM43558_D11AC2G_ID 0x43c1 247*4882a593Smuzhiyun #define BCM43558_D11AC5G_ID 0x43c2 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun #define BCM43566_D11AC_ID 0x43d3 250*4882a593Smuzhiyun #define BCM43566_D11AC2G_ID 0x43d4 251*4882a593Smuzhiyun #define BCM43566_D11AC5G_ID 0x43d5 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun #define BCM43568_D11AC_ID 0x43d6 254*4882a593Smuzhiyun #define BCM43568_D11AC2G_ID 0x43d7 255*4882a593Smuzhiyun #define BCM43568_D11AC5G_ID 0x43d8 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun #define BCM43569_D11AC_ID 0x43d9 258*4882a593Smuzhiyun #define BCM43569_D11AC2G_ID 0x43da 259*4882a593Smuzhiyun #define BCM43569_D11AC5G_ID 0x43db 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun #define BCM43570_D11AC_ID 0x43d9 262*4882a593Smuzhiyun #define BCM43570_D11AC2G_ID 0x43da 263*4882a593Smuzhiyun #define BCM43570_D11AC5G_ID 0x43db 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun #define BCM4354_D11AC_ID 0x43df /* 4354 802.11ac dualband device */ 266*4882a593Smuzhiyun #define BCM4354_D11AC2G_ID 0x43e0 /* 4354 802.11ac 2.4G device */ 267*4882a593Smuzhiyun #define BCM4354_D11AC5G_ID 0x43e1 /* 4354 802.11ac 5G device */ 268*4882a593Smuzhiyun #define BCM43430_D11N2G_ID 0x43e2 /* 43430 802.11n 2.4G device */ 269*4882a593Smuzhiyun #define BCM43018_D11N2G_ID 0x441b /* 43018 802.11n 2.4G device */ 270*4882a593Smuzhiyun 271*4882a593Smuzhiyun #define BCM4347_D11AC_ID 0x440a /* 4347 802.11ac dualband device */ 272*4882a593Smuzhiyun #define BCM4347_D11AC2G_ID 0x440b /* 4347 802.11ac 2.4G device */ 273*4882a593Smuzhiyun #define BCM4347_D11AC5G_ID 0x440c /* 4347 802.11ac 5G device */ 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun #ifdef CHIPS_CUSTOMER_HW6 276*4882a593Smuzhiyun #define BCM4376_D11AC_ID 0x4435 /* 4376 802.11ac dualband device */ 277*4882a593Smuzhiyun #define BCM4376_D11AC2G_ID 0x4436 /* 4376 802.11ac 2.4G device */ 278*4882a593Smuzhiyun #define BCM4376_D11AC5G_ID 0x4437 /* 4376 802.11ac 5G device */ 279*4882a593Smuzhiyun 280*4882a593Smuzhiyun #define BCM4378_D11AC_ID 0x4425 /* 4378 802.11ac dualband device */ 281*4882a593Smuzhiyun #define BCM4378_D11AC2G_ID 0x4426 /* 4378 802.11ac 2.4G device */ 282*4882a593Smuzhiyun #define BCM4378_D11AC5G_ID 0x4427 /* 4378 802.11ac 5G device */ 283*4882a593Smuzhiyun #endif /* CHIPS_CUSTOMER_HW6 */ 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun #define BCM4361_D11AC_ID 0x441f /* 4361 802.11ac dualband device */ 286*4882a593Smuzhiyun #define BCM4361_D11AC2G_ID 0x4420 /* 4361 802.11ac 2.4G device */ 287*4882a593Smuzhiyun #define BCM4361_D11AC5G_ID 0x4421 /* 4361 802.11ac 5G device */ 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun #define BCM4362_D11AX_ID 0x4490 /* 4362 802.11ax dualband device */ 290*4882a593Smuzhiyun #define BCM4362_D11AX2G_ID 0x4491 /* 4362 802.11ax 2.4G device */ 291*4882a593Smuzhiyun #define BCM4362_D11AX5G_ID 0x4492 /* 4362 802.11ax 5G device */ 292*4882a593Smuzhiyun #define BCM43751_D11AX_ID 0x4490 /* 43751 802.11ax dualband device */ 293*4882a593Smuzhiyun #define BCM43751_D11AX2G_ID 0x4491 /* 43751 802.11ax 2.4G device */ 294*4882a593Smuzhiyun #define BCM43751_D11AX5G_ID 0x4492 /* 43751 802.11ax 5G device */ 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun #define BCM4364_D11AC_ID 0x4464 /* 4364 802.11ac dualband device */ 297*4882a593Smuzhiyun #define BCM4364_D11AC2G_ID 0x446a /* 4364 802.11ac 2.4G device */ 298*4882a593Smuzhiyun #define BCM4364_D11AC5G_ID 0x446b /* 4364 802.11ac 5G device */ 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun #define BCM4365_D11AC_ID 0x43ca 301*4882a593Smuzhiyun #define BCM4365_D11AC2G_ID 0x43cb 302*4882a593Smuzhiyun #define BCM4365_D11AC5G_ID 0x43cc 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun #define BCM4366_D11AC_ID 0x43c3 305*4882a593Smuzhiyun #define BCM4366_D11AC2G_ID 0x43c4 306*4882a593Smuzhiyun #define BCM4366_D11AC5G_ID 0x43c5 307*4882a593Smuzhiyun 308*4882a593Smuzhiyun /* TBD change below values */ 309*4882a593Smuzhiyun #define BCM4369_D11AX_ID 0x4470 /* 4369 802.11ax dualband device */ 310*4882a593Smuzhiyun #define BCM4369_D11AX2G_ID 0x4471 /* 4369 802.11ax 2.4G device */ 311*4882a593Smuzhiyun #define BCM4369_D11AX5G_ID 0x4472 /* 4369 802.11ax 5G device */ 312*4882a593Smuzhiyun 313*4882a593Smuzhiyun #define BCM4375_D11AX_ID 0x4475 /* 4375 802.11ax dualband device */ 314*4882a593Smuzhiyun #define BCM4375_D11AX2G_ID 0x4476 /* 4375 802.11ax 2.4G device */ 315*4882a593Smuzhiyun #define BCM4375_D11AX5G_ID 0x4477 /* 4375 802.11ax 5G device */ 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun #ifdef CHIPS_CUSTOMER_HW6 318*4882a593Smuzhiyun #define BCM4377_D11AX_ID 0x4480 /* 4377 802.11ax dualband device */ 319*4882a593Smuzhiyun #define BCM4377_D11AX2G_ID 0x4481 /* 4377 802.11ax 2.4G device */ 320*4882a593Smuzhiyun #define BCM4377_D11AX5G_ID 0x4482 /* 4377 802.11ax 5G device */ 321*4882a593Smuzhiyun 322*4882a593Smuzhiyun #define BCM4377_M_D11AX_ID 0x4488 /* 4377 802.11ax dualband device with multifunction */ 323*4882a593Smuzhiyun 324*4882a593Smuzhiyun /* TBD change below values */ 325*4882a593Smuzhiyun #define BCM4367_D11AC_ID 0x4422 326*4882a593Smuzhiyun #define BCM4367_D11AC2G_ID 0x4423 327*4882a593Smuzhiyun #define BCM4367_D11AC5G_ID 0x4424 328*4882a593Smuzhiyun #endif /* CHIPS_CUSTOMER_HW6 */ 329*4882a593Smuzhiyun 330*4882a593Smuzhiyun #ifdef CHIPS_CUSTOMER_HW6 331*4882a593Smuzhiyun #define BCM4368_D11AC_ID 0x442f 332*4882a593Smuzhiyun #define BCM4368_D11AC2G_ID 0x4430 333*4882a593Smuzhiyun #define BCM4368_D11AC5G_ID 0x4431 334*4882a593Smuzhiyun #define BCM4368_D11ACBT_ID 0x5f30 335*4882a593Smuzhiyun #endif /* CHIPS_CUSTOMER_HW6 */ 336*4882a593Smuzhiyun 337*4882a593Smuzhiyun #define BCM43349_D11N_ID 0x43e6 /* 43349 802.11n dualband id */ 338*4882a593Smuzhiyun #define BCM43349_D11N2G_ID 0x43e7 /* 43349 802.11n 2.4Ghz band id */ 339*4882a593Smuzhiyun #define BCM43349_D11N5G_ID 0x43e8 /* 43349 802.11n 5Ghz band id */ 340*4882a593Smuzhiyun 341*4882a593Smuzhiyun #define BCM4358_D11AC_ID 0x43e9 /* 4358 802.11ac dualband device */ 342*4882a593Smuzhiyun #define BCM4358_D11AC2G_ID 0x43ea /* 4358 802.11ac 2.4G device */ 343*4882a593Smuzhiyun #define BCM4358_D11AC5G_ID 0x43eb /* 4358 802.11ac 5G device */ 344*4882a593Smuzhiyun 345*4882a593Smuzhiyun #define BCM4356_D11AC_ID 0x43ec /* 4356 802.11ac dualband device */ 346*4882a593Smuzhiyun #define BCM4356_D11AC2G_ID 0x43ed /* 4356 802.11ac 2.4G device */ 347*4882a593Smuzhiyun #define BCM4356_D11AC5G_ID 0x43ee /* 4356 802.11ac 5G device */ 348*4882a593Smuzhiyun 349*4882a593Smuzhiyun #define BCM4371_D11AC_ID 0x440d /* 4371 802.11ac dualband device */ 350*4882a593Smuzhiyun #define BCM4371_D11AC2G_ID 0x440e /* 4371 802.11ac 2.4G device */ 351*4882a593Smuzhiyun #define BCM4371_D11AC5G_ID 0x440f /* 4371 802.11ac 5G device */ 352*4882a593Smuzhiyun #define BCM7271_D11AC_ID 0x4410 /* 7271 802.11ac dualband device */ 353*4882a593Smuzhiyun #define BCM7271_D11AC2G_ID 0x4411 /* 7271 802.11ac 2.4G device */ 354*4882a593Smuzhiyun #define BCM7271_D11AC5G_ID 0x4412 /* 7271 802.11ac 5G device */ 355*4882a593Smuzhiyun 356*4882a593Smuzhiyun #define BCM4373_D11AC_ID 0x4418 /* 4373 802.11ac dualband device */ 357*4882a593Smuzhiyun #define BCM4373_D11AC2G_ID 0x4419 /* 4373 802.11ac 2.4G device */ 358*4882a593Smuzhiyun #define BCM4373_D11AC5G_ID 0x441a /* 4373 802.11ac 5G device */ 359*4882a593Smuzhiyun 360*4882a593Smuzhiyun #define CYW55560_WLAN_ID 0xBD31 /* CYW55560 802.11ax WLAN device ID */ 361*4882a593Smuzhiyun #define CYW55560_BT_ID 0xBD37 /* CYW55560 802.11ax BT device ID */ 362*4882a593Smuzhiyun 363*4882a593Smuzhiyun #define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */ 364*4882a593Smuzhiyun #define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */ 365*4882a593Smuzhiyun #define FPGA_JTAGM_ID 0x43f0 /* FPGA jtagm device id */ 366*4882a593Smuzhiyun #define BCM_JTAGM_ID 0x43f1 /* BCM jtagm device id */ 367*4882a593Smuzhiyun #define SDIOH_FPGA_ID 0x43f2 /* sdio host fpga */ 368*4882a593Smuzhiyun #define BCM_SDIOH_ID 0x43f3 /* BCM sdio host id */ 369*4882a593Smuzhiyun #define SDIOD_FPGA_ID 0x43f4 /* sdio device fpga */ 370*4882a593Smuzhiyun #define SPIH_FPGA_ID 0x43f5 /* PCI SPI Host Controller FPGA */ 371*4882a593Smuzhiyun #define BCM_SPIH_ID 0x43f6 /* Synopsis SPI Host Controller */ 372*4882a593Smuzhiyun #define MIMO_FPGA_ID 0x43f8 /* FPGA mimo minimacphy device id */ 373*4882a593Smuzhiyun #define BCM_JTAGM2_ID 0x43f9 /* BCM alternate jtagm device id */ 374*4882a593Smuzhiyun #define SDHCI_FPGA_ID 0x43fa /* Standard SDIO Host Controller FPGA */ 375*4882a593Smuzhiyun #define BCM4402_ENET_ID 0x4402 /* 4402 enet */ 376*4882a593Smuzhiyun #define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */ 377*4882a593Smuzhiyun #define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */ 378*4882a593Smuzhiyun #define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */ 379*4882a593Smuzhiyun #define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */ 380*4882a593Smuzhiyun #define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */ 381*4882a593Smuzhiyun #define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */ 382*4882a593Smuzhiyun #define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */ 383*4882a593Smuzhiyun #define BCM47XX_AUDIO_ID 0x4711 /* 47xx audio codec */ 384*4882a593Smuzhiyun #define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */ 385*4882a593Smuzhiyun #define BCM47XX_ENET_ID 0x4713 /* 47xx enet */ 386*4882a593Smuzhiyun #define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */ 387*4882a593Smuzhiyun #define BCM47XX_GMAC_ID 0x4715 /* 47xx Unimac based GbE */ 388*4882a593Smuzhiyun #define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */ 389*4882a593Smuzhiyun #define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */ 390*4882a593Smuzhiyun #define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */ 391*4882a593Smuzhiyun #define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */ 392*4882a593Smuzhiyun #define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */ 393*4882a593Smuzhiyun #define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */ 394*4882a593Smuzhiyun #define BCM47XX_ATA100_ID 0x471d /* 47xx parallel ATA */ 395*4882a593Smuzhiyun #define BCM47XX_SATAXOR_ID 0x471e /* 47xx serial ATA & XOR DMA */ 396*4882a593Smuzhiyun #define BCM47XX_GIGETH_ID 0x471f /* 47xx GbE (5700) */ 397*4882a593Smuzhiyun #ifdef DEPRECATED /* These products have been deprecated */ 398*4882a593Smuzhiyun #define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */ 399*4882a593Smuzhiyun #define BCM4716_DEVICE_ID 0x4722 /* 4716 base devid */ 400*4882a593Smuzhiyun #endif /* DEPRECATED */ 401*4882a593Smuzhiyun #define BCM47XX_USB30H_ID 0x472a /* 47xx usb 3.0 host */ 402*4882a593Smuzhiyun #define BCM47XX_USB30D_ID 0x472b /* 47xx usb 3.0 device */ 403*4882a593Smuzhiyun #define BCM47XX_USBHUB_ID 0x472c /* 47xx usb hub */ 404*4882a593Smuzhiyun #define BCM47XX_SMBUS_EMU_ID 0x47fe /* 47xx emulated SMBus device */ 405*4882a593Smuzhiyun #define BCM47XX_XOR_EMU_ID 0x47ff /* 47xx emulated XOR engine */ 406*4882a593Smuzhiyun #define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */ 407*4882a593Smuzhiyun #define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */ 408*4882a593Smuzhiyun #define JINVANI_SDIOH_ID 0x4743 /* Jinvani SDIO Gold Host */ 409*4882a593Smuzhiyun #define BCM27XX_SDIOH_ID 0x2702 /* BCM27xx Standard SDIO Host */ 410*4882a593Smuzhiyun #define PCIXX21_FLASHMEDIA_ID 0x803b /* TI PCI xx21 Standard Host Controller */ 411*4882a593Smuzhiyun #define PCIXX21_SDIOH_ID 0x803c /* TI PCI xx21 Standard Host Controller */ 412*4882a593Smuzhiyun #define R5C822_SDIOH_ID 0x0822 /* Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host */ 413*4882a593Smuzhiyun #define JMICRON_SDIOH_ID 0x2381 /* JMicron Standard SDIO Host Controller */ 414*4882a593Smuzhiyun 415*4882a593Smuzhiyun #define BCM43452_D11AC_ID 0x47ab /* 43452 802.11ac dualband device */ 416*4882a593Smuzhiyun #define BCM43452_D11AC2G_ID 0x47ac /* 43452 802.11ac 2.4G device */ 417*4882a593Smuzhiyun #define BCM43452_D11AC5G_ID 0x47ad /* 43452 802.11ac 5G device */ 418*4882a593Smuzhiyun 419*4882a593Smuzhiyun /* Chip IDs */ 420*4882a593Smuzhiyun #ifdef DEPRECATED /* These products have been deprecated */ 421*4882a593Smuzhiyun #define BCM4306_CHIP_ID 0x4306 /* 4306 chipcommon chipid */ 422*4882a593Smuzhiyun #define BCM4311_CHIP_ID 0x4311 /* 4311 PCIe 802.11a/b/g */ 423*4882a593Smuzhiyun #define BCM43111_CHIP_ID 43111 /* 43111 chipcommon chipid (OTP chipid) */ 424*4882a593Smuzhiyun #define BCM43112_CHIP_ID 43112 /* 43112 chipcommon chipid (OTP chipid) */ 425*4882a593Smuzhiyun #define BCM4312_CHIP_ID 0x4312 /* 4312 chipcommon chipid */ 426*4882a593Smuzhiyun #define BCM4314_CHIP_ID 0x4314 /* 4314 chipcommon chipid */ 427*4882a593Smuzhiyun #define BCM43142_CHIP_ID 43142 /* 43142 chipcommon chipid */ 428*4882a593Smuzhiyun #define BCM43143_CHIP_ID 43143 /* 43143 chipcommon chipid */ 429*4882a593Smuzhiyun #define BCM4313_CHIP_ID 0x4313 /* 4313 chip id */ 430*4882a593Smuzhiyun #define BCM4315_CHIP_ID 0x4315 /* 4315 chip id */ 431*4882a593Smuzhiyun #define BCM4318_CHIP_ID 0x4318 /* 4318 chipcommon chipid */ 432*4882a593Smuzhiyun #define BCM4319_CHIP_ID 0x4319 /* 4319 chip id */ 433*4882a593Smuzhiyun #define BCM4320_CHIP_ID 0x4320 /* 4320 chipcommon chipid */ 434*4882a593Smuzhiyun #define BCM4321_CHIP_ID 0x4321 /* 4321 chipcommon chipid */ 435*4882a593Smuzhiyun #define BCM4322_CHIP_ID 0x4322 /* 4322 chipcommon chipid */ 436*4882a593Smuzhiyun #define BCM43221_CHIP_ID 43221 /* 43221 chipcommon chipid (OTP chipid) */ 437*4882a593Smuzhiyun #define BCM43222_CHIP_ID 43222 /* 43222 chipcommon chipid */ 438*4882a593Smuzhiyun #define BCM43224_CHIP_ID 43224 /* 43224 chipcommon chipid */ 439*4882a593Smuzhiyun #define BCM43225_CHIP_ID 43225 /* 43225 chipcommon chipid */ 440*4882a593Smuzhiyun #define BCM43226_CHIP_ID 43226 /* 43226 chipcommon chipid */ 441*4882a593Smuzhiyun #define BCM43227_CHIP_ID 43227 /* 43227 chipcommon chipid */ 442*4882a593Smuzhiyun #define BCM43228_CHIP_ID 43228 /* 43228 chipcommon chipid */ 443*4882a593Smuzhiyun #define BCM43231_CHIP_ID 43231 /* 43231 chipcommon chipid (OTP chipid) */ 444*4882a593Smuzhiyun #define BCM43237_CHIP_ID 43237 /* 43237 chipcommon chipid */ 445*4882a593Smuzhiyun #define BCM43239_CHIP_ID 43239 /* 43239 chipcommon chipid */ 446*4882a593Smuzhiyun #define BCM4324_CHIP_ID 0x4324 /* 4324 chipcommon chipid */ 447*4882a593Smuzhiyun #define BCM43242_CHIP_ID 43242 /* 43242 chipcommon chipid */ 448*4882a593Smuzhiyun #define BCM43243_CHIP_ID 43243 /* 43243 chipcommon chipid */ 449*4882a593Smuzhiyun #define BCM4325_CHIP_ID 0x4325 /* 4325 chip id */ 450*4882a593Smuzhiyun #define BCM4328_CHIP_ID 0x4328 /* 4328 chip id */ 451*4882a593Smuzhiyun #define BCM4329_CHIP_ID 0x4329 /* 4329 chipcommon chipid */ 452*4882a593Smuzhiyun #define BCM4331_CHIP_ID 0x4331 /* 4331 chipcommon chipid */ 453*4882a593Smuzhiyun #define BCM4334_CHIP_ID 0x4334 /* 4334 chipcommon chipid */ 454*4882a593Smuzhiyun #define BCM43349_CHIP_ID 43349 /* 43349(0xA955) chipcommon chipid */ 455*4882a593Smuzhiyun #define BCM43340_CHIP_ID 43340 /* 43340 chipcommon chipid */ 456*4882a593Smuzhiyun #define BCM43341_CHIP_ID 43341 /* 43341 chipcommon chipid */ 457*4882a593Smuzhiyun #define BCM43342_CHIP_ID 43342 /* 43342 chipcommon chipid */ 458*4882a593Smuzhiyun #define BCM4342_CHIP_ID 4342 /* 4342 chipcommon chipid (OTP, RBBU) */ 459*4882a593Smuzhiyun #define BCM43420_CHIP_ID 43420 /* 43420 chipcommon chipid (OTP, RBBU) */ 460*4882a593Smuzhiyun #define BCM43421_CHIP_ID 43421 /* 43224 chipcommon chipid (OTP, RBBU) */ 461*4882a593Smuzhiyun #define BCM43431_CHIP_ID 43431 /* 4331 chipcommon chipid (OTP, RBBU) */ 462*4882a593Smuzhiyun #define BCM43909_CHIP_ID 0xab85 /* 43909 chipcommon chipid */ 463*4882a593Smuzhiyun #define BCM4712_CHIP_ID 0x4712 /* 4712 chipcommon chipid */ 464*4882a593Smuzhiyun #define BCM4716_CHIP_ID 0x4716 /* 4716 chipcommon chipid */ 465*4882a593Smuzhiyun #define BCM4748_CHIP_ID 0x4748 /* 4716 chipcommon chipid (OTP, RBBU) */ 466*4882a593Smuzhiyun #endif /* DEPRECATED */ 467*4882a593Smuzhiyun 468*4882a593Smuzhiyun /* DEPRECATED but still referenced in components - start */ 469*4882a593Smuzhiyun #define BCM47162_CHIP_ID 47162 /* 47162 chipcommon chipid */ 470*4882a593Smuzhiyun #define BCM5354_CHIP_ID 0x5354 /* 5354 chipcommon chipid */ 471*4882a593Smuzhiyun /* DEPRECATED but still referenced in components - end */ 472*4882a593Smuzhiyun 473*4882a593Smuzhiyun #define BCM43217_CHIP_ID 43217 /* 43217 chip id (OTP chipid) */ 474*4882a593Smuzhiyun #define BCM43131_CHIP_ID 43131 /* 43131 chip id (OTP chipid) */ 475*4882a593Smuzhiyun #define BCM43234_CHIP_ID 43234 /* 43234 chipcommon chipid */ 476*4882a593Smuzhiyun #define BCM43235_CHIP_ID 43235 /* 43235 chipcommon chipid */ 477*4882a593Smuzhiyun #define BCM43236_CHIP_ID 43236 /* 43236 chipcommon chipid */ 478*4882a593Smuzhiyun #define BCM43238_CHIP_ID 43238 /* 43238 chipcommon chipid */ 479*4882a593Smuzhiyun #define BCM43428_CHIP_ID 43428 /* 43228 chipcommon chipid (OTP, RBBU) */ 480*4882a593Smuzhiyun #define BCM43460_CHIP_ID 43460 /* 4360 chipcommon chipid (OTP, RBBU) */ 481*4882a593Smuzhiyun #define BCM43465_CHIP_ID 43465 /* 4366 chipcommon chipid (OTP, RBBU) */ 482*4882a593Smuzhiyun #define BCM43525_CHIP_ID 43525 /* 4365 chipcommon chipid (OTP, RBBU) */ 483*4882a593Smuzhiyun #define BCM47452_CHIP_ID 47452 /* 53573 chipcommon chipid (OTP, RBBU) */ 484*4882a593Smuzhiyun #define BCM6362_CHIP_ID 0x6362 /* 6362 chipcommon chipid */ 485*4882a593Smuzhiyun #define BCM4335_CHIP_ID 0x4335 /* 4335 chipcommon chipid */ 486*4882a593Smuzhiyun #define BCM4339_CHIP_ID 0x4339 /* 4339 chipcommon chipid */ 487*4882a593Smuzhiyun #define BCM4360_CHIP_ID 0x4360 /* 4360 chipcommon chipid */ 488*4882a593Smuzhiyun #define BCM4364_CHIP_ID 0x4364 /* 4364 chipcommon chipid */ 489*4882a593Smuzhiyun #define BCM4352_CHIP_ID 0x4352 /* 4352 chipcommon chipid */ 490*4882a593Smuzhiyun #define BCM43526_CHIP_ID 0xAA06 491*4882a593Smuzhiyun #define BCM4350_CHIP_ID 0x4350 /* 4350 chipcommon chipid */ 492*4882a593Smuzhiyun #define BCM4354_CHIP_ID 0x4354 /* 4354 chipcommon chipid */ 493*4882a593Smuzhiyun #define BCM4356_CHIP_ID 0x4356 /* 4356 chipcommon chipid */ 494*4882a593Smuzhiyun #define BCM4371_CHIP_ID 0x4371 /* 4371 chipcommon chipid */ 495*4882a593Smuzhiyun #define BCM43556_CHIP_ID 0xAA24 /* 43556 chipcommon chipid */ 496*4882a593Smuzhiyun #define BCM43558_CHIP_ID 0xAA26 /* 43558 chipcommon chipid */ 497*4882a593Smuzhiyun #define BCM43562_CHIP_ID 0xAA2A /* 43562 chipcommon chipid */ 498*4882a593Smuzhiyun #define BCM43566_CHIP_ID 0xAA2E /* 43566 chipcommon chipid */ 499*4882a593Smuzhiyun #define BCM43567_CHIP_ID 0xAA2F /* 43567 chipcommon chipid */ 500*4882a593Smuzhiyun #define BCM43568_CHIP_ID 0xAA30 /* 43568 chipcommon chipid */ 501*4882a593Smuzhiyun #define BCM43569_CHIP_ID 0xAA31 /* 43569 chipcommon chipid */ 502*4882a593Smuzhiyun #define BCM43570_CHIP_ID 0xAA32 /* 43570 chipcommon chipid */ 503*4882a593Smuzhiyun #define BCM4358_CHIP_ID 0x4358 /* 4358 chipcommon chipid */ 504*4882a593Smuzhiyun #define BCM43012_CHIP_ID 0xA804 /* 43012 chipcommon chipid */ 505*4882a593Smuzhiyun #define BCM43014_CHIP_ID 0xA806 /* 43014 chipcommon chipid */ 506*4882a593Smuzhiyun #define BCM4369_CHIP_ID 0x4369 /* 4369 chipcommon chipid */ 507*4882a593Smuzhiyun 508*4882a593Smuzhiyun #define BCM4350_CHIP(chipid) ((CHIPID(chipid) == BCM4350_CHIP_ID) || \ 509*4882a593Smuzhiyun (CHIPID(chipid) == BCM4354_CHIP_ID) || \ 510*4882a593Smuzhiyun (CHIPID(chipid) == BCM43556_CHIP_ID) || \ 511*4882a593Smuzhiyun (CHIPID(chipid) == BCM43558_CHIP_ID) || \ 512*4882a593Smuzhiyun (CHIPID(chipid) == BCM43566_CHIP_ID) || \ 513*4882a593Smuzhiyun (CHIPID(chipid) == BCM43567_CHIP_ID) || \ 514*4882a593Smuzhiyun (CHIPID(chipid) == BCM43568_CHIP_ID) || \ 515*4882a593Smuzhiyun (CHIPID(chipid) == BCM43569_CHIP_ID) || \ 516*4882a593Smuzhiyun (CHIPID(chipid) == BCM43570_CHIP_ID) || \ 517*4882a593Smuzhiyun (CHIPID(chipid) == BCM4358_CHIP_ID)) /* 4350 variations */ 518*4882a593Smuzhiyun 519*4882a593Smuzhiyun #define BCM4345_CHIP_ID 0x4345 /* 4345 chipcommon chipid */ 520*4882a593Smuzhiyun #define BCM43454_CHIP_ID 43454 /* 43454 chipcommon chipid */ 521*4882a593Smuzhiyun #define BCM43455_CHIP_ID 43455 /* 43455 chipcommon chipid */ 522*4882a593Smuzhiyun #define BCM43457_CHIP_ID 43457 /* 43457 chipcommon chipid */ 523*4882a593Smuzhiyun #define BCM43458_CHIP_ID 43458 /* 43458 chipcommon chipid */ 524*4882a593Smuzhiyun 525*4882a593Smuzhiyun #define BCM4345_CHIP(chipid) (CHIPID(chipid) == BCM4345_CHIP_ID || \ 526*4882a593Smuzhiyun CHIPID(chipid) == BCM43454_CHIP_ID || \ 527*4882a593Smuzhiyun CHIPID(chipid) == BCM43455_CHIP_ID || \ 528*4882a593Smuzhiyun CHIPID(chipid) == BCM43457_CHIP_ID || \ 529*4882a593Smuzhiyun CHIPID(chipid) == BCM43458_CHIP_ID) 530*4882a593Smuzhiyun 531*4882a593Smuzhiyun #define CASE_BCM4345_CHIP case BCM4345_CHIP_ID: /* fallthrough */ \ 532*4882a593Smuzhiyun case BCM43454_CHIP_ID: /* fallthrough */ \ 533*4882a593Smuzhiyun case BCM43455_CHIP_ID: /* fallthrough */ \ 534*4882a593Smuzhiyun case BCM43457_CHIP_ID: /* fallthrough */ \ 535*4882a593Smuzhiyun case BCM43458_CHIP_ID 536*4882a593Smuzhiyun 537*4882a593Smuzhiyun #define BCM43430_CHIP_ID 43430 /* 43430 chipcommon chipid */ 538*4882a593Smuzhiyun #define BCM43018_CHIP_ID 43018 /* 43018 chipcommon chipid */ 539*4882a593Smuzhiyun #define BCM4349_CHIP_ID 0x4349 /* 4349 chipcommon chipid */ 540*4882a593Smuzhiyun #define BCM4355_CHIP_ID 0x4355 /* 4355 chipcommon chipid */ 541*4882a593Smuzhiyun #define BCM4359_CHIP_ID 0x4359 /* 4359 chipcommon chipid */ 542*4882a593Smuzhiyun #define BCM4349_CHIP(chipid) ((CHIPID(chipid) == BCM4349_CHIP_ID) || \ 543*4882a593Smuzhiyun (CHIPID(chipid) == BCM4355_CHIP_ID) || \ 544*4882a593Smuzhiyun (CHIPID(chipid) == BCM4359_CHIP_ID)) 545*4882a593Smuzhiyun 546*4882a593Smuzhiyun #define BCM4355_CHIP(chipid) (CHIPID(chipid) == BCM4355_CHIP_ID) 547*4882a593Smuzhiyun 548*4882a593Smuzhiyun #define BCM4349_CHIP_GRPID BCM4349_CHIP_ID: \ 549*4882a593Smuzhiyun case BCM4355_CHIP_ID: \ 550*4882a593Smuzhiyun case BCM4359_CHIP_ID 551*4882a593Smuzhiyun #define BCM43596_CHIP_ID 43596 /* 43596 chipcommon chipid */ 552*4882a593Smuzhiyun 553*4882a593Smuzhiyun #ifdef CHIPS_CUSTOMER_HW6 554*4882a593Smuzhiyun #define BCM4368_CHIP_ID 0x4368 /* 4368 chipcommon chipid */ 555*4882a593Smuzhiyun #define BCM4368_CHIP(chipid) (CHIPID(chipid) == BCM4368_CHIP_ID) 556*4882a593Smuzhiyun #define BCM4368_CHIP_GRPID BCM4367_CHIP_ID: \ 557*4882a593Smuzhiyun case BCM4368_CHIP_ID 558*4882a593Smuzhiyun #endif /* CHIPS_CUSTOMER_HW6 */ 559*4882a593Smuzhiyun 560*4882a593Smuzhiyun #define BCM4347_CHIP_ID 0x4347 /* 4347 chipcommon chipid */ 561*4882a593Smuzhiyun #define BCM4357_CHIP_ID 0x4357 /* 4357 chipcommon chipid */ 562*4882a593Smuzhiyun #define BCM4361_CHIP_ID 0x4361 /* 4361 chipcommon chipid */ 563*4882a593Smuzhiyun #define BCM4369_CHIP_ID 0x4369 /* 4369/ chipcommon chipid */ 564*4882a593Smuzhiyun #define BCM4373_CHIP_ID 0x4373 /* 4373/ chipcommon chipid */ 565*4882a593Smuzhiyun #define BCM4375_CHIP_ID 0x4375 /* 4375/ chipcommon chipid */ 566*4882a593Smuzhiyun #define BCM4377_CHIP_ID 0x4377 /* 4377/ chipcommon chipid */ 567*4882a593Smuzhiyun #define BCM4362_CHIP_ID 0x4362 /* 4362 chipcommon chipid */ 568*4882a593Smuzhiyun #define BCM43751_CHIP_ID 0xAAE7 /* 43751 chipcommon chipid */ 569*4882a593Smuzhiyun #ifdef CHIPS_CUSTOMER_HW6 570*4882a593Smuzhiyun #define BCM4369_CHIP_ID 0x4369 /* 4369/ chipcommon chipid */ 571*4882a593Smuzhiyun #define BCM4375_CHIP_ID 0x4375 /* 4375/ chipcommon chipid */ 572*4882a593Smuzhiyun #define BCM4376_CHIP_ID 0x4376 /* 4376 chipcommon chipid */ 573*4882a593Smuzhiyun #define BCM4377_CHIP_ID 0x4377 /* 4377/ chipcommon chipid */ 574*4882a593Smuzhiyun #define BCM4378_CHIP_ID 0x4378 /* 4378 chipcommon chipid */ 575*4882a593Smuzhiyun #define BCM4387_CHIP_ID 0x4387 /* 4387 chipcommon chipid */ 576*4882a593Smuzhiyun #endif /* CHIPS_CUSTOMER_HW6 */ 577*4882a593Smuzhiyun 578*4882a593Smuzhiyun #define CYW55500_CHIP_ID 0xD8CC /* CYW55500 chipcommon chipid */ 579*4882a593Smuzhiyun #define CYW55560_CHIP_ID 0xD908 /* CYW55560 chipcommon chipid */ 580*4882a593Smuzhiyun 581*4882a593Smuzhiyun #define BCM4347_CHIP(chipid) ((CHIPID(chipid) == BCM4347_CHIP_ID) || \ 582*4882a593Smuzhiyun (CHIPID(chipid) == BCM4357_CHIP_ID) || \ 583*4882a593Smuzhiyun (CHIPID(chipid) == BCM4361_CHIP_ID)) 584*4882a593Smuzhiyun #define BCM4347_CHIP_GRPID BCM4347_CHIP_ID: \ 585*4882a593Smuzhiyun case BCM4357_CHIP_ID: \ 586*4882a593Smuzhiyun case BCM4361_CHIP_ID 587*4882a593Smuzhiyun 588*4882a593Smuzhiyun #define BCM4369_CHIP(chipid) ((CHIPID(chipid) == BCM4369_CHIP_ID) || \ 589*4882a593Smuzhiyun (CHIPID(chipid) == BCM4377_CHIP_ID)) 590*4882a593Smuzhiyun #define BCM4369_CHIP_GRPID BCM4369_CHIP_ID: \ 591*4882a593Smuzhiyun case BCM4377_CHIP_ID 592*4882a593Smuzhiyun 593*4882a593Smuzhiyun #define BCM4362_CHIP(chipid) (CHIPID(chipid) == BCM4362_CHIP_ID) 594*4882a593Smuzhiyun #define BCM4362_CHIP_GRPID BCM4362_CHIP_ID 595*4882a593Smuzhiyun 596*4882a593Smuzhiyun #ifdef CHIPS_CUSTOMER_HW6 597*4882a593Smuzhiyun #define BCM4378_CHIP(chipid) ((CHIPID(chipid) == BCM4378_CHIP_ID) || \ 598*4882a593Smuzhiyun (CHIPID(chipid) == BCM4376_CHIP_ID)) 599*4882a593Smuzhiyun #define BCM4378_CHIP_GRPID BCM4378_CHIP_ID: \ 600*4882a593Smuzhiyun case BCM4376_CHIP_ID 601*4882a593Smuzhiyun 602*4882a593Smuzhiyun /* BCM4367 */ 603*4882a593Smuzhiyun #define BCM4367_CHIP_ID 0x4367 /* 4367 chipcommon chipid */ 604*4882a593Smuzhiyun #define CASE_BCM4367_CHIP case BCM4367_CHIP_ID 605*4882a593Smuzhiyun #define BCM4367_CHIP(chipid) (CHIPID(chipid) == BCM4367_CHIP_ID) 606*4882a593Smuzhiyun 607*4882a593Smuzhiyun #define BCM4387_CHIP(chipid) (CHIPID(chipid) == BCM4387_CHIP_ID) 608*4882a593Smuzhiyun #define BCM4387_CHIP_GRPID BCM4387_CHIP_ID 609*4882a593Smuzhiyun #endif /* CHIPS_CUSTOMER_HW6 */ 610*4882a593Smuzhiyun 611*4882a593Smuzhiyun #define BCM4365_CHIP_ID 0x4365 /* 4365 chipcommon chipid */ 612*4882a593Smuzhiyun #define BCM4366_CHIP_ID 0x4366 /* 4366 chipcommon chipid */ 613*4882a593Smuzhiyun #define BCM43664_CHIP_ID 43664 /* 4366E chipcommon chipid */ 614*4882a593Smuzhiyun #define BCM43666_CHIP_ID 43666 /* 4365E chipcommon chipid */ 615*4882a593Smuzhiyun #define BCM4365_CHIP(chipid) ((CHIPID(chipid) == BCM4365_CHIP_ID) || \ 616*4882a593Smuzhiyun (CHIPID(chipid) == BCM4366_CHIP_ID) || \ 617*4882a593Smuzhiyun (CHIPID(chipid) == BCM43664_CHIP_ID) || \ 618*4882a593Smuzhiyun (CHIPID(chipid) == BCM43666_CHIP_ID)) 619*4882a593Smuzhiyun #define CASE_BCM4365_CHIP case BCM4365_CHIP_ID: /* fallthrough */ \ 620*4882a593Smuzhiyun case BCM4366_CHIP_ID: /* fallthrough */ \ 621*4882a593Smuzhiyun case BCM43664_CHIP_ID: /* fallthrough */ \ 622*4882a593Smuzhiyun case BCM43666_CHIP_ID 623*4882a593Smuzhiyun 624*4882a593Smuzhiyun #define BCM43602_CHIP_ID 0xaa52 /* 43602 chipcommon chipid */ 625*4882a593Smuzhiyun #define BCM43462_CHIP_ID 0xa9c6 /* 43462 chipcommon chipid */ 626*4882a593Smuzhiyun #define BCM43522_CHIP_ID 0xaa02 /* 43522 chipcommon chipid */ 627*4882a593Smuzhiyun #define BCM43602_CHIP(chipid) ((CHIPID(chipid) == BCM43602_CHIP_ID) || \ 628*4882a593Smuzhiyun (CHIPID(chipid) == BCM43462_CHIP_ID) || \ 629*4882a593Smuzhiyun (CHIPID(chipid) == BCM43522_CHIP_ID)) /* 43602 variations */ 630*4882a593Smuzhiyun #define BCM43012_CHIP(chipid) (CHIPID(chipid) == BCM43012_CHIP_ID) 631*4882a593Smuzhiyun #define CASE_BCM43602_CHIP case BCM43602_CHIP_ID: /* fallthrough */ \ 632*4882a593Smuzhiyun case BCM43462_CHIP_ID: /* fallthrough */ \ 633*4882a593Smuzhiyun case BCM43522_CHIP_ID 634*4882a593Smuzhiyun 635*4882a593Smuzhiyun #define BCM4402_CHIP_ID 0x4402 /* 4402 chipid */ 636*4882a593Smuzhiyun #define BCM4704_CHIP_ID 0x4704 /* 4704 chipcommon chipid */ 637*4882a593Smuzhiyun #define BCM4707_CHIP_ID 53010 /* 4707 chipcommon chipid */ 638*4882a593Smuzhiyun #define BCM47094_CHIP_ID 53030 /* 47094 chipcommon chipid */ 639*4882a593Smuzhiyun #define BCM53018_CHIP_ID 53018 /* 53018 chipcommon chipid */ 640*4882a593Smuzhiyun #define BCM4707_CHIP(chipid) (((chipid) == BCM4707_CHIP_ID) || \ 641*4882a593Smuzhiyun ((chipid) == BCM53018_CHIP_ID) || \ 642*4882a593Smuzhiyun ((chipid) == BCM47094_CHIP_ID)) 643*4882a593Smuzhiyun #define BCM4710_CHIP_ID 0x4710 /* 4710 chipid */ 644*4882a593Smuzhiyun #define BCM4785_CHIP_ID 0x4785 /* 4785 chipcommon chipid */ 645*4882a593Smuzhiyun #define BCM5350_CHIP_ID 0x5350 /* 5350 chipcommon chipid */ 646*4882a593Smuzhiyun #define BCM5352_CHIP_ID 0x5352 /* 5352 chipcommon chipid */ 647*4882a593Smuzhiyun #define BCM5365_CHIP_ID 0x5365 /* 5365 chipcommon chipid */ 648*4882a593Smuzhiyun #define BCM53573_CHIP_ID 53573 /* 53573 chipcommon chipid */ 649*4882a593Smuzhiyun #define BCM53574_CHIP_ID 53574 /* 53574 chipcommon chipid */ 650*4882a593Smuzhiyun #define BCM53573_CHIP(chipid) ((CHIPID(chipid) == BCM53573_CHIP_ID) || \ 651*4882a593Smuzhiyun (CHIPID(chipid) == BCM53574_CHIP_ID) || \ 652*4882a593Smuzhiyun (CHIPID(chipid) == BCM47452_CHIP_ID)) 653*4882a593Smuzhiyun #define BCM53573_CHIP_GRPID BCM53573_CHIP_ID : \ 654*4882a593Smuzhiyun case BCM53574_CHIP_ID : \ 655*4882a593Smuzhiyun case BCM47452_CHIP_ID 656*4882a593Smuzhiyun #define BCM53573_DEVICE(devid) (((devid) == BCM53573_D11AC_ID) || \ 657*4882a593Smuzhiyun ((devid) == BCM53573_D11AC2G_ID) || \ 658*4882a593Smuzhiyun ((devid) == BCM53573_D11AC5G_ID) || \ 659*4882a593Smuzhiyun ((devid) == BCM47189_D11AC_ID) || \ 660*4882a593Smuzhiyun ((devid) == BCM47189_D11AC2G_ID) || \ 661*4882a593Smuzhiyun ((devid) == BCM47189_D11AC5G_ID)) 662*4882a593Smuzhiyun 663*4882a593Smuzhiyun #define BCM7271_CHIP_ID 0x05c9 /* 7271 chipcommon chipid */ 664*4882a593Smuzhiyun #define BCM7271_CHIP(chipid) ((CHIPID(chipid) == BCM7271_CHIP_ID)) 665*4882a593Smuzhiyun 666*4882a593Smuzhiyun #define BCM4373_CHIP_ID 0x4373 /* 4373 chipcommon chipid */ 667*4882a593Smuzhiyun 668*4882a593Smuzhiyun /* Package IDs */ 669*4882a593Smuzhiyun #ifdef DEPRECATED /* These products have been deprecated */ 670*4882a593Smuzhiyun #define BCM4303_PKG_ID 2 /* 4303 package id */ 671*4882a593Smuzhiyun #define BCM4309_PKG_ID 1 /* 4309 package id */ 672*4882a593Smuzhiyun #define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */ 673*4882a593Smuzhiyun #define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */ 674*4882a593Smuzhiyun #define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */ 675*4882a593Smuzhiyun #define BCM4328USBD11G_PKG_ID 2 /* 4328 802.11g USB package id */ 676*4882a593Smuzhiyun #define BCM4328USBDUAL_PKG_ID 3 /* 4328 802.11a/g USB package id */ 677*4882a593Smuzhiyun #define BCM4328SDIOD11G_PKG_ID 4 /* 4328 802.11g SDIO package id */ 678*4882a593Smuzhiyun #define BCM4328SDIODUAL_PKG_ID 5 /* 4328 802.11a/g SDIO package id */ 679*4882a593Smuzhiyun #define BCM4329_289PIN_PKG_ID 0 /* 4329 289-pin package id */ 680*4882a593Smuzhiyun #define BCM4329_182PIN_PKG_ID 1 /* 4329N 182-pin package id */ 681*4882a593Smuzhiyun #define BCM5354E_PKG_ID 1 /* 5354E package id */ 682*4882a593Smuzhiyun #define BCM4716_PKG_ID 8 /* 4716 package id */ 683*4882a593Smuzhiyun #define BCM4717_PKG_ID 9 /* 4717 package id */ 684*4882a593Smuzhiyun #define BCM4718_PKG_ID 10 /* 4718 package id */ 685*4882a593Smuzhiyun #define BCM4331TT_PKG_ID 8 /* 4331 12x12 package id */ 686*4882a593Smuzhiyun #define BCM4331TN_PKG_ID 9 /* 4331 12x9 package id */ 687*4882a593Smuzhiyun #define BCM4331TNA0_PKG_ID 0xb /* 4331 12x9 package id */ 688*4882a593Smuzhiyun #endif /* DEPRECATED */ 689*4882a593Smuzhiyun #define BCM47189_PKG_ID 1 /* 47189 package id */ 690*4882a593Smuzhiyun #define BCM53573_PKG_ID 0 /* 53573 package id */ 691*4882a593Smuzhiyun 692*4882a593Smuzhiyun #define HDLSIM5350_PKG_ID 1 /* HDL simulator package id for a 5350 */ 693*4882a593Smuzhiyun #define HDLSIM_PKG_ID 14 /* HDL simulator package id */ 694*4882a593Smuzhiyun #define HWSIM_PKG_ID 15 /* Hardware simulator package id */ 695*4882a593Smuzhiyun 696*4882a593Smuzhiyun #define BCM4707_PKG_ID 1 /* 4707 package id */ 697*4882a593Smuzhiyun #define BCM4708_PKG_ID 2 /* 4708 package id */ 698*4882a593Smuzhiyun #define BCM4709_PKG_ID 0 /* 4709 package id */ 699*4882a593Smuzhiyun 700*4882a593Smuzhiyun #define PCIXX21_FLASHMEDIA0_ID 0x8033 /* TI PCI xx21 Standard Host Controller */ 701*4882a593Smuzhiyun #define PCIXX21_SDIOH0_ID 0x8034 /* TI PCI xx21 Standard Host Controller */ 702*4882a593Smuzhiyun 703*4882a593Smuzhiyun #define BCM4335_WLCSP_PKG_ID (0x0) /* WLCSP Module/Mobile SDIO/HSIC. */ 704*4882a593Smuzhiyun #define BCM4335_FCBGA_PKG_ID (0x1) /* FCBGA PC/Embeded/Media PCIE/SDIO */ 705*4882a593Smuzhiyun #define BCM4335_WLBGA_PKG_ID (0x2) /* WLBGA COB/Mobile SDIO/HSIC. */ 706*4882a593Smuzhiyun #define BCM4335_FCBGAD_PKG_ID (0x3) /* FCBGA Debug Debug/Dev All if's. */ 707*4882a593Smuzhiyun #define BCM4335_PKG_MASK (0x3) 708*4882a593Smuzhiyun #define BCM43602_12x12_PKG_ID (0x1) /* 12x12 pins package, used for e.g. router designs */ 709*4882a593Smuzhiyun 710*4882a593Smuzhiyun /* boardflags */ 711*4882a593Smuzhiyun #define BFL_BTC2WIRE 0x00000001 /* old 2wire Bluetooth coexistence, OBSOLETE */ 712*4882a593Smuzhiyun #define BFL_BTCOEX 0x00000001 /* Board supports BTCOEX */ 713*4882a593Smuzhiyun #define BFL_PACTRL 0x00000002 /* Board has gpio 9 controlling the PA */ 714*4882a593Smuzhiyun #define BFL_AIRLINEMODE 0x00000004 /* Board implements gpio radio disable indication */ 715*4882a593Smuzhiyun #define BFL_ADCDIV 0x00000008 /* Board has the rssi ADC divider */ 716*4882a593Smuzhiyun #define BFL_DIS_256QAM 0x00000008 717*4882a593Smuzhiyun #define BFL_ENETROBO 0x00000010 /* Board has robo switch or core */ 718*4882a593Smuzhiyun #define BFL_TSSIAVG 0x00000010 /* TSSI averaging for ACPHY chips */ 719*4882a593Smuzhiyun #define BFL_NOPLLDOWN 0x00000020 /* Not ok to power down the chip pll and oscillator */ 720*4882a593Smuzhiyun #define BFL_CCKHIPWR 0x00000040 /* Can do high-power CCK transmission */ 721*4882a593Smuzhiyun #define BFL_ENETADM 0x00000080 /* Board has ADMtek switch */ 722*4882a593Smuzhiyun #define BFL_ENETVLAN 0x00000100 /* Board has VLAN capability */ 723*4882a593Smuzhiyun #define BFL_LTECOEX 0x00000200 /* LTE Coex enabled */ 724*4882a593Smuzhiyun #define BFL_NOPCI 0x00000400 /* Board leaves PCI floating */ 725*4882a593Smuzhiyun #define BFL_FEM 0x00000800 /* Board supports the Front End Module */ 726*4882a593Smuzhiyun #define BFL_EXTLNA 0x00001000 /* Board has an external LNA in 2.4GHz band */ 727*4882a593Smuzhiyun #define BFL_HGPA 0x00002000 /* Board has a high gain PA */ 728*4882a593Smuzhiyun #define BFL_BTC2WIRE_ALTGPIO 0x00004000 /* Board's BTC 2wire is in the alternate gpios */ 729*4882a593Smuzhiyun #define BFL_ALTIQ 0x00008000 /* Alternate I/Q settings */ 730*4882a593Smuzhiyun #define BFL_NOPA 0x00010000 /* Board has no PA */ 731*4882a593Smuzhiyun #define BFL_RSSIINV 0x00020000 /* Board's RSSI uses positive slope(not TSSI) */ 732*4882a593Smuzhiyun #define BFL_PAREF 0x00040000 /* Board uses the PARef LDO */ 733*4882a593Smuzhiyun #define BFL_3TSWITCH 0x00080000 /* Board uses a triple throw switch shared with BT */ 734*4882a593Smuzhiyun #define BFL_PHASESHIFT 0x00100000 /* Board can support phase shifter */ 735*4882a593Smuzhiyun #define BFL_BUCKBOOST 0x00200000 /* Power topology uses BUCKBOOST */ 736*4882a593Smuzhiyun #define BFL_FEM_BT 0x00400000 /* Board has FEM and switch to share antenna w/ BT */ 737*4882a593Smuzhiyun #define BFL_NOCBUCK 0x00800000 /* Power topology doesn't use CBUCK */ 738*4882a593Smuzhiyun #define BFL_CCKFAVOREVM 0x01000000 /* Favor CCK EVM over spectral mask */ 739*4882a593Smuzhiyun #define BFL_PALDO 0x02000000 /* Power topology uses PALDO */ 740*4882a593Smuzhiyun #define BFL_LNLDO2_2P5 0x04000000 /* Select 2.5V as LNLDO2 output voltage */ 741*4882a593Smuzhiyun #define BFL_FASTPWR 0x08000000 742*4882a593Smuzhiyun #define BFL_UCPWRCTL_MININDX 0x08000000 /* Enforce min power index to avoid FEM damage */ 743*4882a593Smuzhiyun #define BFL_EXTLNA_5GHz 0x10000000 /* Board has an external LNA in 5GHz band */ 744*4882a593Smuzhiyun #define BFL_TRSW_1by2 0x20000000 /* Board has 2 TRSW's in 1by2 designs */ 745*4882a593Smuzhiyun #define BFL_GAINBOOSTA01 0x20000000 /* 5g Gainboost for core0 and core1 */ 746*4882a593Smuzhiyun #define BFL_LO_TRSW_R_5GHz 0x40000000 /* In 5G do not throw TRSW to T for clipLO gain */ 747*4882a593Smuzhiyun #define BFL_ELNA_GAINDEF 0x80000000 /* Backoff InitGain based on elna_2g/5g field 748*4882a593Smuzhiyun * when this flag is set 749*4882a593Smuzhiyun */ 750*4882a593Smuzhiyun #define BFL_EXTLNA_TX 0x20000000 /* Temp boardflag to indicate to */ 751*4882a593Smuzhiyun 752*4882a593Smuzhiyun /* boardflags2 */ 753*4882a593Smuzhiyun #define BFL2_RXBB_INT_REG_DIS 0x00000001 /* Board has an external rxbb regulator */ 754*4882a593Smuzhiyun #define BFL2_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */ 755*4882a593Smuzhiyun #define BFL2_TXPWRCTRL_EN 0x00000004 /* Board permits enabling TX Power Control */ 756*4882a593Smuzhiyun #define BFL2_2X4_DIV 0x00000008 /* Board supports the 2X4 diversity switch */ 757*4882a593Smuzhiyun #define BFL2_5G_PWRGAIN 0x00000010 /* Board supports 5G band power gain */ 758*4882a593Smuzhiyun #define BFL2_PCIEWAR_OVR 0x00000020 /* Board overrides ASPM and Clkreq settings */ 759*4882a593Smuzhiyun #define BFL2_CAESERS_BRD 0x00000040 /* Board is Caesers brd (unused by sw) */ 760*4882a593Smuzhiyun #define BFL2_WLCX_ATLAS 0x00000040 /* Board flag to initialize ECI for WLCX on FL-ATLAS */ 761*4882a593Smuzhiyun #define BFL2_BTC3WIRE 0x00000080 /* Board support legacy 3 wire or 4 wire */ 762*4882a593Smuzhiyun #define BFL2_BTCLEGACY 0x00000080 /* Board support legacy 3/4 wire, to replace 763*4882a593Smuzhiyun * BFL2_BTC3WIRE 764*4882a593Smuzhiyun */ 765*4882a593Smuzhiyun #define BFL2_SKWRKFEM_BRD 0x00000100 /* 4321mcm93 board uses Skyworks FEM */ 766*4882a593Smuzhiyun #define BFL2_SPUR_WAR 0x00000200 /* Board has a WAR for clock-harmonic spurs */ 767*4882a593Smuzhiyun #define BFL2_GPLL_WAR 0x00000400 /* Flag to narrow G-band PLL loop b/w */ 768*4882a593Smuzhiyun #define BFL2_TRISTATE_LED 0x00000800 /* Tri-state the LED */ 769*4882a593Smuzhiyun #define BFL2_SINGLEANT_CCK 0x00001000 /* Tx CCK pkts on Ant 0 only */ 770*4882a593Smuzhiyun #define BFL2_2G_SPUR_WAR 0x00002000 /* WAR to reduce and avoid clock-harmonic spurs in 2G */ 771*4882a593Smuzhiyun #define BFL2_BPHY_ALL_TXCORES 0x00004000 /* Transmit bphy frames using all tx cores */ 772*4882a593Smuzhiyun #define BFL2_FCC_BANDEDGE_WAR 0x00008000 /* Activates WAR to improve FCC bandedge performance */ 773*4882a593Smuzhiyun #define BFL2_DAC_SPUR_IMPROVEMENT 0x00008000 /* Reducing DAC Spurs */ 774*4882a593Smuzhiyun #define BFL2_GPLL_WAR2 0x00010000 /* Flag to widen G-band PLL loop b/w */ 775*4882a593Smuzhiyun #define BFL2_REDUCED_PA_TURNONTIME 0x00010000 /* Flag to reduce PA turn on Time */ 776*4882a593Smuzhiyun #define BFL2_IPALVLSHIFT_3P3 0x00020000 777*4882a593Smuzhiyun #define BFL2_INTERNDET_TXIQCAL 0x00040000 /* Use internal envelope detector for TX IQCAL */ 778*4882a593Smuzhiyun #define BFL2_XTALBUFOUTEN 0x00080000 /* Keep the buffered Xtal output from radio on */ 779*4882a593Smuzhiyun /* Most drivers will turn it off without this flag */ 780*4882a593Smuzhiyun /* to save power. */ 781*4882a593Smuzhiyun 782*4882a593Smuzhiyun #define BFL2_ANAPACTRL_2G 0x00100000 /* 2G ext PAs are controlled by analog PA ctrl lines */ 783*4882a593Smuzhiyun #define BFL2_ANAPACTRL_5G 0x00200000 /* 5G ext PAs are controlled by analog PA ctrl lines */ 784*4882a593Smuzhiyun #define BFL2_ELNACTRL_TRSW_2G 0x00400000 /* AZW4329: 2G gmode_elna_gain controls TR Switch */ 785*4882a593Smuzhiyun #define BFL2_BT_SHARE_ANT0 0x00800000 /* share core0 antenna with BT */ 786*4882a593Smuzhiyun #define BFL2_TEMPSENSE_HIGHER 0x01000000 /* The tempsense threshold can sustain higher value 787*4882a593Smuzhiyun * than programmed. The exact delta is decided by 788*4882a593Smuzhiyun * driver per chip/boardtype. This can be used 789*4882a593Smuzhiyun * when tempsense qualification happens after shipment 790*4882a593Smuzhiyun */ 791*4882a593Smuzhiyun #define BFL2_BTC3WIREONLY 0x02000000 /* standard 3 wire btc only. 4 wire not supported */ 792*4882a593Smuzhiyun #define BFL2_PWR_NOMINAL 0x04000000 /* 0: power reduction on, 1: no power reduction */ 793*4882a593Smuzhiyun #define BFL2_EXTLNA_PWRSAVE 0x08000000 /* boardflag to enable ucode to apply power save */ 794*4882a593Smuzhiyun /* ucode control of eLNA during Tx */ 795*4882a593Smuzhiyun #define BFL2_SDR_EN 0x20000000 /* SDR enabled or disabled */ 796*4882a593Smuzhiyun #define BFL2_DYNAMIC_VMID 0x10000000 /* boardflag to enable dynamic Vmid idle TSSI CAL */ 797*4882a593Smuzhiyun #define BFL2_LNA1BYPFORTR2G 0x40000000 /* acphy, enable lna1 bypass for clip gain, 2g */ 798*4882a593Smuzhiyun #define BFL2_LNA1BYPFORTR5G 0x80000000 /* acphy, enable lna1 bypass for clip gain, 5g */ 799*4882a593Smuzhiyun 800*4882a593Smuzhiyun /* SROM 11 - 11ac boardflag definitions */ 801*4882a593Smuzhiyun #define BFL_SROM11_BTCOEX 0x00000001 /* Board supports BTCOEX */ 802*4882a593Smuzhiyun #define BFL_SROM11_WLAN_BT_SH_XTL 0x00000002 /* bluetooth and wlan share same crystal */ 803*4882a593Smuzhiyun #define BFL_SROM11_EXTLNA 0x00001000 /* Board has an external LNA in 2.4GHz band */ 804*4882a593Smuzhiyun #define BFL_SROM11_EPA_TURNON_TIME 0x00018000 /* 2 bits for different PA turn on times */ 805*4882a593Smuzhiyun #define BFL_SROM11_EPA_TURNON_TIME_SHIFT 15 806*4882a593Smuzhiyun #define BFL_SROM11_PRECAL_TX_IDX 0x00040000 /* Dedicated TX IQLOCAL IDX values */ 807*4882a593Smuzhiyun /* per subband, as derived from 43602A1 MCH5 */ 808*4882a593Smuzhiyun #define BFL_SROM11_EXTLNA_5GHz 0x10000000 /* Board has an external LNA in 5GHz band */ 809*4882a593Smuzhiyun #define BFL_SROM11_GAINBOOSTA01 0x20000000 /* 5g Gainboost for core0 and core1 */ 810*4882a593Smuzhiyun #define BFL2_SROM11_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */ 811*4882a593Smuzhiyun #define BFL2_SROM11_ANAPACTRL_2G 0x00100000 /* 2G ext PAs are ctrl-ed by analog PA ctrl lines */ 812*4882a593Smuzhiyun #define BFL2_SROM11_ANAPACTRL_5G 0x00200000 /* 5G ext PAs are ctrl-ed by analog PA ctrl lines */ 813*4882a593Smuzhiyun #define BFL2_SROM11_SINGLEANT_CCK 0x00001000 /* Tx CCK pkts on Ant 0 only */ 814*4882a593Smuzhiyun #define BFL2_SROM11_EPA_ON_DURING_TXIQLOCAL 0x00020000 /* Keep ext. PA's on in TX IQLO CAL */ 815*4882a593Smuzhiyun 816*4882a593Smuzhiyun /* boardflags3 */ 817*4882a593Smuzhiyun #define BFL3_FEMCTRL_SUB 0x00000007 /* acphy, subrevs of femctrl on top of srom_femctrl */ 818*4882a593Smuzhiyun #define BFL3_RCAL_WAR 0x00000008 /* acphy, rcal war active on this board (4335a0) */ 819*4882a593Smuzhiyun #define BFL3_TXGAINTBLID 0x00000070 /* acphy, txgain table id */ 820*4882a593Smuzhiyun #define BFL3_TXGAINTBLID_SHIFT 0x4 /* acphy, txgain table id shift bit */ 821*4882a593Smuzhiyun #define BFL3_TSSI_DIV_WAR 0x00000080 /* acphy, Seperate paparam for 20/40/80 */ 822*4882a593Smuzhiyun #define BFL3_TSSI_DIV_WAR_SHIFT 0x7 /* acphy, Seperate paparam for 20/40/80 shift bit */ 823*4882a593Smuzhiyun #define BFL3_FEMTBL_FROM_NVRAM 0x00000100 /* acphy, femctrl table is read from nvram */ 824*4882a593Smuzhiyun #define BFL3_FEMTBL_FROM_NVRAM_SHIFT 0x8 /* acphy, femctrl table is read from nvram */ 825*4882a593Smuzhiyun #define BFL3_AGC_CFG_2G 0x00000200 /* acphy, gain control configuration for 2G */ 826*4882a593Smuzhiyun #define BFL3_AGC_CFG_5G 0x00000400 /* acphy, gain control configuration for 5G */ 827*4882a593Smuzhiyun #define BFL3_PPR_BIT_EXT 0x00000800 /* acphy, bit position for 1bit extension for ppr */ 828*4882a593Smuzhiyun #define BFL3_PPR_BIT_EXT_SHIFT 11 /* acphy, bit shift for 1bit extension for ppr */ 829*4882a593Smuzhiyun #define BFL3_BBPLL_SPR_MODE_DIS 0x00001000 /* acphy, disables bbpll spur modes */ 830*4882a593Smuzhiyun #define BFL3_RCAL_OTP_VAL_EN 0x00002000 /* acphy, to read rcal_trim value from otp */ 831*4882a593Smuzhiyun #define BFL3_2GTXGAINTBL_BLANK 0x00004000 /* acphy, blank the first X ticks of 2g gaintbl */ 832*4882a593Smuzhiyun #define BFL3_2GTXGAINTBL_BLANK_SHIFT 14 /* acphy, blank the first X ticks of 2g gaintbl */ 833*4882a593Smuzhiyun #define BFL3_5GTXGAINTBL_BLANK 0x00008000 /* acphy, blank the first X ticks of 5g gaintbl */ 834*4882a593Smuzhiyun #define BFL3_5GTXGAINTBL_BLANK_SHIFT 15 /* acphy, blank the first X ticks of 5g gaintbl */ 835*4882a593Smuzhiyun #define BFL3_PHASETRACK_MAX_ALPHABETA 0x00010000 /* acphy, to max out alpha,beta to 511 */ 836*4882a593Smuzhiyun #define BFL3_PHASETRACK_MAX_ALPHABETA_SHIFT 16 /* acphy, to max out alpha,beta to 511 */ 837*4882a593Smuzhiyun /* acphy, to use backed off gaintbl for lte-coex */ 838*4882a593Smuzhiyun #define BFL3_LTECOEX_GAINTBL_EN 0x00060000 839*4882a593Smuzhiyun /* acphy, to use backed off gaintbl for lte-coex */ 840*4882a593Smuzhiyun #define BFL3_LTECOEX_GAINTBL_EN_SHIFT 17 841*4882a593Smuzhiyun #define BFL3_5G_SPUR_WAR 0x00080000 /* acphy, enable spur WAR in 5G band */ 842*4882a593Smuzhiyun #define BFL3_1X1_RSDB_ANT 0x01000000 /* to find if 2-ant RSDB board or 1-ant RSDB board */ 843*4882a593Smuzhiyun #define BFL3_1X1_RSDB_ANT_SHIFT 24 844*4882a593Smuzhiyun 845*4882a593Smuzhiyun /* acphy: lpmode2g and lpmode_5g related boardflags */ 846*4882a593Smuzhiyun #define BFL3_ACPHY_LPMODE_2G 0x00300000 /* bits 20:21 for lpmode_2g choice */ 847*4882a593Smuzhiyun #define BFL3_ACPHY_LPMODE_2G_SHIFT 20 848*4882a593Smuzhiyun 849*4882a593Smuzhiyun #define BFL3_ACPHY_LPMODE_5G 0x00C00000 /* bits 22:23 for lpmode_5g choice */ 850*4882a593Smuzhiyun #define BFL3_ACPHY_LPMODE_5G_SHIFT 22 851*4882a593Smuzhiyun 852*4882a593Smuzhiyun #define BFL3_EXT_LPO_ISCLOCK 0x02000000 /* External LPO is clock, not x-tal */ 853*4882a593Smuzhiyun #define BFL3_FORCE_INT_LPO_SEL 0x04000000 /* Force internal lpo */ 854*4882a593Smuzhiyun #define BFL3_FORCE_EXT_LPO_SEL 0x08000000 /* Force external lpo */ 855*4882a593Smuzhiyun 856*4882a593Smuzhiyun #define BFL3_EN_BRCM_IMPBF 0x10000000 /* acphy, Allow BRCM Implicit TxBF */ 857*4882a593Smuzhiyun #define BFL3_AVVMID_FROM_NVRAM 0x40000000 /* Read Av Vmid from NVRAM */ 858*4882a593Smuzhiyun #define BFL3_VLIN_EN_FROM_NVRAM 0x80000000 /* Read Vlin En from NVRAM */ 859*4882a593Smuzhiyun 860*4882a593Smuzhiyun #define BFL3_AVVMID_FROM_NVRAM_SHIFT 30 /* Read Av Vmid from NVRAM */ 861*4882a593Smuzhiyun #define BFL3_VLIN_EN_FROM_NVRAM_SHIFT 31 /* Enable Vlin from NVRAM */ 862*4882a593Smuzhiyun 863*4882a593Smuzhiyun /* boardflags4 for SROM12/SROM13 */ 864*4882a593Smuzhiyun #define BFL4_SROM12_4dBPAD (1 << 0) /* To distinguigh between normal and 4dB pad board */ 865*4882a593Smuzhiyun #define BFL4_SROM12_2G_DETTYPE (1 << 1) /* Determine power detector type for 2G */ 866*4882a593Smuzhiyun #define BFL4_SROM12_5G_DETTYPE (1 << 2) /* Determine power detector type for 5G */ 867*4882a593Smuzhiyun #define BFL4_SROM13_DETTYPE_EN (1 << 3) /* using pa_dettype from SROM13 flags */ 868*4882a593Smuzhiyun #define BFL4_SROM13_CCK_SPUR_EN (1 << 4) /* using cck spur reduction setting in 4366 */ 869*4882a593Smuzhiyun #define BFL4_SROM13_1P5V_CBUCK (1 << 7) /* using 1.5V cbuck board in 4366 */ 870*4882a593Smuzhiyun #define BFL4_SROM13_EN_SW_TXRXCHAIN_MASK (1 << 8) /* Enable/disable bit for sw chain mask */ 871*4882a593Smuzhiyun 872*4882a593Smuzhiyun #define BFL4_4364_HARPOON 0x0100 /* Harpoon module 4364 */ 873*4882a593Smuzhiyun #define BFL4_4364_GODZILLA 0x0200 /* Godzilla module 4364 */ 874*4882a593Smuzhiyun #define BFL4_BTCOEX_OVER_SECI 0x00000400 /* Enable btcoex over gci seci */ 875*4882a593Smuzhiyun 876*4882a593Smuzhiyun /* papd params */ 877*4882a593Smuzhiyun #define PAPD_TX_ATTN_2G 0xFF 878*4882a593Smuzhiyun #define PAPD_TX_ATTN_5G 0xFF00 879*4882a593Smuzhiyun #define PAPD_TX_ATTN_5G_SHIFT 8 880*4882a593Smuzhiyun #define PAPD_RX_ATTN_2G 0xFF 881*4882a593Smuzhiyun #define PAPD_RX_ATTN_5G 0xFF00 882*4882a593Smuzhiyun #define PAPD_RX_ATTN_5G_SHIFT 8 883*4882a593Smuzhiyun #define PAPD_CAL_IDX_2G 0xFF 884*4882a593Smuzhiyun #define PAPD_CAL_IDX_5G 0xFF00 885*4882a593Smuzhiyun #define PAPD_CAL_IDX_5G_SHIFT 8 886*4882a593Smuzhiyun #define PAPD_BBMULT_2G 0xFF 887*4882a593Smuzhiyun #define PAPD_BBMULT_5G 0xFF00 888*4882a593Smuzhiyun #define PAPD_BBMULT_5G_SHIFT 8 889*4882a593Smuzhiyun #define TIA_GAIN_MODE_2G 0xFF 890*4882a593Smuzhiyun #define TIA_GAIN_MODE_5G 0xFF00 891*4882a593Smuzhiyun #define TIA_GAIN_MODE_5G_SHIFT 8 892*4882a593Smuzhiyun #define PAPD_EPS_OFFSET_2G 0xFFFF 893*4882a593Smuzhiyun #define PAPD_EPS_OFFSET_5G 0xFFFF0000 894*4882a593Smuzhiyun #define PAPD_EPS_OFFSET_5G_SHIFT 16 895*4882a593Smuzhiyun #define PAPD_CALREF_DB_2G 0xFF 896*4882a593Smuzhiyun #define PAPD_CALREF_DB_5G 0xFF00 897*4882a593Smuzhiyun #define PAPD_CALREF_DB_5G_SHIFT 8 898*4882a593Smuzhiyun 899*4882a593Smuzhiyun /* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */ 900*4882a593Smuzhiyun #define BOARD_GPIO_BTC3W_IN 0x850 /* bit 4 is RF_ACTIVE, bit 6 is STATUS, bit 11 is PRI */ 901*4882a593Smuzhiyun #define BOARD_GPIO_BTC3W_OUT 0x020 /* bit 5 is TX_CONF */ 902*4882a593Smuzhiyun #define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistence Input */ 903*4882a593Smuzhiyun #define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistence Out */ 904*4882a593Smuzhiyun #define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistence Input */ 905*4882a593Smuzhiyun #define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistence Out */ 906*4882a593Smuzhiyun #define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */ 907*4882a593Smuzhiyun #define BOARD_GPIO_12 0x1000 /* gpio 12 */ 908*4882a593Smuzhiyun #define BOARD_GPIO_13 0x2000 /* gpio 13 */ 909*4882a593Smuzhiyun #define BOARD_GPIO_BTC4_IN 0x0800 /* gpio 11, coex4, in */ 910*4882a593Smuzhiyun #define BOARD_GPIO_BTC4_BT 0x2000 /* gpio 12, coex4, bt active */ 911*4882a593Smuzhiyun #define BOARD_GPIO_BTC4_STAT 0x4000 /* gpio 14, coex4, status */ 912*4882a593Smuzhiyun #define BOARD_GPIO_BTC4_WLAN 0x8000 /* gpio 15, coex4, wlan active */ 913*4882a593Smuzhiyun #define BOARD_GPIO_1_WLAN_PWR 0x02 /* throttle WLAN power on X21 board */ 914*4882a593Smuzhiyun #define BOARD_GPIO_2_WLAN_PWR 0x04 /* throttle WLAN power on X29C board */ 915*4882a593Smuzhiyun #define BOARD_GPIO_3_WLAN_PWR 0x08 /* throttle WLAN power on X28 board */ 916*4882a593Smuzhiyun #define BOARD_GPIO_4_WLAN_PWR 0x10 /* throttle WLAN power on X19 board */ 917*4882a593Smuzhiyun #define BOARD_GPIO_13_WLAN_PWR 0x2000 /* throttle WLAN power on X14 board */ 918*4882a593Smuzhiyun 919*4882a593Smuzhiyun #define GPIO_BTC4W_OUT_4312 0x010 /* bit 4 is BT_IODISABLE */ 920*4882a593Smuzhiyun 921*4882a593Smuzhiyun #define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */ 922*4882a593Smuzhiyun #define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */ 923*4882a593Smuzhiyun #define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal power-up */ 924*4882a593Smuzhiyun #define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL power-down */ 925*4882a593Smuzhiyun 926*4882a593Smuzhiyun /* power control defines */ 927*4882a593Smuzhiyun #define PLL_DELAY 150 /* us pll on delay */ 928*4882a593Smuzhiyun #define FREF_DELAY 200 /* us fref change delay */ 929*4882a593Smuzhiyun #define MIN_SLOW_CLK 32 /* us Slow clock period */ 930*4882a593Smuzhiyun #define XTAL_ON_DELAY 1000 /* us crystal power-on delay */ 931*4882a593Smuzhiyun 932*4882a593Smuzhiyun /* 43012 wlbga Board */ 933*4882a593Smuzhiyun #define BCM943012WLREF_SSID 0x07d7 934*4882a593Smuzhiyun 935*4882a593Smuzhiyun /* 43012 fcbga Board */ 936*4882a593Smuzhiyun #define BCM943012FCREF_SSID 0x07d4 937*4882a593Smuzhiyun 938*4882a593Smuzhiyun /* 43602 Boards, unclear yet what boards will be created. */ 939*4882a593Smuzhiyun #define BCM943602RSVD1_SSID 0x06a5 940*4882a593Smuzhiyun #define BCM943602RSVD2_SSID 0x06a6 941*4882a593Smuzhiyun #define BCM943602X87 0X0133 942*4882a593Smuzhiyun #define BCM943602X87P2 0X0152 943*4882a593Smuzhiyun #define BCM943602X87P3 0X0153 944*4882a593Smuzhiyun #define BCM943602X238 0X0132 945*4882a593Smuzhiyun #define BCM943602X238D 0X014A 946*4882a593Smuzhiyun #define BCM943602X238DP2 0X0155 947*4882a593Smuzhiyun #define BCM943602X238DP3 0X0156 948*4882a593Smuzhiyun #define BCM943602X100 0x0761 949*4882a593Smuzhiyun #define BCM943602X100GS 0x0157 950*4882a593Smuzhiyun #define BCM943602X100P2 0x015A 951*4882a593Smuzhiyun 952*4882a593Smuzhiyun /* # of GPIO pins */ 953*4882a593Smuzhiyun #define GPIO_NUMPINS 32 954*4882a593Smuzhiyun 955*4882a593Smuzhiyun /* These values are used by dhd host driver. */ 956*4882a593Smuzhiyun #define RDL_RAM_BASE_4319 0x60000000 957*4882a593Smuzhiyun #define RDL_RAM_BASE_4329 0x60000000 958*4882a593Smuzhiyun #define RDL_RAM_SIZE_4319 0x48000 959*4882a593Smuzhiyun #define RDL_RAM_SIZE_4329 0x48000 960*4882a593Smuzhiyun #define RDL_RAM_SIZE_43236 0x70000 961*4882a593Smuzhiyun #define RDL_RAM_BASE_43236 0x60000000 962*4882a593Smuzhiyun #define RDL_RAM_SIZE_4328 0x60000 963*4882a593Smuzhiyun #define RDL_RAM_BASE_4328 0x80000000 964*4882a593Smuzhiyun #define RDL_RAM_SIZE_4322 0x60000 965*4882a593Smuzhiyun #define RDL_RAM_BASE_4322 0x60000000 966*4882a593Smuzhiyun #define RDL_RAM_SIZE_4360 0xA0000 967*4882a593Smuzhiyun #define RDL_RAM_BASE_4360 0x60000000 968*4882a593Smuzhiyun #define RDL_RAM_SIZE_43143 0x70000 969*4882a593Smuzhiyun #define RDL_RAM_BASE_43143 0x60000000 970*4882a593Smuzhiyun #define RDL_RAM_SIZE_4350 0xC0000 971*4882a593Smuzhiyun #define RDL_RAM_BASE_4350 0x180800 972*4882a593Smuzhiyun 973*4882a593Smuzhiyun /* generic defs for nvram "muxenab" bits 974*4882a593Smuzhiyun * Note: these differ for 4335a0. refer bcmchipc.h for specific mux options. 975*4882a593Smuzhiyun */ 976*4882a593Smuzhiyun #define MUXENAB_UART 0x00000001 977*4882a593Smuzhiyun #define MUXENAB_GPIO 0x00000002 978*4882a593Smuzhiyun #define MUXENAB_ERCX 0x00000004 /* External Radio BT coex */ 979*4882a593Smuzhiyun #define MUXENAB_JTAG 0x00000008 980*4882a593Smuzhiyun #define MUXENAB_HOST_WAKE 0x00000010 /* configure GPIO for SDIO host_wake */ 981*4882a593Smuzhiyun #define MUXENAB_I2S_EN 0x00000020 982*4882a593Smuzhiyun #define MUXENAB_I2S_MASTER 0x00000040 983*4882a593Smuzhiyun #define MUXENAB_I2S_FULL 0x00000080 984*4882a593Smuzhiyun #define MUXENAB_SFLASH 0x00000100 985*4882a593Smuzhiyun #define MUXENAB_RFSWCTRL0 0x00000200 986*4882a593Smuzhiyun #define MUXENAB_RFSWCTRL1 0x00000400 987*4882a593Smuzhiyun #define MUXENAB_RFSWCTRL2 0x00000800 988*4882a593Smuzhiyun #define MUXENAB_SECI 0x00001000 989*4882a593Smuzhiyun #define MUXENAB_BT_LEGACY 0x00002000 990*4882a593Smuzhiyun #define MUXENAB_HOST_WAKE1 0x00004000 /* configure alternative GPIO for SDIO host_wake */ 991*4882a593Smuzhiyun 992*4882a593Smuzhiyun /* Boot flags */ 993*4882a593Smuzhiyun #define FLASH_KERNEL_NFLASH 0x00000001 994*4882a593Smuzhiyun #define FLASH_BOOT_NFLASH 0x00000002 995*4882a593Smuzhiyun 996*4882a593Smuzhiyun #endif /* _BCMDEVS_H */ 997