1 /*
2 * Linux DHD Bus Module for PCIE
3 *
4 * Portions of this code are copyright (c) 2021 Cypress Semiconductor Corporation
5 *
6 * Copyright (C) 1999-2017, Broadcom Corporation
7 *
8 * Unless you and Broadcom execute a separate written software license
9 * agreement governing use of this software, this software is licensed to you
10 * under the terms of the GNU General Public License version 2 (the "GPL"),
11 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
12 * following added to such license:
13 *
14 * As a special exception, the copyright holders of this software give you
15 * permission to link this software with independent modules, and to copy and
16 * distribute the resulting executable under terms of your choice, provided that
17 * you also meet, for each linked independent module, the terms and conditions of
18 * the license of that module. An independent module is a module which is not
19 * derived from this software. The special exception does not apply to any
20 * modifications of the software.
21 *
22 * Notwithstanding the above, under no circumstances may you combine this
23 * software in any way with any other Broadcom software provided under a license
24 * other than the GPL, without Broadcom's express prior written consent.
25 *
26 *
27 * <<Broadcom-WL-IPTag/Open:>>
28 *
29 * $Id: dhd_pcie_linux.c 701741 2017-05-26 08:18:08Z $
30 */
31
32 /* include files */
33 #include <typedefs.h>
34 #include <bcmutils.h>
35 #include <bcmdevs.h>
36 #include <siutils.h>
37 #include <hndsoc.h>
38 #include <hndpmu.h>
39 #include <sbchipc.h>
40 #if defined(DHD_DEBUG)
41 #include <hnd_armtrap.h>
42 #include <hnd_cons.h>
43 #endif /* defined(DHD_DEBUG) */
44 #include <dngl_stats.h>
45 #include <pcie_core.h>
46 #include <dhd.h>
47 #include <dhd_bus.h>
48 #include <dhd_proto.h>
49 #include <dhd_dbg.h>
50 #include <dhdioctl.h>
51 #include <bcmmsgbuf.h>
52 #include <pcicfg.h>
53 #include <dhd_pcie.h>
54 #include <dhd_linux.h>
55 #ifdef OEM_ANDROID
56 #ifdef CONFIG_ARCH_MSM
57 #if defined(CONFIG_PCI_MSM) || defined(CONFIG_ARCH_MSM8996)
58 #include <linux/msm_pcie.h>
59 #else
60 #include <mach/msm_pcie.h>
61 #endif /* CONFIG_PCI_MSM */
62 #endif /* CONFIG_ARCH_MSM */
63 #endif /* OEM_ANDROID */
64
65 #ifdef DHD_PCIE_NATIVE_RUNTIMEPM
66 #include <linux/pm_runtime.h>
67 #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
68
69 #ifdef DHD_PCIE_NATIVE_RUNTIMEPM
70 #ifndef AUTO_SUSPEND_TIMEOUT
71 #define AUTO_SUSPEND_TIMEOUT 1000
72 #endif /* AUTO_SUSPEND_TIMEOUT */
73 #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
74
75 #include <linux/irq.h>
76 #ifdef USE_SMMU_ARCH_MSM
77 #include <asm/dma-iommu.h>
78 #include <linux/iommu.h>
79 #include <linux/of.h>
80 #include <linux/platform_device.h>
81 #endif /* USE_SMMU_ARCH_MSM */
82
83 #define PCI_CFG_RETRY 10
84 #define OS_HANDLE_MAGIC 0x1234abcd /* Magic # to recognize osh */
85 #define BCM_MEM_FILENAME_LEN 24 /* Mem. filename length */
86
87 #ifdef FORCE_TPOWERON
88 extern uint32 tpoweron_scale;
89 #endif /* FORCE_TPOWERON */
90 /* user defined data structures */
91
92 typedef bool (*dhdpcie_cb_fn_t)(void *);
93
94 typedef struct dhdpcie_info
95 {
96 dhd_bus_t *bus;
97 osl_t *osh;
98 struct pci_dev *dev; /* pci device handle */
99 volatile char *regs; /* pci device memory va */
100 volatile char *tcm; /* pci device memory va */
101 uint32 bar1_size; /* pci device memory size */
102 uint32 curr_bar1_win; /* current PCIEBar1Window setting */
103 struct pcos_info *pcos_info;
104 uint16 last_intrstatus; /* to cache intrstatus */
105 int irq;
106 char pciname[32];
107 struct pci_saved_state* default_state;
108 struct pci_saved_state* state;
109 #ifdef BCMPCIE_OOB_HOST_WAKE
110 void *os_cxt; /* Pointer to per-OS private data */
111 #endif /* BCMPCIE_OOB_HOST_WAKE */
112 #ifdef DHD_WAKE_STATUS
113 spinlock_t pcie_lock;
114 unsigned int total_wake_count;
115 int pkt_wake;
116 int wake_irq;
117 #endif /* DHD_WAKE_STATUS */
118 #ifdef USE_SMMU_ARCH_MSM
119 void *smmu_cxt;
120 #endif /* USE_SMMU_ARCH_MSM */
121 } dhdpcie_info_t;
122
123 struct pcos_info {
124 dhdpcie_info_t *pc;
125 spinlock_t lock;
126 wait_queue_head_t intr_wait_queue;
127 struct timer_list tuning_timer;
128 int tuning_timer_exp;
129 atomic_t timer_enab;
130 struct tasklet_struct tuning_tasklet;
131 };
132
133 #ifdef BCMPCIE_OOB_HOST_WAKE
134 typedef struct dhdpcie_os_info {
135 int oob_irq_num; /* valid when hardware or software oob in use */
136 unsigned long oob_irq_flags; /* valid when hardware or software oob in use */
137 bool oob_irq_registered;
138 bool oob_irq_enabled;
139 bool oob_irq_wake_enabled;
140 spinlock_t oob_irq_spinlock;
141 void *dev; /* handle to the underlying device */
142 } dhdpcie_os_info_t;
143 static irqreturn_t wlan_oob_irq(int irq, void *data);
144 #ifdef CUSTOMER_HW2
145 extern struct brcm_pcie_wake brcm_pcie_wake;
146 #endif /* CUSTOMER_HW2 */
147 #endif /* BCMPCIE_OOB_HOST_WAKE */
148
149 #ifdef USE_SMMU_ARCH_MSM
150 typedef struct dhdpcie_smmu_info {
151 struct dma_iommu_mapping *smmu_mapping;
152 dma_addr_t smmu_iova_start;
153 size_t smmu_iova_len;
154 } dhdpcie_smmu_info_t;
155 #endif /* USE_SMMU_ARCH_MSM */
156
157 /* function declarations */
158 static int __devinit
159 dhdpcie_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
160 static void __devexit
161 dhdpcie_pci_remove(struct pci_dev *pdev);
162 static int dhdpcie_init(struct pci_dev *pdev);
163 static irqreturn_t dhdpcie_isr(int irq, void *arg);
164 /* OS Routine functions for PCI suspend/resume */
165
166 #ifdef DHD_PCIE_NATIVE_RUNTIMEPM
167 static int dhdpcie_set_suspend_resume(struct pci_dev *dev, bool state, bool byint);
168 #else
169 static int dhdpcie_set_suspend_resume(dhd_bus_t *bus, bool state);
170 #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
171 static int dhdpcie_resume_host_dev(dhd_bus_t *bus);
172 static int dhdpcie_suspend_host_dev(dhd_bus_t *bus);
173 static int dhdpcie_resume_dev(struct pci_dev *dev);
174 static int dhdpcie_suspend_dev(struct pci_dev *dev);
175 #ifdef DHD_PCIE_RUNTIMEPM
176 static int dhdpcie_pm_suspend(struct device *dev);
177 static int dhdpcie_pm_prepare(struct device *dev);
178 static int dhdpcie_pm_resume(struct device *dev);
179 static void dhdpcie_pm_complete(struct device *dev);
180 #else
181 #ifdef DHD_PCIE_NATIVE_RUNTIMEPM
182 static int dhdpcie_pm_system_suspend_noirq(struct device * dev);
183 static int dhdpcie_pm_system_resume_noirq(struct device * dev);
184 #else
185 static int dhdpcie_pci_suspend(struct pci_dev *dev, pm_message_t state);
186 static int dhdpcie_pci_resume(struct pci_dev *dev);
187 #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
188 #endif /* DHD_PCIE_RUNTIMEPM */
189
190 #ifdef DHD_PCIE_NATIVE_RUNTIMEPM
191 static int dhdpcie_pm_runtime_suspend(struct device * dev);
192 static int dhdpcie_pm_runtime_resume(struct device * dev);
193 static int dhdpcie_pm_system_suspend_noirq(struct device * dev);
194 static int dhdpcie_pm_system_resume_noirq(struct device * dev);
195 #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
196
197 static void dhdpcie_config_save_restore_coherent(dhd_bus_t *bus, bool state);
198
199 uint32
200 dhdpcie_access_cap(struct pci_dev *pdev, int cap, uint offset, bool is_ext, bool is_write,
201 uint32 writeval);
202
203 static struct pci_device_id dhdpcie_pci_devid[] __devinitdata = {
204 {
205 vendor: VENDOR_CYPRESS,
206 device: PCI_ANY_ID,
207 subvendor: PCI_ANY_ID,
208 subdevice: PCI_ANY_ID,
209 class: PCI_CLASS_NETWORK_OTHER << 8,
210 class_mask: 0xffff00,
211 driver_data: 0,
212 },
213 {
214 vendor: VENDOR_BROADCOM,
215 device: PCI_ANY_ID,
216 subvendor: PCI_ANY_ID,
217 subdevice: PCI_ANY_ID,
218 class: PCI_CLASS_NETWORK_OTHER << 8,
219 class_mask: 0xffff00,
220 driver_data: 0,
221 },
222 { 0, 0, 0, 0, 0, 0, 0}
223 };
224 MODULE_DEVICE_TABLE(pci, dhdpcie_pci_devid);
225
226 /* Power Management Hooks */
227 #ifdef DHD_PCIE_RUNTIMEPM
228 static const struct dev_pm_ops dhd_pcie_pm_ops = {
229 .prepare = dhdpcie_pm_prepare,
230 .suspend = dhdpcie_pm_suspend,
231 .resume = dhdpcie_pm_resume,
232 .complete = dhdpcie_pm_complete,
233 };
234 #endif /* DHD_PCIE_RUNTIMEPM */
235 #ifdef DHD_PCIE_NATIVE_RUNTIMEPM
236 static const struct dev_pm_ops dhdpcie_pm_ops = {
237 SET_RUNTIME_PM_OPS(dhdpcie_pm_runtime_suspend, dhdpcie_pm_runtime_resume, NULL)
238 .suspend_noirq = dhdpcie_pm_system_suspend_noirq,
239 .resume_noirq = dhdpcie_pm_system_resume_noirq
240 };
241 #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
242
243 static struct pci_driver dhdpcie_driver = {
244 node: {&dhdpcie_driver.node, &dhdpcie_driver.node},
245 #ifndef BCMDHDX
246 name: "pcieh",
247 #else
248 name: "pciehx",
249 #endif /* BCMDHDX */
250 id_table: dhdpcie_pci_devid,
251 probe: dhdpcie_pci_probe,
252 remove: dhdpcie_pci_remove,
253 #if defined(DHD_PCIE_RUNTIMEPM) || defined(DHD_PCIE_NATIVE_RUNTIMEPM)
254 .driver.pm = &dhd_pcie_pm_ops,
255 #else
256 suspend: dhdpcie_pci_suspend,
257 resume: dhdpcie_pci_resume,
258 #endif /* DHD_PCIE_RUNTIMEPM || DHD_PCIE_NATIVE_RUNTIMEPM */
259 };
260
261 int dhdpcie_init_succeeded = FALSE;
262
263 #ifdef USE_SMMU_ARCH_MSM
dhdpcie_smmu_init(struct pci_dev * pdev,void * smmu_cxt)264 static int dhdpcie_smmu_init(struct pci_dev *pdev, void *smmu_cxt)
265 {
266 struct dma_iommu_mapping *mapping;
267 struct device_node *root_node = NULL;
268 dhdpcie_smmu_info_t *smmu_info = (dhdpcie_smmu_info_t *)smmu_cxt;
269 int smmu_iova_address[2];
270 char *wlan_node = "android,bcmdhd_wlan";
271 char *wlan_smmu_node = "wlan-smmu-iova-address";
272 int atomic_ctx = 1;
273 int s1_bypass = 1;
274 int ret = 0;
275
276 DHD_ERROR(("%s: SMMU initialize\n", __FUNCTION__));
277
278 root_node = of_find_compatible_node(NULL, NULL, wlan_node);
279 if (!root_node) {
280 WARN(1, "failed to get device node of BRCM WLAN\n");
281 return -ENODEV;
282 }
283
284 if (of_property_read_u32_array(root_node, wlan_smmu_node,
285 smmu_iova_address, 2) == 0) {
286 DHD_ERROR(("%s : get SMMU start address 0x%x, size 0x%x\n",
287 __FUNCTION__, smmu_iova_address[0], smmu_iova_address[1]));
288 smmu_info->smmu_iova_start = smmu_iova_address[0];
289 smmu_info->smmu_iova_len = smmu_iova_address[1];
290 } else {
291 printf("%s : can't get smmu iova address property\n",
292 __FUNCTION__);
293 return -ENODEV;
294 }
295
296 if (smmu_info->smmu_iova_len <= 0) {
297 DHD_ERROR(("%s: Invalid smmu iova len %d\n",
298 __FUNCTION__, (int)smmu_info->smmu_iova_len));
299 return -EINVAL;
300 }
301
302 DHD_ERROR(("%s : SMMU init start\n", __FUNCTION__));
303
304 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) ||
305 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
306 DHD_ERROR(("%s: DMA set 64bit mask failed.\n", __FUNCTION__));
307 return -EINVAL;
308 }
309
310 mapping = arm_iommu_create_mapping(&platform_bus_type,
311 smmu_info->smmu_iova_start, smmu_info->smmu_iova_len);
312 if (IS_ERR(mapping)) {
313 DHD_ERROR(("%s: create mapping failed, err = %d\n",
314 __FUNCTION__, ret));
315 ret = PTR_ERR(mapping);
316 goto map_fail;
317 }
318
319 ret = iommu_domain_set_attr(mapping->domain,
320 DOMAIN_ATTR_ATOMIC, &atomic_ctx);
321 if (ret) {
322 DHD_ERROR(("%s: set atomic_ctx attribute failed, err = %d\n",
323 __FUNCTION__, ret));
324 goto set_attr_fail;
325 }
326
327 ret = iommu_domain_set_attr(mapping->domain,
328 DOMAIN_ATTR_S1_BYPASS, &s1_bypass);
329 if (ret < 0) {
330 DHD_ERROR(("%s: set s1_bypass attribute failed, err = %d\n",
331 __FUNCTION__, ret));
332 goto set_attr_fail;
333 }
334
335 ret = arm_iommu_attach_device(&pdev->dev, mapping);
336 if (ret) {
337 DHD_ERROR(("%s: attach device failed, err = %d\n",
338 __FUNCTION__, ret));
339 goto attach_fail;
340 }
341
342 smmu_info->smmu_mapping = mapping;
343
344 return ret;
345
346 attach_fail:
347 set_attr_fail:
348 arm_iommu_release_mapping(mapping);
349 map_fail:
350 return ret;
351 }
352
dhdpcie_smmu_remove(struct pci_dev * pdev,void * smmu_cxt)353 static void dhdpcie_smmu_remove(struct pci_dev *pdev, void *smmu_cxt)
354 {
355 dhdpcie_smmu_info_t *smmu_info;
356
357 if (!smmu_cxt) {
358 return;
359 }
360
361 smmu_info = (dhdpcie_smmu_info_t *)smmu_cxt;
362 if (smmu_info->smmu_mapping) {
363 arm_iommu_detach_device(&pdev->dev);
364 arm_iommu_release_mapping(smmu_info->smmu_mapping);
365 smmu_info->smmu_mapping = NULL;
366 }
367 }
368 #endif /* USE_SMMU_ARCH_MSM */
369
370 #ifdef FORCE_TPOWERON
371 static void
dhd_bus_get_tpoweron(dhd_bus_t * bus)372 dhd_bus_get_tpoweron(dhd_bus_t *bus)
373 {
374
375 uint32 tpoweron_rc;
376 uint32 tpoweron_ep;
377
378 tpoweron_rc = dhdpcie_rc_access_cap(bus, PCIE_EXTCAP_ID_L1SS,
379 PCIE_EXTCAP_L1SS_CONTROL2_OFFSET, TRUE, FALSE, 0);
380 tpoweron_ep = dhdpcie_ep_access_cap(bus, PCIE_EXTCAP_ID_L1SS,
381 PCIE_EXTCAP_L1SS_CONTROL2_OFFSET, TRUE, FALSE, 0);
382 DHD_ERROR(("%s: tpoweron_rc:0x%x tpoweron_ep:0x%x\n",
383 __FUNCTION__, tpoweron_rc, tpoweron_ep));
384 }
385
386 static void
dhd_bus_set_tpoweron(dhd_bus_t * bus,uint16 tpoweron)387 dhd_bus_set_tpoweron(dhd_bus_t *bus, uint16 tpoweron)
388 {
389
390 dhd_bus_get_tpoweron(bus);
391 /* Set the tpoweron */
392 DHD_ERROR(("%s tpoweron: 0x%x\n", __FUNCTION__, tpoweron));
393 dhdpcie_rc_access_cap(bus, PCIE_EXTCAP_ID_L1SS,
394 PCIE_EXTCAP_L1SS_CONTROL2_OFFSET, TRUE, TRUE, tpoweron);
395 dhdpcie_ep_access_cap(bus, PCIE_EXTCAP_ID_L1SS,
396 PCIE_EXTCAP_L1SS_CONTROL2_OFFSET, TRUE, TRUE, tpoweron);
397
398 dhd_bus_get_tpoweron(bus);
399
400 }
401
402 static bool
dhdpcie_chip_req_forced_tpoweron(dhd_bus_t * bus)403 dhdpcie_chip_req_forced_tpoweron(dhd_bus_t *bus)
404 {
405 /*
406 * On Fire's reference platform, coming out of L1.2,
407 * there is a constant delay of 45us between CLKREQ# and stable REFCLK
408 * Due to this delay, with tPowerOn < 50
409 * there is a chance of the refclk sense to trigger on noise.
410 *
411 * Which ever chip needs forced tPowerOn of 50us should be listed below.
412 */
413 if (si_chipid(bus->sih) == BCM4377_CHIP_ID) {
414 return TRUE;
415 }
416 return FALSE;
417 }
418 #endif /* FORCE_TPOWERON */
419
420 static bool
dhd_bus_aspm_enable_dev(dhd_bus_t * bus,struct pci_dev * dev,bool enable)421 dhd_bus_aspm_enable_dev(dhd_bus_t *bus, struct pci_dev *dev, bool enable)
422 {
423 uint32 linkctrl_before;
424 uint32 linkctrl_after = 0;
425 uint8 linkctrl_asm;
426 char *device;
427
428 device = (dev == bus->dev) ? "EP" : "RC";
429
430 linkctrl_before = dhdpcie_access_cap(dev, PCIE_CAP_ID_EXP, PCIE_CAP_LINKCTRL_OFFSET,
431 FALSE, FALSE, 0);
432 linkctrl_asm = (linkctrl_before & PCIE_ASPM_CTRL_MASK);
433
434 if (enable) {
435 if (linkctrl_asm == PCIE_ASPM_L1_ENAB) {
436 DHD_ERROR(("%s: %s already enabled linkctrl: 0x%x\n",
437 __FUNCTION__, device, linkctrl_before));
438 return FALSE;
439 }
440 /* Enable only L1 ASPM (bit 1) */
441 dhdpcie_access_cap(dev, PCIE_CAP_ID_EXP, PCIE_CAP_LINKCTRL_OFFSET, FALSE,
442 TRUE, (linkctrl_before | PCIE_ASPM_L1_ENAB));
443 } else {
444 if (linkctrl_asm == 0) {
445 DHD_ERROR(("%s: %s already disabled linkctrl: 0x%x\n",
446 __FUNCTION__, device, linkctrl_before));
447 return FALSE;
448 }
449 /* Disable complete ASPM (bit 1 and bit 0) */
450 dhdpcie_access_cap(dev, PCIE_CAP_ID_EXP, PCIE_CAP_LINKCTRL_OFFSET, FALSE,
451 TRUE, (linkctrl_before & (~PCIE_ASPM_ENAB)));
452 }
453
454 linkctrl_after = dhdpcie_access_cap(dev, PCIE_CAP_ID_EXP, PCIE_CAP_LINKCTRL_OFFSET,
455 FALSE, FALSE, 0);
456 DHD_ERROR(("%s: %s %s, linkctrl_before: 0x%x linkctrl_after: 0x%x\n",
457 __FUNCTION__, device, (enable ? "ENABLE " : "DISABLE"),
458 linkctrl_before, linkctrl_after));
459
460 return TRUE;
461 }
462
463 static bool
dhd_bus_is_rc_ep_aspm_capable(dhd_bus_t * bus)464 dhd_bus_is_rc_ep_aspm_capable(dhd_bus_t *bus)
465 {
466 uint32 rc_aspm_cap;
467 uint32 ep_aspm_cap;
468
469 /* RC ASPM capability */
470 rc_aspm_cap = dhdpcie_access_cap(bus->rc_dev, PCIE_CAP_ID_EXP, PCIE_CAP_LINKCTRL_OFFSET,
471 FALSE, FALSE, 0);
472 if (rc_aspm_cap == BCME_ERROR) {
473 DHD_ERROR(("%s RC is not ASPM capable\n", __FUNCTION__));
474 return FALSE;
475 }
476
477 /* EP ASPM capability */
478 ep_aspm_cap = dhdpcie_access_cap(bus->dev, PCIE_CAP_ID_EXP, PCIE_CAP_LINKCTRL_OFFSET,
479 FALSE, FALSE, 0);
480 if (ep_aspm_cap == BCME_ERROR) {
481 DHD_ERROR(("%s EP is not ASPM capable\n", __FUNCTION__));
482 return FALSE;
483 }
484
485 return TRUE;
486 }
487
488 bool
dhd_bus_aspm_enable_rc_ep(dhd_bus_t * bus,bool enable)489 dhd_bus_aspm_enable_rc_ep(dhd_bus_t *bus, bool enable)
490 {
491 bool ret;
492
493 if (!bus->rc_ep_aspm_cap) {
494 DHD_ERROR(("%s: NOT ASPM CAPABLE rc_ep_aspm_cap: %d\n",
495 __FUNCTION__, bus->rc_ep_aspm_cap));
496 return FALSE;
497 }
498
499 if (enable) {
500 /* Enable only L1 ASPM first RC then EP */
501 ret = dhd_bus_aspm_enable_dev(bus, bus->rc_dev, enable);
502 ret = dhd_bus_aspm_enable_dev(bus, bus->dev, enable);
503 } else {
504 /* Disable complete ASPM first EP then RC */
505 ret = dhd_bus_aspm_enable_dev(bus, bus->dev, enable);
506 ret = dhd_bus_aspm_enable_dev(bus, bus->rc_dev, enable);
507 }
508
509 return ret;
510 }
511
512 static void
dhd_bus_l1ss_enable_dev(dhd_bus_t * bus,struct pci_dev * dev,bool enable)513 dhd_bus_l1ss_enable_dev(dhd_bus_t *bus, struct pci_dev *dev, bool enable)
514 {
515 uint32 l1ssctrl_before;
516 uint32 l1ssctrl_after = 0;
517 uint8 l1ss_ep;
518 char *device;
519
520 device = (dev == bus->dev) ? "EP" : "RC";
521
522 /* Extendend Capacility Reg */
523 l1ssctrl_before = dhdpcie_access_cap(dev, PCIE_EXTCAP_ID_L1SS,
524 PCIE_EXTCAP_L1SS_CONTROL_OFFSET, TRUE, FALSE, 0);
525 l1ss_ep = (l1ssctrl_before & PCIE_EXT_L1SS_MASK);
526
527 if (enable) {
528 if (l1ss_ep == PCIE_EXT_L1SS_ENAB) {
529 DHD_ERROR(("%s: %s already enabled, l1ssctrl: 0x%x\n",
530 __FUNCTION__, device, l1ssctrl_before));
531 return;
532 }
533 dhdpcie_access_cap(dev, PCIE_EXTCAP_ID_L1SS, PCIE_EXTCAP_L1SS_CONTROL_OFFSET,
534 TRUE, TRUE, (l1ssctrl_before | PCIE_EXT_L1SS_ENAB));
535 } else {
536 if (l1ss_ep == 0) {
537 DHD_ERROR(("%s: %s already disabled, l1ssctrl: 0x%x\n",
538 __FUNCTION__, device, l1ssctrl_before));
539 return;
540 }
541 dhdpcie_access_cap(dev, PCIE_EXTCAP_ID_L1SS, PCIE_EXTCAP_L1SS_CONTROL_OFFSET,
542 TRUE, TRUE, (l1ssctrl_before & (~PCIE_EXT_L1SS_ENAB)));
543 }
544 l1ssctrl_after = dhdpcie_access_cap(dev, PCIE_EXTCAP_ID_L1SS,
545 PCIE_EXTCAP_L1SS_CONTROL_OFFSET, TRUE, FALSE, 0);
546 DHD_ERROR(("%s: %s %s, l1ssctrl_before: 0x%x l1ssctrl_after: 0x%x\n",
547 __FUNCTION__, device, (enable ? "ENABLE " : "DISABLE"),
548 l1ssctrl_before, l1ssctrl_after));
549
550 }
551
552 static bool
dhd_bus_is_rc_ep_l1ss_capable(dhd_bus_t * bus)553 dhd_bus_is_rc_ep_l1ss_capable(dhd_bus_t *bus)
554 {
555 uint32 rc_l1ss_cap;
556 uint32 ep_l1ss_cap;
557
558 /* RC Extendend Capacility */
559 rc_l1ss_cap = dhdpcie_access_cap(bus->rc_dev, PCIE_EXTCAP_ID_L1SS,
560 PCIE_EXTCAP_L1SS_CONTROL_OFFSET, TRUE, FALSE, 0);
561 if (rc_l1ss_cap == BCME_ERROR) {
562 DHD_ERROR(("%s RC is not l1ss capable\n", __FUNCTION__));
563 return FALSE;
564 }
565
566 /* EP Extendend Capacility */
567 ep_l1ss_cap = dhdpcie_access_cap(bus->dev, PCIE_EXTCAP_ID_L1SS,
568 PCIE_EXTCAP_L1SS_CONTROL_OFFSET, TRUE, FALSE, 0);
569 if (ep_l1ss_cap == BCME_ERROR) {
570 DHD_ERROR(("%s EP is not l1ss capable\n", __FUNCTION__));
571 return FALSE;
572 }
573
574 return TRUE;
575 }
576
577 void
dhd_bus_l1ss_enable_rc_ep(dhd_bus_t * bus,bool enable)578 dhd_bus_l1ss_enable_rc_ep(dhd_bus_t *bus, bool enable)
579 {
580 bool ret;
581
582 if ((!bus->rc_ep_aspm_cap) || (!bus->rc_ep_l1ss_cap)) {
583 DHD_ERROR(("%s: NOT L1SS CAPABLE rc_ep_aspm_cap: %d rc_ep_l1ss_cap: %d\n",
584 __FUNCTION__, bus->rc_ep_aspm_cap, bus->rc_ep_l1ss_cap));
585 return;
586 }
587
588 /* Disable ASPM of RC and EP */
589 ret = dhd_bus_aspm_enable_rc_ep(bus, FALSE);
590
591 if (enable) {
592 /* Enable RC then EP */
593 dhd_bus_l1ss_enable_dev(bus, bus->rc_dev, enable);
594 dhd_bus_l1ss_enable_dev(bus, bus->dev, enable);
595 } else {
596 /* Disable EP then RC */
597 dhd_bus_l1ss_enable_dev(bus, bus->dev, enable);
598 dhd_bus_l1ss_enable_dev(bus, bus->rc_dev, enable);
599 }
600
601 /* Enable ASPM of RC and EP only if this API disabled */
602 if (ret == TRUE) {
603 dhd_bus_aspm_enable_rc_ep(bus, TRUE);
604 }
605 }
606
607 void
dhd_bus_aer_config(dhd_bus_t * bus)608 dhd_bus_aer_config(dhd_bus_t *bus)
609 {
610 uint32 val;
611
612 DHD_ERROR(("%s: Configure AER registers for EP\n", __FUNCTION__));
613 val = dhdpcie_ep_access_cap(bus, PCIE_ADVERRREP_CAPID,
614 PCIE_ADV_CORR_ERR_MASK_OFFSET, TRUE, FALSE, 0);
615 if (val != (uint32)-1) {
616 val &= ~CORR_ERR_AE;
617 dhdpcie_ep_access_cap(bus, PCIE_ADVERRREP_CAPID,
618 PCIE_ADV_CORR_ERR_MASK_OFFSET, TRUE, TRUE, val);
619 } else {
620 DHD_ERROR(("%s: Invalid EP's PCIE_ADV_CORR_ERR_MASK: 0x%x\n",
621 __FUNCTION__, val));
622 }
623
624 DHD_ERROR(("%s: Configure AER registers for RC\n", __FUNCTION__));
625 val = dhdpcie_rc_access_cap(bus, PCIE_ADVERRREP_CAPID,
626 PCIE_ADV_CORR_ERR_MASK_OFFSET, TRUE, FALSE, 0);
627 if (val != (uint32)-1) {
628 val &= ~CORR_ERR_AE;
629 dhdpcie_rc_access_cap(bus, PCIE_ADVERRREP_CAPID,
630 PCIE_ADV_CORR_ERR_MASK_OFFSET, TRUE, TRUE, val);
631 } else {
632 DHD_ERROR(("%s: Invalid RC's PCIE_ADV_CORR_ERR_MASK: 0x%x\n",
633 __FUNCTION__, val));
634 }
635 }
636
637 #ifdef DHD_PCIE_RUNTIMEPM
dhdpcie_pm_suspend(struct device * dev)638 static int dhdpcie_pm_suspend(struct device *dev)
639 {
640 int ret = 0;
641 struct pci_dev *pdev = to_pci_dev(dev);
642 dhdpcie_info_t *pch = pci_get_drvdata(pdev);
643 dhd_bus_t *bus = NULL;
644 unsigned long flags;
645
646 if (pch) {
647 bus = pch->bus;
648 }
649 if (!bus) {
650 return ret;
651 }
652
653 DHD_GENERAL_LOCK(bus->dhd, flags);
654 if (!DHD_BUS_BUSY_CHECK_IDLE(bus->dhd)) {
655 DHD_ERROR(("%s: Bus not IDLE!! dhd_bus_busy_state = 0x%x\n",
656 __FUNCTION__, bus->dhd->dhd_bus_busy_state));
657 DHD_GENERAL_UNLOCK(bus->dhd, flags);
658 return -EBUSY;
659 }
660 DHD_BUS_BUSY_SET_SUSPEND_IN_PROGRESS(bus->dhd);
661 DHD_GENERAL_UNLOCK(bus->dhd, flags);
662
663 if (!bus->dhd->dongle_reset)
664 ret = dhdpcie_set_suspend_resume(bus, TRUE);
665
666 DHD_GENERAL_LOCK(bus->dhd, flags);
667 DHD_BUS_BUSY_CLEAR_SUSPEND_IN_PROGRESS(bus->dhd);
668 dhd_os_busbusy_wake(bus->dhd);
669 DHD_GENERAL_UNLOCK(bus->dhd, flags);
670
671 return ret;
672
673 }
674
dhdpcie_pm_prepare(struct device * dev)675 static int dhdpcie_pm_prepare(struct device *dev)
676 {
677 struct pci_dev *pdev = to_pci_dev(dev);
678 dhdpcie_info_t *pch = pci_get_drvdata(pdev);
679 dhd_bus_t *bus = NULL;
680
681 if (!pch || !pch->bus) {
682 return 0;
683 }
684
685 bus = pch->bus;
686 DHD_DISABLE_RUNTIME_PM(bus->dhd);
687 bus->chk_pm = TRUE;
688
689 return 0;
690 }
691
dhdpcie_pm_resume(struct device * dev)692 static int dhdpcie_pm_resume(struct device *dev)
693 {
694 int ret = 0;
695 struct pci_dev *pdev = to_pci_dev(dev);
696 dhdpcie_info_t *pch = pci_get_drvdata(pdev);
697 dhd_bus_t *bus = NULL;
698 unsigned long flags;
699
700 if (pch) {
701 bus = pch->bus;
702 }
703 if (!bus) {
704 return ret;
705 }
706
707 DHD_GENERAL_LOCK(bus->dhd, flags);
708 DHD_BUS_BUSY_SET_RESUME_IN_PROGRESS(bus->dhd);
709 DHD_GENERAL_UNLOCK(bus->dhd, flags);
710
711 if (!bus->dhd->dongle_reset)
712 ret = dhdpcie_set_suspend_resume(bus, FALSE);
713
714 DHD_GENERAL_LOCK(bus->dhd, flags);
715 DHD_BUS_BUSY_CLEAR_RESUME_IN_PROGRESS(bus->dhd);
716 dhd_os_busbusy_wake(bus->dhd);
717 DHD_GENERAL_UNLOCK(bus->dhd, flags);
718
719 return ret;
720 }
721
dhdpcie_pm_complete(struct device * dev)722 static void dhdpcie_pm_complete(struct device *dev)
723 {
724 struct pci_dev *pdev = to_pci_dev(dev);
725 dhdpcie_info_t *pch = pci_get_drvdata(pdev);
726 dhd_bus_t *bus = NULL;
727
728 if (!pch || !pch->bus) {
729 return;
730 }
731
732 bus = pch->bus;
733 DHD_ENABLE_RUNTIME_PM(bus->dhd);
734 bus->chk_pm = FALSE;
735
736 return;
737 }
738 #else
dhdpcie_pci_suspend(struct pci_dev * pdev,pm_message_t state)739 static int dhdpcie_pci_suspend(struct pci_dev * pdev, pm_message_t state)
740 {
741 int ret = 0;
742 dhdpcie_info_t *pch = pci_get_drvdata(pdev);
743 dhd_bus_t *bus = NULL;
744 unsigned long flags;
745
746 if (pch) {
747 bus = pch->bus;
748 }
749 if (!bus) {
750 return ret;
751 }
752
753 BCM_REFERENCE(state);
754
755 DHD_GENERAL_LOCK(bus->dhd, flags);
756 if (!DHD_BUS_BUSY_CHECK_IDLE(bus->dhd)) {
757 DHD_ERROR(("%s: Bus not IDLE!! dhd_bus_busy_state = 0x%x\n",
758 __FUNCTION__, bus->dhd->dhd_bus_busy_state));
759 DHD_GENERAL_UNLOCK(bus->dhd, flags);
760 return -EBUSY;
761 }
762 DHD_BUS_BUSY_SET_SUSPEND_IN_PROGRESS(bus->dhd);
763 DHD_GENERAL_UNLOCK(bus->dhd, flags);
764
765 if (!bus->dhd->dongle_reset)
766 ret = dhdpcie_set_suspend_resume(bus, TRUE);
767
768 DHD_GENERAL_LOCK(bus->dhd, flags);
769 DHD_BUS_BUSY_CLEAR_SUSPEND_IN_PROGRESS(bus->dhd);
770 dhd_os_busbusy_wake(bus->dhd);
771 DHD_GENERAL_UNLOCK(bus->dhd, flags);
772
773 return ret;
774 }
775
dhdpcie_pci_resume(struct pci_dev * pdev)776 static int dhdpcie_pci_resume(struct pci_dev *pdev)
777 {
778 int ret = 0;
779 dhdpcie_info_t *pch = pci_get_drvdata(pdev);
780 dhd_bus_t *bus = NULL;
781 unsigned long flags;
782
783 if (pch) {
784 bus = pch->bus;
785 }
786 if (!bus) {
787 return ret;
788 }
789
790 DHD_GENERAL_LOCK(bus->dhd, flags);
791 DHD_BUS_BUSY_SET_RESUME_IN_PROGRESS(bus->dhd);
792 DHD_GENERAL_UNLOCK(bus->dhd, flags);
793
794 if (!bus->dhd->dongle_reset)
795 ret = dhdpcie_set_suspend_resume(bus, FALSE);
796
797 DHD_GENERAL_LOCK(bus->dhd, flags);
798 DHD_BUS_BUSY_CLEAR_RESUME_IN_PROGRESS(bus->dhd);
799 dhd_os_busbusy_wake(bus->dhd);
800 DHD_GENERAL_UNLOCK(bus->dhd, flags);
801
802 return ret;
803 }
804
805 #endif /* DHD_PCIE_RUNTIMEPM */
806 #ifdef DHD_PCIE_NATIVE_RUNTIMEPM
dhdpcie_set_suspend_resume(dhd_bus_t * bus,bool state,bool byint)807 static int dhdpcie_set_suspend_resume(dhd_bus_t *bus, bool state, bool byint)
808 #else
809 static int dhdpcie_set_suspend_resume(dhd_bus_t *bus, bool state)
810 #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
811 {
812 int ret = 0;
813
814 ASSERT(bus && !bus->dhd->dongle_reset);
815
816 #ifdef DHD_PCIE_RUNTIMEPM
817 /* if wakelock is held during suspend, return failed */
818 if (state == TRUE && dhd_os_check_wakelock_all(bus->dhd)) {
819 return -EBUSY;
820 }
821 mutex_lock(&bus->pm_lock);
822 #endif /* DHD_PCIE_RUNTIMEPM */
823
824 /* When firmware is not loaded do the PCI bus */
825 /* suspend/resume only */
826 if (bus->dhd->busstate == DHD_BUS_DOWN) {
827 ret = dhdpcie_pci_suspend_resume(bus, state);
828 #ifdef DHD_PCIE_RUNTIMEPM
829 mutex_unlock(&bus->pm_lock);
830 #endif /* DHD_PCIE_RUNTIMEPM */
831 return ret;
832 }
833 #ifdef DHD_PCIE_NATIVE_RUNTIMEPM
834 ret = dhdpcie_bus_suspend(bus, state, byint);
835 #else
836 ret = dhdpcie_bus_suspend(bus, state);
837 #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
838
839 #ifdef DHD_PCIE_RUNTIMEPM
840 mutex_unlock(&bus->pm_lock);
841 #endif /* DHD_PCIE_RUNTIMEPM */
842
843 return ret;
844 }
845
846 #ifdef DHD_PCIE_NATIVE_RUNTIMEPM
dhdpcie_pm_runtime_suspend(struct device * dev)847 static int dhdpcie_pm_runtime_suspend(struct device * dev)
848 {
849 struct pci_dev *pdev = to_pci_dev(dev);
850 dhdpcie_info_t *pch = pci_get_drvdata(pdev);
851 dhd_bus_t *bus = NULL;
852 int ret = 0;
853
854 if (!pch)
855 return -EBUSY;
856
857 bus = pch->bus;
858
859 DHD_RPM(("%s Enter\n", __FUNCTION__));
860
861 if (atomic_read(&bus->dhd->block_bus))
862 return -EHOSTDOWN;
863
864 dhd_netif_stop_queue(bus);
865 atomic_set(&bus->dhd->block_bus, TRUE);
866
867 if (dhdpcie_set_suspend_resume(pdev, TRUE, TRUE)) {
868 pm_runtime_mark_last_busy(dev);
869 ret = -EAGAIN;
870 }
871
872 atomic_set(&bus->dhd->block_bus, FALSE);
873 dhd_bus_start_queue(bus);
874
875 return ret;
876 }
877
dhdpcie_pm_runtime_resume(struct device * dev)878 static int dhdpcie_pm_runtime_resume(struct device * dev)
879 {
880 struct pci_dev *pdev = to_pci_dev(dev);
881 dhdpcie_info_t *pch = pci_get_drvdata(pdev);
882 dhd_bus_t *bus = pch->bus;
883
884 DHD_RPM(("%s Enter\n", __FUNCTION__));
885
886 if (atomic_read(&bus->dhd->block_bus))
887 return -EHOSTDOWN;
888
889 if (dhdpcie_set_suspend_resume(pdev, FALSE, TRUE))
890 return -EAGAIN;
891
892 return 0;
893 }
894
dhdpcie_pm_system_suspend_noirq(struct device * dev)895 static int dhdpcie_pm_system_suspend_noirq(struct device * dev)
896 {
897 struct pci_dev *pdev = to_pci_dev(dev);
898 dhdpcie_info_t *pch = pci_get_drvdata(pdev);
899 dhd_bus_t *bus = NULL;
900 int ret;
901
902 DHD_RPM(("%s Enter\n", __FUNCTION__));
903
904 if (!pch)
905 return -EBUSY;
906
907 bus = pch->bus;
908
909 if (atomic_read(&bus->dhd->block_bus))
910 return -EHOSTDOWN;
911
912 dhd_netif_stop_queue(bus);
913 atomic_set(&bus->dhd->block_bus, TRUE);
914
915 ret = dhdpcie_set_suspend_resume(pdev, TRUE, FALSE);
916
917 if (ret) {
918 dhd_bus_start_queue(bus);
919 atomic_set(&bus->dhd->block_bus, FALSE);
920 }
921
922 return ret;
923 }
924
dhdpcie_pm_system_resume_noirq(struct device * dev)925 static int dhdpcie_pm_system_resume_noirq(struct device * dev)
926 {
927 struct pci_dev *pdev = to_pci_dev(dev);
928 dhdpcie_info_t *pch = pci_get_drvdata(pdev);
929 dhd_bus_t *bus = NULL;
930 int ret;
931
932 if (!pch)
933 return -EBUSY;
934
935 bus = pch->bus;
936
937 DHD_RPM(("%s Enter\n", __FUNCTION__));
938
939 ret = dhdpcie_set_suspend_resume(pdev, FALSE, FALSE);
940
941 atomic_set(&bus->dhd->block_bus, FALSE);
942 dhd_bus_start_queue(bus);
943 pm_runtime_mark_last_busy(dhd_bus_to_dev(bus));
944
945 return ret;
946 }
947 #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
948
949 #if defined(OEM_ANDROID) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
950 extern void dhd_dpc_tasklet_kill(dhd_pub_t *dhdp);
951 #endif /* OEM_ANDROID && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
952
953 static void
dhdpcie_suspend_dump_cfgregs(struct dhd_bus * bus,char * suspend_state)954 dhdpcie_suspend_dump_cfgregs(struct dhd_bus *bus, char *suspend_state)
955 {
956 DHD_ERROR(("%s: BaseAddress0(0x%x)=0x%x, "
957 "BaseAddress1(0x%x)=0x%x PCIE_CFG_PMCSR(0x%x)=0x%x\n",
958 suspend_state,
959 PCIECFGREG_BASEADDR0,
960 dhd_pcie_config_read(bus->osh,
961 PCIECFGREG_BASEADDR0, sizeof(uint32)),
962 PCIECFGREG_BASEADDR1,
963 dhd_pcie_config_read(bus->osh,
964 PCIECFGREG_BASEADDR1, sizeof(uint32)),
965 PCIE_CFG_PMCSR,
966 dhd_pcie_config_read(bus->osh,
967 PCIE_CFG_PMCSR, sizeof(uint32))));
968 }
969
dhdpcie_suspend_dev(struct pci_dev * dev)970 static int dhdpcie_suspend_dev(struct pci_dev *dev)
971 {
972 int ret;
973 dhdpcie_info_t *pch = pci_get_drvdata(dev);
974 dhd_bus_t *bus = pch->bus;
975
976 #if defined(OEM_ANDROID) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
977 if (bus->is_linkdown) {
978 DHD_ERROR(("%s: PCIe link is down\n", __FUNCTION__));
979 return BCME_ERROR;
980 }
981 #endif /* OEM_ANDROID && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
982 DHD_ERROR(("%s: Enter\n", __FUNCTION__));
983 dhdpcie_suspend_dump_cfgregs(bus, "BEFORE_EP_SUSPEND");
984 #if defined(OEM_ANDROID) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
985 dhd_dpc_tasklet_kill(bus->dhd);
986 #endif /* OEM_ANDROID && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
987 pci_save_state(dev);
988 #if defined(OEM_ANDROID) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
989 pch->state = pci_store_saved_state(dev);
990 #endif /* OEM_ANDROID && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
991 pci_enable_wake(dev, PCI_D0, TRUE);
992 if (pci_is_enabled(dev))
993 pci_disable_device(dev);
994
995 ret = pci_set_power_state(dev, PCI_D3hot);
996 if (ret) {
997 DHD_ERROR(("%s: pci_set_power_state error %d\n",
998 __FUNCTION__, ret));
999 }
1000 #ifdef OEM_ANDROID
1001 dev->state_saved = FALSE;
1002 #endif /* OEM_ANDROID */
1003 dhdpcie_suspend_dump_cfgregs(bus, "AFTER_EP_SUSPEND");
1004 return ret;
1005 }
1006
1007 #ifdef DHD_WAKE_STATUS
bcmpcie_get_total_wake(struct dhd_bus * bus)1008 int bcmpcie_get_total_wake(struct dhd_bus *bus)
1009 {
1010 dhdpcie_info_t *pch = pci_get_drvdata(bus->dev);
1011
1012 return pch->total_wake_count;
1013 }
1014
bcmpcie_set_get_wake(struct dhd_bus * bus,int flag)1015 int bcmpcie_set_get_wake(struct dhd_bus *bus, int flag)
1016 {
1017 dhdpcie_info_t *pch = pci_get_drvdata(bus->dev);
1018 unsigned long flags;
1019 int ret;
1020
1021 spin_lock_irqsave(&pch->pcie_lock, flags);
1022
1023 ret = pch->pkt_wake;
1024 pch->total_wake_count += flag;
1025 pch->pkt_wake = flag;
1026
1027 spin_unlock_irqrestore(&pch->pcie_lock, flags);
1028 return ret;
1029 }
1030 #endif /* DHD_WAKE_STATUS */
1031
dhdpcie_resume_dev(struct pci_dev * dev)1032 static int dhdpcie_resume_dev(struct pci_dev *dev)
1033 {
1034 int err = 0;
1035 dhdpcie_info_t *pch = pci_get_drvdata(dev);
1036 #if defined(OEM_ANDROID) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
1037 pci_load_and_free_saved_state(dev, &pch->state);
1038 #endif /* OEM_ANDROID && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
1039 DHD_ERROR(("%s: Enter\n", __FUNCTION__));
1040 #ifdef OEM_ANDROID
1041 dev->state_saved = TRUE;
1042 #endif /* OEM_ANDROID */
1043 pci_restore_state(dev);
1044 #ifdef FORCE_TPOWERON
1045 if (dhdpcie_chip_req_forced_tpoweron(pch->bus)) {
1046 dhd_bus_set_tpoweron(pch->bus, tpoweron_scale);
1047 }
1048 #endif /* FORCE_TPOWERON */
1049 err = pci_enable_device(dev);
1050 if (err) {
1051 printf("%s:pci_enable_device error %d \n", __FUNCTION__, err);
1052 goto out;
1053 }
1054 pci_set_master(dev);
1055 err = pci_set_power_state(dev, PCI_D0);
1056 if (err) {
1057 printf("%s:pci_set_power_state error %d \n", __FUNCTION__, err);
1058 goto out;
1059 }
1060 BCM_REFERENCE(pch);
1061 dhdpcie_suspend_dump_cfgregs(pch->bus, "AFTER_EP_RESUME");
1062 out:
1063 return err;
1064 }
1065
dhdpcie_resume_host_dev(dhd_bus_t * bus)1066 static int dhdpcie_resume_host_dev(dhd_bus_t *bus)
1067 {
1068 int bcmerror = 0;
1069 #ifdef USE_EXYNOS_PCIE_RC_PMPATCH
1070 bcmerror = exynos_pcie_pm_resume(SAMSUNG_PCIE_CH_NUM);
1071 #endif /* USE_EXYNOS_PCIE_RC_PMPATCH */
1072 #ifdef CONFIG_ARCH_MSM
1073 bcmerror = dhdpcie_start_host_pcieclock(bus);
1074 #endif /* CONFIG_ARCH_MSM */
1075 #ifdef CONFIG_ARCH_TEGRA
1076 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 18, 0))
1077 bcmerror = tegra_pcie_pm_resume();
1078 #endif // endif
1079 #endif /* CONFIG_ARCH_TEGRA */
1080 if (bcmerror < 0) {
1081 DHD_ERROR(("%s: PCIe RC resume failed!!! (%d)\n",
1082 __FUNCTION__, bcmerror));
1083 bus->is_linkdown = 1;
1084 #ifdef SUPPORT_LINKDOWN_RECOVERY
1085 #ifdef CONFIG_ARCH_MSM
1086 bus->no_cfg_restore = 1;
1087 #endif /* CONFIG_ARCH_MSM */
1088 #endif /* SUPPORT_LINKDOWN_RECOVERY */
1089 }
1090
1091 return bcmerror;
1092 }
1093
dhdpcie_suspend_host_dev(dhd_bus_t * bus)1094 static int dhdpcie_suspend_host_dev(dhd_bus_t *bus)
1095 {
1096 int bcmerror = 0;
1097 #ifdef USE_EXYNOS_PCIE_RC_PMPATCH
1098 if (bus->rc_dev) {
1099 pci_save_state(bus->rc_dev);
1100 } else {
1101 DHD_ERROR(("%s: RC %x:%x handle is NULL\n",
1102 __FUNCTION__, PCIE_RC_VENDOR_ID, PCIE_RC_DEVICE_ID));
1103 }
1104 exynos_pcie_pm_suspend(SAMSUNG_PCIE_CH_NUM);
1105 #endif /* USE_EXYNOS_PCIE_RC_PMPATCH */
1106 #ifdef CONFIG_ARCH_MSM
1107 bcmerror = dhdpcie_stop_host_pcieclock(bus);
1108 #endif /* CONFIG_ARCH_MSM */
1109 #ifdef CONFIG_ARCH_TEGRA
1110 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 18, 0))
1111 bcmerror = tegra_pcie_pm_suspend();
1112 #endif // endif
1113 #endif /* CONFIG_ARCH_TEGRA */
1114 return bcmerror;
1115 }
1116
1117 /**
1118 * dhdpcie_os_setbar1win
1119 *
1120 * Interface function for setting bar1 window in order to allow
1121 * os layer to be aware of current window positon.
1122 *
1123 * @bus: dhd bus context
1124 * @addr: new backplane windows address for BAR1
1125 */
1126 void
dhdpcie_os_setbar1win(dhd_bus_t * bus,uint32 addr)1127 dhdpcie_os_setbar1win(dhd_bus_t *bus, uint32 addr)
1128 {
1129 dhdpcie_info_t *pch = pci_get_drvdata(bus->dev);
1130
1131 osl_pci_write_config(bus->osh, PCI_BAR1_WIN, 4, addr);
1132 pch->curr_bar1_win = addr;
1133 }
1134
1135 /**
1136 * dhdpcie_os_chkbpoffset
1137 *
1138 * Check the provided address is within the current BAR1 window,
1139 * if not, shift the window
1140 *
1141 * @bus: dhd bus context
1142 * @offset: back plane address that the caller wants to access
1143 *
1144 * Return: new offset for access
1145 */
1146 static ulong
dhdpcie_os_chkbpoffset(dhdpcie_info_t * pch,ulong offset)1147 dhdpcie_os_chkbpoffset(dhdpcie_info_t *pch, ulong offset)
1148 {
1149 /* Determine BAR1 backplane window using window size
1150 * Window address mask should be ~(size - 1)
1151 */
1152 uint32 bpwin = (uint32)(offset & ~(pch->bar1_size - 1));
1153
1154 if (bpwin != pch->curr_bar1_win) {
1155 /* Move BAR1 window */
1156 dhdpcie_os_setbar1win(pch->bus, bpwin);
1157 }
1158
1159 return offset - bpwin;
1160 }
1161
1162 /**
1163 * dhdpcie os layer tcm read/write interface
1164 */
1165 void
dhdpcie_os_wtcm8(dhd_bus_t * bus,ulong offset,uint8 data)1166 dhdpcie_os_wtcm8(dhd_bus_t *bus, ulong offset, uint8 data)
1167 {
1168 dhdpcie_info_t *pch = pci_get_drvdata(bus->dev);
1169
1170 offset = dhdpcie_os_chkbpoffset(pch, offset);
1171 W_REG(bus->dhd->osh, (volatile uint8 *)(bus->tcm + offset), data);
1172 }
1173
1174 uint8
dhdpcie_os_rtcm8(dhd_bus_t * bus,ulong offset)1175 dhdpcie_os_rtcm8(dhd_bus_t *bus, ulong offset)
1176 {
1177 volatile uint8 data;
1178 dhdpcie_info_t *pch = pci_get_drvdata(bus->dev);
1179
1180 offset = dhdpcie_os_chkbpoffset(pch, offset);
1181 data = R_REG(bus->dhd->osh, (volatile uint8 *)(bus->tcm + offset));
1182 return data;
1183 }
1184
1185 void
dhdpcie_os_wtcm16(dhd_bus_t * bus,ulong offset,uint16 data)1186 dhdpcie_os_wtcm16(dhd_bus_t *bus, ulong offset, uint16 data)
1187 {
1188 dhdpcie_info_t *pch = pci_get_drvdata(bus->dev);
1189
1190 offset = dhdpcie_os_chkbpoffset(pch, offset);
1191 W_REG(bus->dhd->osh, (volatile uint16 *)(bus->tcm + offset), data);
1192 }
1193
1194 uint16
dhdpcie_os_rtcm16(dhd_bus_t * bus,ulong offset)1195 dhdpcie_os_rtcm16(dhd_bus_t *bus, ulong offset)
1196 {
1197 volatile uint16 data;
1198 dhdpcie_info_t *pch = pci_get_drvdata(bus->dev);
1199
1200 offset = dhdpcie_os_chkbpoffset(pch, offset);
1201 data = R_REG(bus->dhd->osh, (volatile uint16 *)(bus->tcm + offset));
1202 return data;
1203 }
1204
1205 void
dhdpcie_os_wtcm32(dhd_bus_t * bus,ulong offset,uint32 data)1206 dhdpcie_os_wtcm32(dhd_bus_t *bus, ulong offset, uint32 data)
1207 {
1208 dhdpcie_info_t *pch = pci_get_drvdata(bus->dev);
1209
1210 offset = dhdpcie_os_chkbpoffset(pch, offset);
1211 W_REG(bus->dhd->osh, (volatile uint32 *)(bus->tcm + offset), data);
1212 }
1213
1214 uint32
dhdpcie_os_rtcm32(dhd_bus_t * bus,ulong offset)1215 dhdpcie_os_rtcm32(dhd_bus_t *bus, ulong offset)
1216 {
1217 volatile uint32 data;
1218 dhdpcie_info_t *pch = pci_get_drvdata(bus->dev);
1219
1220 offset = dhdpcie_os_chkbpoffset(pch, offset);
1221 data = R_REG(bus->dhd->osh, (volatile uint32 *)(bus->tcm + offset));
1222 return data;
1223 }
1224
1225 #ifdef DHD_SUPPORT_64BIT
1226 void
dhdpcie_os_wtcm64(dhd_bus_t * bus,ulong offset,uint64 data)1227 dhdpcie_os_wtcm64(dhd_bus_t *bus, ulong offset, uint64 data)
1228 {
1229 dhdpcie_info_t *pch = pci_get_drvdata(bus->dev);
1230
1231 offset = dhdpcie_os_chkbpoffset(pch, offset);
1232 W_REG(bus->dhd->osh, (volatile uint64 *)(bus->tcm + offset), data);
1233 }
1234
1235 uint64
dhdpcie_os_rtcm64(dhd_bus_t * bus,ulong offset)1236 dhdpcie_os_rtcm64(dhd_bus_t *bus, ulong offset)
1237 {
1238 volatile uint64 data;
1239 dhdpcie_info_t *pch = pci_get_drvdata(bus->dev);
1240
1241 offset = dhdpcie_os_chkbpoffset(pch, offset);
1242 data = R_REG(bus->dhd->osh, (volatile uint64 *)(bus->tcm + offset));
1243 return data;
1244 }
1245 #endif /* DHD_SUPPORT_64BIT */
1246
1247 uint32
dhdpcie_rc_config_read(dhd_bus_t * bus,uint offset)1248 dhdpcie_rc_config_read(dhd_bus_t *bus, uint offset)
1249 {
1250 uint val = -1; /* Initialise to 0xfffffff */
1251 if (bus->rc_dev) {
1252 pci_read_config_dword(bus->rc_dev, offset, &val);
1253 OSL_DELAY(100);
1254 } else {
1255 DHD_ERROR(("%s: RC %x:%x handle is NULL\n",
1256 __FUNCTION__, PCIE_RC_VENDOR_ID, PCIE_RC_DEVICE_ID));
1257 }
1258 DHD_ERROR(("%s: RC %x:%x offset 0x%x val 0x%x\n",
1259 __FUNCTION__, PCIE_RC_VENDOR_ID, PCIE_RC_DEVICE_ID, offset, val));
1260 return (val);
1261 }
1262
1263 /*
1264 * Reads/ Writes the value of capability register
1265 * from the given CAP_ID section of PCI Root Port
1266 *
1267 * Arguements
1268 * @bus current dhd_bus_t pointer
1269 * @cap Capability or Extended Capability ID to get
1270 * @offset offset of Register to Read
1271 * @is_ext TRUE if @cap is given for Extended Capability
1272 * @is_write is set to TRUE to indicate write
1273 * @val value to write
1274 *
1275 * Return Value
1276 * Returns 0xffffffff on error
1277 * on write success returns BCME_OK (0)
1278 * on Read Success returns the value of register requested
1279 * Note: caller shoud ensure valid capability ID and Ext. Capability ID.
1280 */
1281
1282 uint32
dhdpcie_access_cap(struct pci_dev * pdev,int cap,uint offset,bool is_ext,bool is_write,uint32 writeval)1283 dhdpcie_access_cap(struct pci_dev *pdev, int cap, uint offset, bool is_ext, bool is_write,
1284 uint32 writeval)
1285 {
1286 int cap_ptr = 0;
1287 uint32 ret = -1;
1288 uint32 readval;
1289
1290 if (!(pdev)) {
1291 DHD_ERROR(("%s: pdev is NULL\n", __FUNCTION__));
1292 return ret;
1293 }
1294
1295 /* Find Capability offset */
1296 if (is_ext) {
1297 /* removing max EXT_CAP_ID check as
1298 * linux kernel definition's max value is not upadted yet as per spec
1299 */
1300 cap_ptr = pci_find_ext_capability(pdev, cap);
1301
1302 } else {
1303 /* removing max PCI_CAP_ID_MAX check as
1304 * pervious kernel versions dont have this definition
1305 */
1306 cap_ptr = pci_find_capability(pdev, cap);
1307 }
1308
1309 /* Return if capability with given ID not found */
1310 if (cap_ptr == 0) {
1311 DHD_ERROR(("%s: PCI Cap(0x%02x) not supported.\n",
1312 __FUNCTION__, cap));
1313 return BCME_ERROR;
1314 }
1315
1316 if (is_write) {
1317 pci_write_config_dword(pdev, (cap_ptr + offset), writeval);
1318 ret = BCME_OK;
1319
1320 } else {
1321
1322 pci_read_config_dword(pdev, (cap_ptr + offset), &readval);
1323 ret = readval;
1324 }
1325
1326 return ret;
1327 }
1328
1329 uint32
dhdpcie_rc_access_cap(dhd_bus_t * bus,int cap,uint offset,bool is_ext,bool is_write,uint32 writeval)1330 dhdpcie_rc_access_cap(dhd_bus_t *bus, int cap, uint offset, bool is_ext, bool is_write,
1331 uint32 writeval)
1332 {
1333 if (!(bus->rc_dev)) {
1334 DHD_ERROR(("%s: RC %x:%x handle is NULL\n",
1335 __FUNCTION__, PCIE_RC_VENDOR_ID, PCIE_RC_DEVICE_ID));
1336 return BCME_ERROR;
1337 }
1338
1339 return dhdpcie_access_cap(bus->rc_dev, cap, offset, is_ext, is_write, writeval);
1340 }
1341
1342 uint32
dhdpcie_ep_access_cap(dhd_bus_t * bus,int cap,uint offset,bool is_ext,bool is_write,uint32 writeval)1343 dhdpcie_ep_access_cap(dhd_bus_t *bus, int cap, uint offset, bool is_ext, bool is_write,
1344 uint32 writeval)
1345 {
1346 if (!(bus->dev)) {
1347 DHD_ERROR(("%s: EP handle is NULL\n", __FUNCTION__));
1348 return BCME_ERROR;
1349 }
1350
1351 return dhdpcie_access_cap(bus->dev, cap, offset, is_ext, is_write, writeval);
1352 }
1353
1354 /* API wrapper to read Root Port link capability
1355 * Returns 2 = GEN2 1 = GEN1 BCME_ERR on linkcap not found
1356 */
1357
dhd_debug_get_rc_linkcap(dhd_bus_t * bus)1358 uint32 dhd_debug_get_rc_linkcap(dhd_bus_t *bus)
1359 {
1360 uint32 linkcap = -1;
1361 linkcap = dhdpcie_rc_access_cap(bus, PCIE_CAP_ID_EXP,
1362 PCIE_CAP_LINKCAP_OFFSET, FALSE, FALSE, 0);
1363 linkcap &= PCIE_CAP_LINKCAP_LNKSPEED_MASK;
1364 return linkcap;
1365 }
1366
dhdpcie_config_save_restore_coherent(dhd_bus_t * bus,bool state)1367 static void dhdpcie_config_save_restore_coherent(dhd_bus_t *bus, bool state)
1368 {
1369 if (bus->coreid == ARMCA7_CORE_ID) {
1370 if (state) {
1371 /* Sleep */
1372 bus->coherent_state = dhdpcie_bus_cfg_read_dword(bus,
1373 PCIE_CFG_SUBSYSTEM_CONTROL, 4) & PCIE_BARCOHERENTACCEN_MASK;
1374 } else {
1375 uint32 val = (dhdpcie_bus_cfg_read_dword(bus, PCIE_CFG_SUBSYSTEM_CONTROL,
1376 4) & ~PCIE_BARCOHERENTACCEN_MASK) | bus->coherent_state;
1377 dhdpcie_bus_cfg_write_dword(bus, PCIE_CFG_SUBSYSTEM_CONTROL, 4, val);
1378 }
1379 }
1380 }
1381
dhdpcie_pci_suspend_resume(dhd_bus_t * bus,bool state)1382 int dhdpcie_pci_suspend_resume(dhd_bus_t *bus, bool state)
1383 {
1384 int rc;
1385
1386 struct pci_dev *dev = bus->dev;
1387
1388 if (state) {
1389 dhdpcie_config_save_restore_coherent(bus, state);
1390 #if !defined(BCMPCIE_OOB_HOST_WAKE)
1391 dhdpcie_pme_active(bus->osh, state);
1392 #endif // endif
1393 rc = dhdpcie_suspend_dev(dev);
1394 if (!rc) {
1395 dhdpcie_suspend_host_dev(bus);
1396 }
1397 } else {
1398 rc = dhdpcie_resume_host_dev(bus);
1399 if (!rc) {
1400 rc = dhdpcie_resume_dev(dev);
1401 if (PCIECTO_ENAB(bus)) {
1402 /* reinit CTO configuration
1403 * because cfg space got reset at D3 (PERST)
1404 */
1405 dhdpcie_cto_cfg_init(bus, TRUE);
1406 }
1407 if (PCIE_ENUM_RESET_WAR_ENAB(bus->sih->buscorerev)) {
1408 dhdpcie_ssreset_dis_enum_rst(bus);
1409 }
1410 #if !defined(BCMPCIE_OOB_HOST_WAKE)
1411 dhdpcie_pme_active(bus->osh, state);
1412 #endif // endif
1413 }
1414 dhdpcie_config_save_restore_coherent(bus, state);
1415 #if defined(OEM_ANDROID)
1416 #if defined(DHD_HANG_SEND_UP_TEST)
1417 if (bus->is_linkdown ||
1418 bus->dhd->req_hang_type == HANG_REASON_PCIE_RC_LINK_UP_FAIL) {
1419 #else /* DHD_HANG_SEND_UP_TEST */
1420 if (bus->is_linkdown) {
1421 #endif /* DHD_HANG_SEND_UP_TEST */
1422 bus->dhd->hang_reason = HANG_REASON_PCIE_RC_LINK_UP_FAIL;
1423 dhd_os_send_hang_message(bus->dhd);
1424 }
1425 #endif /* OEM_ANDROID */
1426 }
1427 return rc;
1428 }
1429
1430 static int dhdpcie_device_scan(struct device *dev, void *data)
1431 {
1432 struct pci_dev *pcidev;
1433 int *cnt = data;
1434
1435 #if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
1436 #pragma GCC diagnostic push
1437 #pragma GCC diagnostic ignored "-Wcast-qual"
1438 #endif // endif
1439 pcidev = container_of(dev, struct pci_dev, dev);
1440 #if defined(STRICT_GCC_WARNINGS) && defined(__GNUC__)
1441 #pragma GCC diagnostic pop
1442 #endif // endif
1443 if (pcidev->vendor != VENDOR_BROADCOM && pcidev->vendor != VENDOR_CYPRESS)
1444 return 0;
1445
1446 if (pcidev->vendor == VENDOR_CYPRESS) {
1447 DHD_INFO(("Found Cypress PCI device 0x%04x\n", pcidev->device));
1448 } else {
1449 DHD_INFO(("Found Broadcom PCI device 0x%04x\n", pcidev->device));
1450 }
1451 *cnt += 1;
1452 if (pcidev->driver && strcmp(pcidev->driver->name, dhdpcie_driver.name))
1453 DHD_ERROR(("Broadcom PCI Device 0x%04x has allocated with driver %s\n",
1454 pcidev->device, pcidev->driver->name));
1455
1456 return 0;
1457 }
1458
1459 int
1460 dhdpcie_bus_register(void)
1461 {
1462 int error = 0;
1463
1464 if (!(error = pci_register_driver(&dhdpcie_driver))) {
1465 bus_for_each_dev(dhdpcie_driver.driver.bus, NULL, &error, dhdpcie_device_scan);
1466 if (!error) {
1467 DHD_ERROR(("No Broadcom PCI device enumerated!\n"));
1468 } else if (!dhdpcie_init_succeeded) {
1469 DHD_ERROR(("%s: dhdpcie initialize failed.\n", __FUNCTION__));
1470 } else {
1471 return 0;
1472 }
1473
1474 pci_unregister_driver(&dhdpcie_driver);
1475 error = BCME_ERROR;
1476 }
1477
1478 return error;
1479 }
1480
1481 void
1482 dhdpcie_bus_unregister(void)
1483 {
1484 pci_unregister_driver(&dhdpcie_driver);
1485 }
1486
1487 int __devinit
1488 dhdpcie_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1489 {
1490 #ifndef MULTI_CHIP_SUPPORT
1491 /* Don't enumerate more than one device */
1492 if (dhdpcie_init_succeeded) {
1493 DHD_TRACE(("%s: PCIe Enumeration is already done.\n",
1494 __func__));
1495 return -ENODEV;
1496 }
1497 #endif /* MULTI_CHIP_SUPPORT */
1498
1499 if (dhdpcie_chipmatch (pdev->vendor, pdev->device)) {
1500 DHD_ERROR(("%s: chipmatch failed!!\n", __FUNCTION__));
1501 return -ENODEV;
1502 }
1503
1504 printf("PCI_PROBE: bus %X, slot %X,vendor %X, device %X"
1505 "(good PCI location)\n", pdev->bus->number,
1506 PCI_SLOT(pdev->devfn), pdev->vendor, pdev->device);
1507
1508 if (dhdpcie_init_succeeded == TRUE) {
1509 DHD_ERROR(("%s(): === Driver Already attached to a BRCM device === \r\n",
1510 __FUNCTION__));
1511 return -ENODEV;
1512 }
1513
1514 if (dhdpcie_init (pdev)) {
1515 DHD_ERROR(("%s: PCIe Enumeration failed\n", __FUNCTION__));
1516 return -ENODEV;
1517 }
1518
1519 #ifdef DHD_PCIE_NATIVE_RUNTIMEPM
1520 /*
1521 Since MSM PCIe RC dev usage conunt already incremented +2 even
1522 before dhdpcie_pci_probe() called, then we inevitably to call
1523 pm_runtime_put_noidle() two times to make the count start with zero.
1524 */
1525
1526 pm_runtime_put_noidle(&pdev->dev);
1527 pm_runtime_put_noidle(&pdev->dev);
1528 pm_runtime_set_suspended(&pdev->dev);
1529 #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
1530
1531 #ifdef BCMPCIE_DISABLE_ASYNC_SUSPEND
1532 /* disable async suspend */
1533 device_disable_async_suspend(&pdev->dev);
1534 #endif /* BCMPCIE_DISABLE_ASYNC_SUSPEND */
1535
1536 DHD_TRACE(("%s: PCIe Enumeration done!!\n", __FUNCTION__));
1537 return 0;
1538 }
1539
1540 int
1541 dhdpcie_detach(dhdpcie_info_t *pch)
1542 {
1543 if (pch) {
1544 #if defined(OEM_ANDROID) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
1545 if (pch->default_state) {
1546 pci_load_and_free_saved_state(pch->dev, &pch->default_state);
1547 }
1548 #endif /* OEM_ANDROID && LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
1549 MFREE(pch->osh, pch, sizeof(dhdpcie_info_t));
1550 }
1551 return 0;
1552 }
1553
1554 void __devexit
1555 dhdpcie_pci_remove(struct pci_dev *pdev)
1556 {
1557 osl_t *osh = NULL;
1558 dhdpcie_info_t *pch = NULL;
1559 dhd_bus_t *bus = NULL;
1560
1561 DHD_TRACE(("%s Enter\n", __FUNCTION__));
1562 pch = pci_get_drvdata(pdev);
1563 bus = pch->bus;
1564 osh = pch->osh;
1565
1566 #ifdef DHD_PCIE_NATIVE_RUNTIMEPM
1567 pm_runtime_get_noresume(&pdev->dev);
1568 pm_runtime_get_noresume(&pdev->dev);
1569 #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
1570
1571 if (bus) {
1572 #ifdef SUPPORT_LINKDOWN_RECOVERY
1573 #ifdef CONFIG_ARCH_MSM
1574 msm_pcie_deregister_event(&bus->pcie_event);
1575 #endif /* CONFIG_ARCH_MSM */
1576 #ifdef EXYNOS_PCIE_LINKDOWN_RECOVERY
1577 #if defined(CONFIG_SOC_EXYNOS8890) || defined(CONFIG_SOC_EXYNOS8895) || \
1578 defined(CONFIG_SOC_EXYNOS9810) || defined(CONFIG_SOC_EXYNOS9820)
1579 exynos_pcie_deregister_event(&bus->pcie_event);
1580 #endif /* CONFIG_SOC_EXYNOS8890 || CONFIG_SOC_EXYNOS8895 ||
1581 * CONFIG_SOC_EXYNOS9810 || CONFIG_SOC_EXYNOS9820
1582 */
1583 #endif /* EXYNOS_PCIE_LINKDOWN_RECOVERY */
1584 #endif /* SUPPORT_LINKDOWN_RECOVERY */
1585
1586 bus->rc_dev = NULL;
1587
1588 dhdpcie_bus_release(bus);
1589 }
1590
1591 if (pci_is_enabled(pdev))
1592 pci_disable_device(pdev);
1593 #if defined(CONFIG_ARCH_MSM)
1594 msm_pcie_pm_control(MSM_PCIE_SUSPEND, pdev->bus->number, pdev, NULL, 0);
1595 #endif // endif
1596 #ifdef BCMPCIE_OOB_HOST_WAKE
1597 /* pcie os info detach */
1598 MFREE(osh, pch->os_cxt, sizeof(dhdpcie_os_info_t));
1599 #endif /* BCMPCIE_OOB_HOST_WAKE */
1600 #ifdef USE_SMMU_ARCH_MSM
1601 /* smmu info detach */
1602 dhdpcie_smmu_remove(pdev, pch->smmu_cxt);
1603 MFREE(osh, pch->smmu_cxt, sizeof(dhdpcie_smmu_info_t));
1604 #endif /* USE_SMMU_ARCH_MSM */
1605 /* pcie info detach */
1606 dhdpcie_detach(pch);
1607 /* osl detach */
1608 osl_detach(osh);
1609
1610 #if defined(BCMPCIE_OOB_HOST_WAKE) && defined(CUSTOMER_HW2) && \
1611 defined(CONFIG_ARCH_APQ8084)
1612 brcm_pcie_wake.wake_irq = NULL;
1613 brcm_pcie_wake.data = NULL;
1614 #endif /* BCMPCIE_OOB_HOST_WAKE && CUSTOMR_HW2 && CONFIG_ARCH_APQ8084 */
1615
1616 dhdpcie_init_succeeded = FALSE;
1617
1618 DHD_TRACE(("%s Exit\n", __FUNCTION__));
1619
1620 return;
1621 }
1622
1623 /* Enable Linux Msi */
1624 int
1625 dhdpcie_enable_msi(struct pci_dev *pdev, unsigned int min_vecs, unsigned int max_vecs)
1626 {
1627 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0))
1628 return pci_alloc_irq_vectors(pdev, min_vecs, max_vecs, PCI_IRQ_MSI);
1629 #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0))
1630 return pci_enable_msi_range(pdev, min_vecs, max_vecs);
1631 #else
1632 return pci_enable_msi_block(pdev, max_vecs);
1633 #endif // endif
1634 }
1635
1636 /* Disable Linux Msi */
1637 void
1638 dhdpcie_disable_msi(struct pci_dev *pdev)
1639 {
1640 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0))
1641 pci_free_irq_vectors(pdev);
1642 #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0))
1643 pci_disable_msi(pdev);
1644 #else
1645 pci_disable_msi(pdev);
1646 #endif // endif
1647 return;
1648 }
1649
1650 /* Request Linux irq */
1651 int
1652 dhdpcie_request_irq(dhdpcie_info_t *dhdpcie_info)
1653 {
1654 dhd_bus_t *bus = dhdpcie_info->bus;
1655 struct pci_dev *pdev = dhdpcie_info->bus->dev;
1656 int host_irq_disabled;
1657
1658 if (!bus->irq_registered) {
1659 snprintf(dhdpcie_info->pciname, sizeof(dhdpcie_info->pciname),
1660 "dhdpcie:%s", pci_name(pdev));
1661
1662 if (bus->d2h_intr_method == PCIE_MSI) {
1663 if (dhdpcie_enable_msi(pdev, 1, 1) < 0) {
1664 DHD_ERROR(("%s: dhdpcie_enable_msi() failed\n", __FUNCTION__));
1665 dhdpcie_disable_msi(pdev);
1666 bus->d2h_intr_method = PCIE_INTX;
1667 }
1668 }
1669
1670 if (request_irq(pdev->irq, dhdpcie_isr, IRQF_SHARED,
1671 dhdpcie_info->pciname, bus) < 0) {
1672 DHD_ERROR(("%s: request_irq() failed\n", __FUNCTION__));
1673 if (bus->d2h_intr_method == PCIE_MSI) {
1674 dhdpcie_disable_msi(pdev);
1675 }
1676 return -1;
1677 }
1678 else {
1679 bus->irq_registered = TRUE;
1680 }
1681 } else {
1682 DHD_ERROR(("%s: PCI IRQ is already registered\n", __FUNCTION__));
1683 }
1684
1685 host_irq_disabled = dhdpcie_irq_disabled(bus);
1686 if (host_irq_disabled) {
1687 DHD_ERROR(("%s: PCIe IRQ was disabled(%d), so, enabled it again\n",
1688 __FUNCTION__, host_irq_disabled));
1689 dhdpcie_enable_irq(bus);
1690 }
1691
1692 DHD_TRACE(("%s %s\n", __FUNCTION__, dhdpcie_info->pciname));
1693
1694 return 0; /* SUCCESS */
1695 }
1696
1697 /**
1698 * dhdpcie_get_pcieirq - return pcie irq number to linux-dhd
1699 */
1700 int
1701 dhdpcie_get_pcieirq(struct dhd_bus *bus, unsigned int *irq)
1702 {
1703 struct pci_dev *pdev = bus->dev;
1704
1705 if (!pdev) {
1706 DHD_ERROR(("%s : bus->dev is NULL\n", __FUNCTION__));
1707 return -ENODEV;
1708 }
1709
1710 *irq = pdev->irq;
1711
1712 return 0; /* SUCCESS */
1713 }
1714
1715 #ifdef CONFIG_PHYS_ADDR_T_64BIT
1716 #define PRINTF_RESOURCE "0x%016llx"
1717 #else
1718 #define PRINTF_RESOURCE "0x%08x"
1719 #endif // endif
1720
1721 #ifdef EXYNOS_PCIE_MODULE_PATCH
1722 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
1723 extern struct pci_saved_state *bcm_pcie_default_state;
1724 #endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
1725 #endif /* EXYNOS_MODULE_PATCH */
1726
1727 /*
1728
1729 Name: osl_pci_get_resource
1730
1731 Parametrs:
1732
1733 1: struct pci_dev *pdev -- pci device structure
1734 2: pci_res -- structure containing pci configuration space values
1735
1736 Return value:
1737
1738 int - Status (TRUE or FALSE)
1739
1740 Description:
1741 Access PCI configuration space, retrieve PCI allocated resources , updates in resource structure.
1742
1743 */
1744 int dhdpcie_get_resource(dhdpcie_info_t *dhdpcie_info)
1745 {
1746 phys_addr_t bar0_addr, bar1_addr;
1747 ulong bar1_size;
1748 struct pci_dev *pdev = dhdpcie_info->dev;
1749 #if defined(CONFIG_ARCH_MSM) && !defined(ENABLE_INSMOD_NO_FW_LOAD)
1750 int ret;
1751 /* enable PCIe link */
1752 ret = msm_pcie_pm_control(MSM_PCIE_RESUME, pdev->bus->number,
1753 pdev, NULL, MSM_PCIE_CONFIG_NO_CFG_RESTORE);
1754 if (ret) {
1755 DHD_ERROR(("%s: MSM_PCIE_RESUME failed : %d\n", __FUNCTION__, ret));
1756 goto err;
1757 }
1758 DHD_ERROR(("PCIe:%s:enabled link\n", __FUNCTION__));
1759 /* recover the config space of both RC and Endpoint */
1760 msm_pcie_recover_config(pdev);
1761 #endif /* CONFIG_ARCH_MSM && !ENABLE_INSMOD_NO_FW_LOAD */
1762 #ifdef EXYNOS_PCIE_MODULE_PATCH
1763 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
1764 if (bcm_pcie_default_state) {
1765 pci_load_saved_state(pdev, bcm_pcie_default_state);
1766 pci_restore_state(pdev);
1767 }
1768 #endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
1769 #endif /* EXYNOS_MODULE_PATCH */
1770 do {
1771 if (pci_enable_device(pdev)) {
1772 printf("%s: Cannot enable PCI device\n", __FUNCTION__);
1773 break;
1774 }
1775 pci_set_master(pdev);
1776 bar0_addr = pci_resource_start(pdev, 0); /* Bar-0 mapped address */
1777 bar1_addr = pci_resource_start(pdev, 2); /* Bar-1 mapped address */
1778
1779 /* read Bar-1 mapped memory range */
1780 bar1_size = pci_resource_len(pdev, 2);
1781
1782 if ((bar1_size == 0) || (bar1_addr == 0)) {
1783 printf("%s: BAR1 Not enabled for this device size(%ld),"
1784 " addr(0x"PRINTF_RESOURCE")\n",
1785 __FUNCTION__, bar1_size, bar1_addr);
1786 goto err;
1787 }
1788
1789 dhdpcie_info->regs = (volatile char *) REG_MAP(bar0_addr, DONGLE_REG_MAP_SIZE);
1790 dhdpcie_info->bar1_size =
1791 (bar1_size > DONGLE_TCM_MAP_SIZE) ? bar1_size : DONGLE_TCM_MAP_SIZE;
1792 dhdpcie_info->tcm = (volatile char *) REG_MAP(bar1_addr, dhdpcie_info->bar1_size);
1793
1794 if (!dhdpcie_info->regs || !dhdpcie_info->tcm) {
1795 DHD_ERROR(("%s:ioremap() failed\n", __FUNCTION__));
1796 break;
1797 }
1798 #ifdef EXYNOS_PCIE_MODULE_PATCH
1799 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
1800 if (bcm_pcie_default_state == NULL) {
1801 pci_save_state(pdev);
1802 bcm_pcie_default_state = pci_store_saved_state(pdev);
1803 }
1804 #endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
1805 #endif /* EXYNOS_MODULE_PATCH */
1806
1807 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
1808 /* Backup PCIe configuration so as to use Wi-Fi on/off process
1809 * in case of built in driver
1810 */
1811 pci_save_state(pdev);
1812 dhdpcie_info->default_state = pci_store_saved_state(pdev);
1813
1814 if (dhdpcie_info->default_state == NULL) {
1815 DHD_ERROR(("%s pci_store_saved_state returns NULL\n",
1816 __FUNCTION__));
1817 REG_UNMAP(dhdpcie_info->regs);
1818 REG_UNMAP(dhdpcie_info->tcm);
1819 pci_disable_device(pdev);
1820 break;
1821 }
1822 #endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
1823
1824 DHD_TRACE(("%s:Phys addr : reg space = %p base addr 0x"PRINTF_RESOURCE" \n",
1825 __FUNCTION__, dhdpcie_info->regs, bar0_addr));
1826 DHD_TRACE(("%s:Phys addr : tcm_space = %p base addr 0x"PRINTF_RESOURCE" \n",
1827 __FUNCTION__, dhdpcie_info->tcm, bar1_addr));
1828
1829 return 0; /* SUCCESS */
1830 } while (0);
1831 err:
1832 return -1; /* FAILURE */
1833 }
1834
1835 int dhdpcie_scan_resource(dhdpcie_info_t *dhdpcie_info)
1836 {
1837
1838 DHD_TRACE(("%s: ENTER\n", __FUNCTION__));
1839
1840 do {
1841 /* define it here only!! */
1842 if (dhdpcie_get_resource (dhdpcie_info)) {
1843 DHD_ERROR(("%s: Failed to get PCI resources\n", __FUNCTION__));
1844 break;
1845 }
1846 DHD_TRACE(("%s:Exit - SUCCESS \n",
1847 __FUNCTION__));
1848
1849 return 0; /* SUCCESS */
1850
1851 } while (0);
1852
1853 DHD_TRACE(("%s:Exit - FAILURE \n", __FUNCTION__));
1854
1855 return -1; /* FAILURE */
1856
1857 }
1858
1859 void dhdpcie_dump_resource(dhd_bus_t *bus)
1860 {
1861 dhdpcie_info_t *pch;
1862
1863 if (bus == NULL) {
1864 DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__));
1865 return;
1866 }
1867
1868 if (bus->dev == NULL) {
1869 DHD_ERROR(("%s: bus->dev is NULL\n", __FUNCTION__));
1870 return;
1871 }
1872
1873 pch = pci_get_drvdata(bus->dev);
1874 if (pch == NULL) {
1875 DHD_ERROR(("%s: pch is NULL\n", __FUNCTION__));
1876 return;
1877 }
1878
1879 /* BAR0 */
1880 DHD_ERROR(("%s: BAR0(VA): 0x%pK, BAR0(PA): "PRINTF_RESOURCE", SIZE: %d\n",
1881 __FUNCTION__, pch->regs, pci_resource_start(bus->dev, 0),
1882 DONGLE_REG_MAP_SIZE));
1883
1884 /* BAR1 */
1885 DHD_ERROR(("%s: BAR1(VA): 0x%pK, BAR1(PA): "PRINTF_RESOURCE", SIZE: %d\n",
1886 __FUNCTION__, pch->tcm, pci_resource_start(bus->dev, 2),
1887 pch->bar1_size));
1888 }
1889
1890 #ifdef SUPPORT_LINKDOWN_RECOVERY
1891 #if defined(CONFIG_ARCH_MSM) || (defined(EXYNOS_PCIE_LINKDOWN_RECOVERY) && \
1892 (defined(CONFIG_SOC_EXYNOS8890) || defined(CONFIG_SOC_EXYNOS8895) || \
1893 defined(CONFIG_SOC_EXYNOS9810) || defined(CONFIG_SOC_EXYNOS9820)))
1894 void dhdpcie_linkdown_cb(struct_pcie_notify *noti)
1895 {
1896 struct pci_dev *pdev = (struct pci_dev *)noti->user;
1897 dhdpcie_info_t *pch = NULL;
1898
1899 if (pdev) {
1900 pch = pci_get_drvdata(pdev);
1901 if (pch) {
1902 dhd_bus_t *bus = pch->bus;
1903 if (bus) {
1904 dhd_pub_t *dhd = bus->dhd;
1905 if (dhd) {
1906 DHD_ERROR(("%s: Event HANG send up "
1907 "due to PCIe linkdown\n",
1908 __FUNCTION__));
1909 #ifdef CONFIG_ARCH_MSM
1910 bus->no_cfg_restore = 1;
1911 #endif /* CONFIG_ARCH_MSM */
1912 bus->is_linkdown = 1;
1913 DHD_OS_WAKE_LOCK(dhd);
1914 dhd->hang_reason = HANG_REASON_PCIE_LINK_DOWN_RC_DETECT;
1915 dhd_os_send_hang_message(dhd);
1916 }
1917 }
1918 }
1919 }
1920
1921 }
1922 #endif /* CONFIG_ARCH_MSM || (EXYNOS_PCIE_LINKDOWN_RECOVERY &&
1923 * (CONFIG_SOC_EXYNOS8890 || CONFIG_SOC_EXYNOS8895 || \
1924 * CONFIG_SOC_EXYNOS9810 || CONFIG_SOC_EXYNOS9820))
1925 */
1926 #endif /* SUPPORT_LINKDOWN_RECOVERY */
1927
1928 int dhdpcie_init(struct pci_dev *pdev)
1929 {
1930
1931 osl_t *osh = NULL;
1932 dhd_bus_t *bus = NULL;
1933 dhdpcie_info_t *dhdpcie_info = NULL;
1934 wifi_adapter_info_t *adapter = NULL;
1935 #ifdef BCMPCIE_OOB_HOST_WAKE
1936 dhdpcie_os_info_t *dhdpcie_osinfo = NULL;
1937 #endif /* BCMPCIE_OOB_HOST_WAKE */
1938 #ifdef USE_SMMU_ARCH_MSM
1939 dhdpcie_smmu_info_t *dhdpcie_smmu_info = NULL;
1940 #endif /* USE_SMMU_ARCH_MSM */
1941 int ret = 0;
1942
1943 do {
1944 /* osl attach */
1945 if (!(osh = osl_attach(pdev, PCI_BUS, FALSE))) {
1946 DHD_ERROR(("%s: osl_attach failed\n", __FUNCTION__));
1947 break;
1948 }
1949
1950 /* initialize static buffer */
1951 adapter = dhd_wifi_platform_get_adapter(PCI_BUS, pdev->bus->number,
1952 PCI_SLOT(pdev->devfn));
1953 if (adapter != NULL)
1954 DHD_ERROR(("%s: found adapter info '%s'\n", __FUNCTION__, adapter->name));
1955 else
1956 DHD_ERROR(("%s: can't find adapter info for this chip\n", __FUNCTION__));
1957 osl_static_mem_init(osh, adapter);
1958
1959 /* Set ACP coherence flag */
1960 if (OSL_ACP_WAR_ENAB() || OSL_ARCH_IS_COHERENT())
1961 osl_flag_set(osh, OSL_ACP_COHERENCE);
1962
1963 /* allocate linux spcific pcie structure here */
1964 if (!(dhdpcie_info = MALLOC(osh, sizeof(dhdpcie_info_t)))) {
1965 DHD_ERROR(("%s: MALLOC of dhd_bus_t failed\n", __FUNCTION__));
1966 break;
1967 }
1968 bzero(dhdpcie_info, sizeof(dhdpcie_info_t));
1969 dhdpcie_info->osh = osh;
1970 dhdpcie_info->dev = pdev;
1971
1972 #ifdef BCMPCIE_OOB_HOST_WAKE
1973 /* allocate OS speicific structure */
1974 dhdpcie_osinfo = MALLOC(osh, sizeof(dhdpcie_os_info_t));
1975 if (dhdpcie_osinfo == NULL) {
1976 DHD_ERROR(("%s: MALLOC of dhdpcie_os_info_t failed\n",
1977 __FUNCTION__));
1978 break;
1979 }
1980 bzero(dhdpcie_osinfo, sizeof(dhdpcie_os_info_t));
1981 dhdpcie_info->os_cxt = (void *)dhdpcie_osinfo;
1982
1983 /* Initialize host wake IRQ */
1984 spin_lock_init(&dhdpcie_osinfo->oob_irq_spinlock);
1985 /* Get customer specific host wake IRQ parametres: IRQ number as IRQ type */
1986 dhdpcie_osinfo->oob_irq_num = wifi_platform_get_irq_number(adapter,
1987 &dhdpcie_osinfo->oob_irq_flags);
1988 if (dhdpcie_osinfo->oob_irq_num < 0) {
1989 DHD_ERROR(("%s: Host OOB irq is not defined\n", __FUNCTION__));
1990 }
1991 #endif /* BCMPCIE_OOB_HOST_WAKE */
1992
1993 #ifdef USE_SMMU_ARCH_MSM
1994 /* allocate private structure for using SMMU */
1995 dhdpcie_smmu_info = MALLOC(osh, sizeof(dhdpcie_smmu_info_t));
1996 if (dhdpcie_smmu_info == NULL) {
1997 DHD_ERROR(("%s: MALLOC of dhdpcie_smmu_info_t failed\n",
1998 __FUNCTION__));
1999 break;
2000 }
2001 bzero(dhdpcie_smmu_info, sizeof(dhdpcie_smmu_info_t));
2002 dhdpcie_info->smmu_cxt = (void *)dhdpcie_smmu_info;
2003
2004 /* Initialize smmu structure */
2005 if (dhdpcie_smmu_init(pdev, dhdpcie_info->smmu_cxt) < 0) {
2006 DHD_ERROR(("%s: Failed to initialize SMMU\n",
2007 __FUNCTION__));
2008 break;
2009 }
2010 #endif /* USE_SMMU_ARCH_MSM */
2011
2012 #ifdef DHD_WAKE_STATUS
2013 /* Initialize pcie_lock */
2014 spin_lock_init(&dhdpcie_info->pcie_lock);
2015 #endif /* DHD_WAKE_STATUS */
2016
2017 /* Find the PCI resources, verify the */
2018 /* vendor and device ID, map BAR regions and irq, update in structures */
2019 if (dhdpcie_scan_resource(dhdpcie_info)) {
2020 DHD_ERROR(("%s: dhd_Scan_PCI_Res failed\n", __FUNCTION__));
2021
2022 break;
2023 }
2024
2025 /* Bus initialization */
2026 ret = dhdpcie_bus_attach(osh, &bus, dhdpcie_info->regs, dhdpcie_info->tcm, pdev);
2027 if (ret != BCME_OK) {
2028 DHD_ERROR(("%s:dhdpcie_bus_attach() failed\n", __FUNCTION__));
2029 break;
2030 }
2031
2032 dhdpcie_info->bus = bus;
2033 bus->is_linkdown = 0;
2034 bus->no_bus_init = FALSE;
2035 bus->cto_triggered = 0;
2036
2037 bus->rc_dev = NULL;
2038
2039 /* Get RC Device Handle */
2040 if (bus->dev->bus) {
2041 /* self member of structure pci_bus is bridge device as seen by parent */
2042 bus->rc_dev = bus->dev->bus->self;
2043 DHD_ERROR(("%s: rc_dev from dev->bus->self (%x:%x) is %pK\n", __FUNCTION__,
2044 bus->rc_dev->vendor, bus->rc_dev->device, bus->rc_dev));
2045 } else {
2046 DHD_ERROR(("%s: unable to get rc_dev as dev->bus is NULL\n", __FUNCTION__));
2047 }
2048
2049 /* if rc_dev is still NULL, try to get from vendor/device IDs */
2050 if (bus->rc_dev == NULL) {
2051 bus->rc_dev = pci_get_device(PCIE_RC_VENDOR_ID, PCIE_RC_DEVICE_ID, NULL);
2052 DHD_ERROR(("%s: rc_dev from pci_get_device (%x:%x) is %p\n", __FUNCTION__,
2053 PCIE_RC_VENDOR_ID, PCIE_RC_DEVICE_ID, bus->rc_dev));
2054 }
2055
2056 bus->rc_ep_aspm_cap = dhd_bus_is_rc_ep_aspm_capable(bus);
2057 bus->rc_ep_l1ss_cap = dhd_bus_is_rc_ep_l1ss_capable(bus);
2058 DHD_ERROR(("%s: rc_ep_aspm_cap: %d rc_ep_l1ss_cap: %d\n",
2059 __FUNCTION__, bus->rc_ep_aspm_cap, bus->rc_ep_l1ss_cap));
2060 #ifdef DHD_DISABLE_ASPM
2061 dhd_bus_aspm_enable_rc_ep(bus, FALSE);
2062 #endif /* DHD_DISABLE_ASPM */
2063
2064 #ifdef FORCE_TPOWERON
2065 if (dhdpcie_chip_req_forced_tpoweron(bus)) {
2066 dhd_bus_set_tpoweron(bus, tpoweron_scale);
2067 }
2068 #endif /* FORCE_TPOWERON */
2069
2070 #if defined(BCMPCIE_OOB_HOST_WAKE) && defined(CUSTOMER_HW2) && \
2071 defined(CONFIG_ARCH_APQ8084)
2072 brcm_pcie_wake.wake_irq = wlan_oob_irq;
2073 brcm_pcie_wake.data = bus;
2074 #endif /* BCMPCIE_OOB_HOST_WAKE && CUSTOMR_HW2 && CONFIG_ARCH_APQ8084 */
2075
2076 #ifdef DONGLE_ENABLE_ISOLATION
2077 bus->dhd->dongle_isolation = TRUE;
2078 #endif /* DONGLE_ENABLE_ISOLATION */
2079 #ifdef SUPPORT_LINKDOWN_RECOVERY
2080 #ifdef CONFIG_ARCH_MSM
2081 bus->pcie_event.events = MSM_PCIE_EVENT_LINKDOWN;
2082 bus->pcie_event.user = pdev;
2083 bus->pcie_event.mode = MSM_PCIE_TRIGGER_CALLBACK;
2084 bus->pcie_event.callback = dhdpcie_linkdown_cb;
2085 bus->pcie_event.options = MSM_PCIE_CONFIG_NO_RECOVERY;
2086 msm_pcie_register_event(&bus->pcie_event);
2087 bus->no_cfg_restore = FALSE;
2088 #endif /* CONFIG_ARCH_MSM */
2089 #ifdef EXYNOS_PCIE_LINKDOWN_RECOVERY
2090 #if defined(CONFIG_SOC_EXYNOS8890) || defined(CONFIG_SOC_EXYNOS8895) || \
2091 defined(CONFIG_SOC_EXYNOS9810) || defined(CONFIG_SOC_EXYNOS9820)
2092 bus->pcie_event.events = EXYNOS_PCIE_EVENT_LINKDOWN;
2093 bus->pcie_event.user = pdev;
2094 bus->pcie_event.mode = EXYNOS_PCIE_TRIGGER_CALLBACK;
2095 bus->pcie_event.callback = dhdpcie_linkdown_cb;
2096 exynos_pcie_register_event(&bus->pcie_event);
2097 #endif /* CONFIG_SOC_EXYNOS8890 || CONFIG_SOC_EXYNOS8895 ||
2098 * CONFIG_SOC_EXYNOS9810 || CONFIG_SOC_EXYNOS9820
2099 */
2100 #endif /* EXYNOS_PCIE_LINKDOWN_RECOVERY */
2101 bus->read_shm_fail = FALSE;
2102 #endif /* SUPPORT_LINKDOWN_RECOVERY */
2103
2104 if (bus->intr) {
2105 /* Register interrupt callback, but mask it (not operational yet). */
2106 DHD_INTR(("%s: Registering and masking interrupts\n", __FUNCTION__));
2107 dhdpcie_bus_intr_disable(bus);
2108
2109 if (dhdpcie_request_irq(dhdpcie_info)) {
2110 DHD_ERROR(("%s: request_irq() failed\n", __FUNCTION__));
2111 break;
2112 }
2113 } else {
2114 bus->pollrate = 1;
2115 DHD_INFO(("%s: PCIe interrupt function is NOT registered "
2116 "due to polling mode\n", __FUNCTION__));
2117 }
2118
2119 #if defined(BCM_REQUEST_FW)
2120 if (dhd_bus_download_firmware(bus, osh, NULL, NULL) < 0) {
2121 DHD_ERROR(("%s: failed to download firmware\n", __FUNCTION__));
2122 }
2123 bus->nv_path = NULL;
2124 bus->fw_path = NULL;
2125 #endif /* BCM_REQUEST_FW */
2126
2127 /* set private data for pci_dev */
2128 pci_set_drvdata(pdev, dhdpcie_info);
2129
2130 if (dhd_download_fw_on_driverload) {
2131 if (dhd_bus_start(bus->dhd)) {
2132 DHD_ERROR(("%s: dhd_bud_start() failed\n", __FUNCTION__));
2133 if (!allow_delay_fwdl)
2134 break;
2135 }
2136 } else {
2137 /* Set ramdom MAC address during boot time */
2138 get_random_bytes(&bus->dhd->mac.octet[3], 3);
2139 /* Adding BRCM OUI */
2140 bus->dhd->mac.octet[0] = 0;
2141 bus->dhd->mac.octet[1] = 0x90;
2142 bus->dhd->mac.octet[2] = 0x4C;
2143 }
2144
2145 /* Attach to the OS network interface */
2146 DHD_TRACE(("%s(): Calling dhd_register_if() \n", __FUNCTION__));
2147 if (dhd_attach_net(bus->dhd, TRUE)) {
2148 DHD_ERROR(("%s(): ERROR.. dhd_register_if() failed\n", __FUNCTION__));
2149 break;
2150 }
2151 #ifdef WL_VIF_SUPPORT
2152 /* Attach to the virtual interface */
2153 DHD_TRACE(("%s(): Calling dhd_register_vif() \n", __FUNCTION__));
2154 if (dhd_register_vif(bus->dhd) != 0) {
2155 DHD_ERROR(("%s(): ERROR.. dhd_register_vif() failed\n", __FUNCTION__));
2156 }
2157 #endif // endif
2158
2159 dhdpcie_init_succeeded = TRUE;
2160
2161 #ifdef DHD_PCIE_NATIVE_RUNTIMEPM
2162 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTO_SUSPEND_TIMEOUT);
2163 pm_runtime_use_autosuspend(&pdev->dev);
2164 atomic_set(&bus->dhd->block_bus, FALSE);
2165 #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
2166
2167 DHD_TRACE(("%s:Exit - SUCCESS \n", __FUNCTION__));
2168 return 0; /* return SUCCESS */
2169
2170 } while (0);
2171 /* reverse the initialization in order in case of error */
2172
2173 if (bus)
2174 dhdpcie_bus_release(bus);
2175
2176 #ifdef BCMPCIE_OOB_HOST_WAKE
2177 if (dhdpcie_osinfo) {
2178 MFREE(osh, dhdpcie_osinfo, sizeof(dhdpcie_os_info_t));
2179 }
2180 #endif /* BCMPCIE_OOB_HOST_WAKE */
2181
2182 #ifdef USE_SMMU_ARCH_MSM
2183 if (dhdpcie_smmu_info) {
2184 MFREE(osh, dhdpcie_smmu_info, sizeof(dhdpcie_smmu_info_t));
2185 dhdpcie_info->smmu_cxt = NULL;
2186 }
2187 #endif /* USE_SMMU_ARCH_MSM */
2188
2189 if (dhdpcie_info)
2190 dhdpcie_detach(dhdpcie_info);
2191 pci_disable_device(pdev);
2192 if (osh)
2193 osl_detach(osh);
2194
2195 dhdpcie_init_succeeded = FALSE;
2196
2197 DHD_TRACE(("%s:Exit - FAILURE \n", __FUNCTION__));
2198
2199 return -1; /* return FAILURE */
2200 }
2201
2202 /* Free Linux irq */
2203 void
2204 dhdpcie_free_irq(dhd_bus_t *bus)
2205 {
2206 struct pci_dev *pdev = NULL;
2207
2208 DHD_TRACE(("%s: freeing up the IRQ\n", __FUNCTION__));
2209 if (bus) {
2210 pdev = bus->dev;
2211 if (bus->irq_registered) {
2212 free_irq(pdev->irq, bus);
2213 bus->irq_registered = FALSE;
2214 if (bus->d2h_intr_method == PCIE_MSI) {
2215 dhdpcie_disable_msi(pdev);
2216 }
2217 } else {
2218 DHD_ERROR(("%s: PCIe IRQ is not registered\n", __FUNCTION__));
2219 }
2220 }
2221 DHD_TRACE(("%s: Exit\n", __FUNCTION__));
2222 return;
2223 }
2224
2225 /*
2226
2227 Name: dhdpcie_isr
2228
2229 Parametrs:
2230
2231 1: IN int irq -- interrupt vector
2232 2: IN void *arg -- handle to private data structure
2233
2234 Return value:
2235
2236 Status (TRUE or FALSE)
2237
2238 Description:
2239 Interrupt Service routine checks for the status register,
2240 disable interrupt and queue DPC if mail box interrupts are raised.
2241 */
2242
2243 irqreturn_t
2244 dhdpcie_isr(int irq, void *arg)
2245 {
2246 dhd_bus_t *bus = (dhd_bus_t*)arg;
2247 bus->isr_entry_time = OSL_LOCALTIME_NS();
2248 if (!dhdpcie_bus_isr(bus)) {
2249 DHD_LOG_MEM(("%s: dhdpcie_bus_isr returns with FALSE\n", __FUNCTION__));
2250 }
2251 bus->isr_exit_time = OSL_LOCALTIME_NS();
2252 return IRQ_HANDLED;
2253 }
2254
2255 int
2256 dhdpcie_disable_irq_nosync(dhd_bus_t *bus)
2257 {
2258 struct pci_dev *dev;
2259 if ((bus == NULL) || (bus->dev == NULL)) {
2260 DHD_ERROR(("%s: bus or bus->dev is NULL\n", __FUNCTION__));
2261 return BCME_ERROR;
2262 }
2263
2264 dev = bus->dev;
2265 disable_irq_nosync(dev->irq);
2266 return BCME_OK;
2267 }
2268
2269 int
2270 dhdpcie_disable_irq(dhd_bus_t *bus)
2271 {
2272 struct pci_dev *dev;
2273 if ((bus == NULL) || (bus->dev == NULL)) {
2274 DHD_ERROR(("%s: bus or bus->dev is NULL\n", __FUNCTION__));
2275 return BCME_ERROR;
2276 }
2277
2278 dev = bus->dev;
2279 disable_irq(dev->irq);
2280 return BCME_OK;
2281 }
2282
2283 int
2284 dhdpcie_enable_irq(dhd_bus_t *bus)
2285 {
2286 struct pci_dev *dev;
2287 if ((bus == NULL) || (bus->dev == NULL)) {
2288 DHD_ERROR(("%s: bus or bus->dev is NULL\n", __FUNCTION__));
2289 return BCME_ERROR;
2290 }
2291
2292 dev = bus->dev;
2293 enable_irq(dev->irq);
2294 return BCME_OK;
2295 }
2296
2297 int
2298 dhdpcie_irq_disabled(dhd_bus_t *bus)
2299 {
2300 struct irq_desc *desc = irq_to_desc(bus->dev->irq);
2301 /* depth will be zero, if enabled */
2302 return desc->depth;
2303 }
2304
2305 int
2306 dhdpcie_start_host_pcieclock(dhd_bus_t *bus)
2307 {
2308 int ret = 0;
2309 #ifdef CONFIG_ARCH_MSM
2310 #ifdef SUPPORT_LINKDOWN_RECOVERY
2311 int options = 0;
2312 #endif /* SUPPORT_LINKDOWN_RECOVERY */
2313 #endif /* CONFIG_ARCH_MSM */
2314 DHD_TRACE(("%s Enter:\n", __FUNCTION__));
2315
2316 if (bus == NULL) {
2317 return BCME_ERROR;
2318 }
2319
2320 if (bus->dev == NULL) {
2321 return BCME_ERROR;
2322 }
2323
2324 #ifdef CONFIG_ARCH_MSM
2325 #ifdef SUPPORT_LINKDOWN_RECOVERY
2326 if (bus->no_cfg_restore) {
2327 options = MSM_PCIE_CONFIG_NO_CFG_RESTORE;
2328 }
2329 ret = msm_pcie_pm_control(MSM_PCIE_RESUME, bus->dev->bus->number,
2330 bus->dev, NULL, options);
2331 if (bus->no_cfg_restore && !ret) {
2332 msm_pcie_recover_config(bus->dev);
2333 bus->no_cfg_restore = 0;
2334 }
2335 #else
2336 ret = msm_pcie_pm_control(MSM_PCIE_RESUME, bus->dev->bus->number,
2337 bus->dev, NULL, 0);
2338 #endif /* SUPPORT_LINKDOWN_RECOVERY */
2339 if (ret) {
2340 DHD_ERROR(("%s Failed to bring up PCIe link\n", __FUNCTION__));
2341 goto done;
2342 }
2343
2344 done:
2345 #endif /* CONFIG_ARCH_MSM */
2346 DHD_TRACE(("%s Exit:\n", __FUNCTION__));
2347 return ret;
2348 }
2349
2350 int
2351 dhdpcie_stop_host_pcieclock(dhd_bus_t *bus)
2352 {
2353 int ret = 0;
2354 #ifdef CONFIG_ARCH_MSM
2355 #ifdef SUPPORT_LINKDOWN_RECOVERY
2356 int options = 0;
2357 #endif /* SUPPORT_LINKDOWN_RECOVERY */
2358 #endif /* CONFIG_ARCH_MSM */
2359
2360 DHD_TRACE(("%s Enter:\n", __FUNCTION__));
2361
2362 if (bus == NULL) {
2363 return BCME_ERROR;
2364 }
2365
2366 if (bus->dev == NULL) {
2367 return BCME_ERROR;
2368 }
2369
2370 #ifdef CONFIG_ARCH_MSM
2371 #ifdef SUPPORT_LINKDOWN_RECOVERY
2372 if (bus->no_cfg_restore) {
2373 options = MSM_PCIE_CONFIG_NO_CFG_RESTORE | MSM_PCIE_CONFIG_LINKDOWN;
2374 }
2375
2376 ret = msm_pcie_pm_control(MSM_PCIE_SUSPEND, bus->dev->bus->number,
2377 bus->dev, NULL, options);
2378 #else
2379 ret = msm_pcie_pm_control(MSM_PCIE_SUSPEND, bus->dev->bus->number,
2380 bus->dev, NULL, 0);
2381 #endif /* SUPPORT_LINKDOWN_RECOVERY */
2382 if (ret) {
2383 DHD_ERROR(("Failed to stop PCIe link\n"));
2384 goto done;
2385 }
2386 done:
2387 #endif /* CONFIG_ARCH_MSM */
2388 DHD_TRACE(("%s Exit:\n", __FUNCTION__));
2389 return ret;
2390 }
2391
2392 int
2393 dhdpcie_disable_device(dhd_bus_t *bus)
2394 {
2395 DHD_TRACE(("%s Enter:\n", __FUNCTION__));
2396
2397 if (bus == NULL) {
2398 return BCME_ERROR;
2399 }
2400
2401 if (bus->dev == NULL) {
2402 return BCME_ERROR;
2403 }
2404
2405 if (pci_is_enabled(bus->dev))
2406 pci_disable_device(bus->dev);
2407
2408 return 0;
2409 }
2410
2411 int
2412 dhdpcie_enable_device(dhd_bus_t *bus)
2413 {
2414 int ret = BCME_ERROR;
2415 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
2416 dhdpcie_info_t *pch;
2417 #endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0) */
2418
2419 DHD_TRACE(("%s Enter:\n", __FUNCTION__));
2420
2421 if (bus == NULL) {
2422 return BCME_ERROR;
2423 }
2424
2425 if (bus->dev == NULL) {
2426 return BCME_ERROR;
2427 }
2428
2429 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0))
2430 pch = pci_get_drvdata(bus->dev);
2431 if (pch == NULL) {
2432 return BCME_ERROR;
2433 }
2434
2435 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) && (LINUX_VERSION_CODE < \
2436 KERNEL_VERSION(3, 19, 0)) && !defined(CONFIG_SOC_EXYNOS8890)
2437 /* Updated with pci_load_and_free_saved_state to compatible
2438 * with Kernel version 3.14.0 to 3.18.41.
2439 */
2440 pci_load_and_free_saved_state(bus->dev, &pch->default_state);
2441 pch->default_state = pci_store_saved_state(bus->dev);
2442 #else
2443 pci_load_saved_state(bus->dev, pch->default_state);
2444 #endif /* LINUX_VERSION >= 3.14.0 && LINUX_VERSION < 3.19.0 && !CONFIG_SOC_EXYNOS8890 */
2445
2446 /* Check if Device ID is valid */
2447 if (bus->dev->state_saved) {
2448 uint32 vid, saved_vid;
2449 pci_read_config_dword(bus->dev, PCI_CFG_VID, &vid);
2450 saved_vid = bus->dev->saved_config_space[PCI_CFG_VID];
2451 if (vid != saved_vid) {
2452 DHD_ERROR(("%s: VID(0x%x) is different from saved VID(0x%x) "
2453 "Skip the bus init\n", __FUNCTION__, vid, saved_vid));
2454 bus->no_bus_init = TRUE;
2455 /* Check if the PCIe link is down */
2456 if (vid == (uint32)-1) {
2457 bus->is_linkdown = 1;
2458 #ifdef SUPPORT_LINKDOWN_RECOVERY
2459 #ifdef CONFIG_ARCH_MSM
2460 bus->no_cfg_restore = TRUE;
2461 #endif /* CONFIG_ARCH_MSM */
2462 #endif /* SUPPORT_LINKDOWN_RECOVERY */
2463 }
2464 return BCME_ERROR;
2465 }
2466 }
2467
2468 pci_restore_state(bus->dev);
2469 #endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) */
2470
2471 ret = pci_enable_device(bus->dev);
2472 if (ret) {
2473 pci_disable_device(bus->dev);
2474 } else {
2475 pci_set_master(bus->dev);
2476 }
2477
2478 return ret;
2479 }
2480
2481 int
2482 dhdpcie_alloc_resource(dhd_bus_t *bus)
2483 {
2484 dhdpcie_info_t *dhdpcie_info;
2485 phys_addr_t bar0_addr, bar1_addr;
2486 ulong bar1_size;
2487
2488 do {
2489 if (bus == NULL) {
2490 DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__));
2491 break;
2492 }
2493
2494 if (bus->dev == NULL) {
2495 DHD_ERROR(("%s: bus->dev is NULL\n", __FUNCTION__));
2496 break;
2497 }
2498
2499 dhdpcie_info = pci_get_drvdata(bus->dev);
2500 if (dhdpcie_info == NULL) {
2501 DHD_ERROR(("%s: dhdpcie_info is NULL\n", __FUNCTION__));
2502 break;
2503 }
2504
2505 bar0_addr = pci_resource_start(bus->dev, 0); /* Bar-0 mapped address */
2506 bar1_addr = pci_resource_start(bus->dev, 2); /* Bar-1 mapped address */
2507
2508 /* read Bar-1 mapped memory range */
2509 bar1_size = pci_resource_len(bus->dev, 2);
2510
2511 if ((bar1_size == 0) || (bar1_addr == 0)) {
2512 printf("%s: BAR1 Not enabled for this device size(%ld),"
2513 " addr(0x"PRINTF_RESOURCE")\n",
2514 __FUNCTION__, bar1_size, bar1_addr);
2515 break;
2516 }
2517
2518 dhdpcie_info->regs = (volatile char *) REG_MAP(bar0_addr, DONGLE_REG_MAP_SIZE);
2519 if (!dhdpcie_info->regs) {
2520 DHD_ERROR(("%s: ioremap() for regs is failed\n", __FUNCTION__));
2521 break;
2522 }
2523
2524 bus->regs = dhdpcie_info->regs;
2525 dhdpcie_info->bar1_size =
2526 (bar1_size > DONGLE_TCM_MAP_SIZE) ? bar1_size : DONGLE_TCM_MAP_SIZE;
2527 dhdpcie_info->tcm = (volatile char *) REG_MAP(bar1_addr, dhdpcie_info->bar1_size);
2528 if (!dhdpcie_info->tcm) {
2529 DHD_ERROR(("%s: ioremap() for regs is failed\n", __FUNCTION__));
2530 REG_UNMAP(dhdpcie_info->regs);
2531 bus->regs = NULL;
2532 break;
2533 }
2534
2535 bus->tcm = dhdpcie_info->tcm;
2536
2537 DHD_TRACE(("%s:Phys addr : reg space = %p base addr 0x"PRINTF_RESOURCE" \n",
2538 __FUNCTION__, dhdpcie_info->regs, bar0_addr));
2539 DHD_TRACE(("%s:Phys addr : tcm_space = %p base addr 0x"PRINTF_RESOURCE" \n",
2540 __FUNCTION__, dhdpcie_info->tcm, bar1_addr));
2541
2542 return 0;
2543 } while (0);
2544
2545 return BCME_ERROR;
2546 }
2547
2548 void
2549 dhdpcie_free_resource(dhd_bus_t *bus)
2550 {
2551 dhdpcie_info_t *dhdpcie_info;
2552
2553 if (bus == NULL) {
2554 DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__));
2555 return;
2556 }
2557
2558 if (bus->dev == NULL) {
2559 DHD_ERROR(("%s: bus->dev is NULL\n", __FUNCTION__));
2560 return;
2561 }
2562
2563 dhdpcie_info = pci_get_drvdata(bus->dev);
2564 if (dhdpcie_info == NULL) {
2565 DHD_ERROR(("%s: dhdpcie_info is NULL\n", __FUNCTION__));
2566 return;
2567 }
2568
2569 if (bus->regs) {
2570 REG_UNMAP(dhdpcie_info->regs);
2571 bus->regs = NULL;
2572 }
2573
2574 if (bus->tcm) {
2575 REG_UNMAP(dhdpcie_info->tcm);
2576 bus->tcm = NULL;
2577 }
2578 }
2579
2580 int
2581 dhdpcie_bus_request_irq(struct dhd_bus *bus)
2582 {
2583 dhdpcie_info_t *dhdpcie_info;
2584 int ret = 0;
2585
2586 if (bus == NULL) {
2587 DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__));
2588 return BCME_ERROR;
2589 }
2590
2591 if (bus->dev == NULL) {
2592 DHD_ERROR(("%s: bus->dev is NULL\n", __FUNCTION__));
2593 return BCME_ERROR;
2594 }
2595
2596 dhdpcie_info = pci_get_drvdata(bus->dev);
2597 if (dhdpcie_info == NULL) {
2598 DHD_ERROR(("%s: dhdpcie_info is NULL\n", __FUNCTION__));
2599 return BCME_ERROR;
2600 }
2601
2602 if (bus->intr) {
2603 /* Register interrupt callback, but mask it (not operational yet). */
2604 DHD_INTR(("%s: Registering and masking interrupts\n", __FUNCTION__));
2605 dhdpcie_bus_intr_disable(bus);
2606 ret = dhdpcie_request_irq(dhdpcie_info);
2607 if (ret) {
2608 DHD_ERROR(("%s: request_irq() failed, ret=%d\n",
2609 __FUNCTION__, ret));
2610 return ret;
2611 }
2612 }
2613
2614 return ret;
2615 }
2616
2617 #ifdef BCMPCIE_OOB_HOST_WAKE
2618 #ifdef CONFIG_BCMDHD_GET_OOB_STATE
2619 extern int dhd_get_wlan_oob_gpio(void);
2620 #endif /* CONFIG_BCMDHD_GET_OOB_STATE */
2621
2622 int dhdpcie_get_oob_irq_level(void)
2623 {
2624 int gpio_level;
2625
2626 #ifdef CONFIG_BCMDHD_GET_OOB_STATE
2627 gpio_level = dhd_get_wlan_oob_gpio();
2628 #else
2629 gpio_level = BCME_UNSUPPORTED;
2630 #endif /* CONFIG_BCMDHD_GET_OOB_STATE */
2631 return gpio_level;
2632 }
2633
2634 int dhdpcie_get_oob_irq_status(struct dhd_bus *bus)
2635 {
2636 dhdpcie_info_t *pch;
2637 dhdpcie_os_info_t *dhdpcie_osinfo;
2638
2639 if (bus == NULL) {
2640 DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__));
2641 return 0;
2642 }
2643
2644 if (bus->dev == NULL) {
2645 DHD_ERROR(("%s: bus->dev is NULL\n", __FUNCTION__));
2646 return 0;
2647 }
2648
2649 pch = pci_get_drvdata(bus->dev);
2650 if (pch == NULL) {
2651 DHD_ERROR(("%s: pch is NULL\n", __FUNCTION__));
2652 return 0;
2653 }
2654
2655 dhdpcie_osinfo = (dhdpcie_os_info_t *)pch->os_cxt;
2656
2657 return dhdpcie_osinfo ? dhdpcie_osinfo->oob_irq_enabled : 0;
2658 }
2659
2660 int dhdpcie_get_oob_irq_num(struct dhd_bus *bus)
2661 {
2662 dhdpcie_info_t *pch;
2663 dhdpcie_os_info_t *dhdpcie_osinfo;
2664
2665 if (bus == NULL) {
2666 DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__));
2667 return 0;
2668 }
2669
2670 if (bus->dev == NULL) {
2671 DHD_ERROR(("%s: bus->dev is NULL\n", __FUNCTION__));
2672 return 0;
2673 }
2674
2675 pch = pci_get_drvdata(bus->dev);
2676 if (pch == NULL) {
2677 DHD_ERROR(("%s: pch is NULL\n", __FUNCTION__));
2678 return 0;
2679 }
2680
2681 dhdpcie_osinfo = (dhdpcie_os_info_t *)pch->os_cxt;
2682
2683 return dhdpcie_osinfo ? dhdpcie_osinfo->oob_irq_num : 0;
2684 }
2685
2686 void dhdpcie_oob_intr_set(dhd_bus_t *bus, bool enable)
2687 {
2688 unsigned long flags;
2689 dhdpcie_info_t *pch;
2690 dhdpcie_os_info_t *dhdpcie_osinfo;
2691
2692 if (bus == NULL) {
2693 DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__));
2694 return;
2695 }
2696
2697 if (bus->dev == NULL) {
2698 DHD_ERROR(("%s: bus->dev is NULL\n", __FUNCTION__));
2699 return;
2700 }
2701
2702 pch = pci_get_drvdata(bus->dev);
2703 if (pch == NULL) {
2704 DHD_ERROR(("%s: pch is NULL\n", __FUNCTION__));
2705 return;
2706 }
2707
2708 dhdpcie_osinfo = (dhdpcie_os_info_t *)pch->os_cxt;
2709 spin_lock_irqsave(&dhdpcie_osinfo->oob_irq_spinlock, flags);
2710 if ((dhdpcie_osinfo->oob_irq_enabled != enable) &&
2711 (dhdpcie_osinfo->oob_irq_num > 0)) {
2712 if (enable) {
2713 enable_irq(dhdpcie_osinfo->oob_irq_num);
2714 bus->oob_intr_enable_count++;
2715 bus->last_oob_irq_enable_time = OSL_LOCALTIME_NS();
2716 } else {
2717 disable_irq_nosync(dhdpcie_osinfo->oob_irq_num);
2718 bus->oob_intr_disable_count++;
2719 bus->last_oob_irq_disable_time = OSL_LOCALTIME_NS();
2720 }
2721 dhdpcie_osinfo->oob_irq_enabled = enable;
2722 }
2723 spin_unlock_irqrestore(&dhdpcie_osinfo->oob_irq_spinlock, flags);
2724 }
2725
2726 static irqreturn_t wlan_oob_irq(int irq, void *data)
2727 {
2728 dhd_bus_t *bus;
2729 unsigned long flags_bus;
2730 DHD_TRACE(("%s: IRQ Triggered\n", __FUNCTION__));
2731 bus = (dhd_bus_t *)data;
2732 dhdpcie_oob_intr_set(bus, FALSE);
2733 bus->last_oob_irq_time = OSL_LOCALTIME_NS();
2734 bus->oob_intr_count++;
2735 #ifdef DHD_WAKE_STATUS
2736 #ifdef DHD_PCIE_RUNTIMEPM
2737 /* This condition is for avoiding counting of wake up from Runtime PM */
2738 if (bus->chk_pm)
2739 #endif /* DHD_PCIE_RUNTIMPM */
2740 {
2741 bcmpcie_set_get_wake(bus, 1);
2742 }
2743 #endif /* DHD_WAKE_STATUS */
2744 #ifdef DHD_PCIE_RUNTIMEPM
2745 dhdpcie_runtime_bus_wake(bus->dhd, FALSE, wlan_oob_irq);
2746 #endif /* DHD_PCIE_RUNTIMPM */
2747 #ifdef DHD_PCIE_NATIVE_RUNTIMEPM
2748 dhd_bus_wakeup_work(bus->dhd);
2749 #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
2750 DHD_BUS_LOCK(bus->bus_lock, flags_bus);
2751 /* Hold wakelock if bus_low_power_state is
2752 * DHD_BUS_D3_INFORM_SENT OR DHD_BUS_D3_ACK_RECIEVED
2753 */
2754 if (bus->dhd->up && bus->bus_low_power_state != DHD_BUS_NO_LOW_POWER_STATE) {
2755 DHD_OS_OOB_IRQ_WAKE_LOCK_TIMEOUT(bus->dhd, OOB_WAKE_LOCK_TIMEOUT);
2756 }
2757 DHD_BUS_UNLOCK(bus->bus_lock, flags_bus);
2758 return IRQ_HANDLED;
2759 }
2760
2761 int dhdpcie_oob_intr_register(dhd_bus_t *bus)
2762 {
2763 int err = 0;
2764 dhdpcie_info_t *pch;
2765 dhdpcie_os_info_t *dhdpcie_osinfo;
2766
2767 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
2768 if (bus == NULL) {
2769 DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__));
2770 return -EINVAL;
2771 }
2772
2773 if (bus->dev == NULL) {
2774 DHD_ERROR(("%s: bus->dev is NULL\n", __FUNCTION__));
2775 return -EINVAL;
2776 }
2777
2778 pch = pci_get_drvdata(bus->dev);
2779 if (pch == NULL) {
2780 DHD_ERROR(("%s: pch is NULL\n", __FUNCTION__));
2781 return -EINVAL;
2782 }
2783
2784 dhdpcie_osinfo = (dhdpcie_os_info_t *)pch->os_cxt;
2785 if (dhdpcie_osinfo->oob_irq_registered) {
2786 DHD_ERROR(("%s: irq is already registered\n", __FUNCTION__));
2787 return -EBUSY;
2788 }
2789
2790 if (dhdpcie_osinfo->oob_irq_num > 0) {
2791 DHD_INFO_HW4(("%s OOB irq=%d flags=%X \n", __FUNCTION__,
2792 (int)dhdpcie_osinfo->oob_irq_num,
2793 (int)dhdpcie_osinfo->oob_irq_flags));
2794 err = request_irq(dhdpcie_osinfo->oob_irq_num, wlan_oob_irq,
2795 dhdpcie_osinfo->oob_irq_flags, "dhdpcie_host_wake",
2796 bus);
2797 if (err) {
2798 DHD_ERROR(("%s: request_irq failed with %d\n",
2799 __FUNCTION__, err));
2800 return err;
2801 }
2802 err = enable_irq_wake(dhdpcie_osinfo->oob_irq_num);
2803 if (!err) {
2804 dhdpcie_osinfo->oob_irq_wake_enabled = TRUE;
2805 } else {
2806 /* On Hikey platform enable_irq_wake() is failing with error
2807 * ENXIO (No such device or address). This is because the callback function
2808 * irq_set_wake() is not registered in kernel, hence returning BCME_OK.
2809 */
2810 #ifdef BOARD_HIKEY
2811 DHD_ERROR(("%s: continue eventhough enable_irq_wake failed: %d\n",
2812 __FUNCTION__, err));
2813 err = BCME_OK;
2814 #endif /* BOARD_HIKEY */
2815 }
2816 dhdpcie_osinfo->oob_irq_enabled = TRUE;
2817 }
2818
2819 dhdpcie_osinfo->oob_irq_registered = TRUE;
2820
2821 return err;
2822 }
2823
2824 void dhdpcie_oob_intr_unregister(dhd_bus_t *bus)
2825 {
2826 int err = 0;
2827 dhdpcie_info_t *pch;
2828 dhdpcie_os_info_t *dhdpcie_osinfo;
2829
2830 DHD_TRACE(("%s: Enter\n", __FUNCTION__));
2831 if (bus == NULL) {
2832 DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__));
2833 return;
2834 }
2835
2836 if (bus->dev == NULL) {
2837 DHD_ERROR(("%s: bus->dev is NULL\n", __FUNCTION__));
2838 return;
2839 }
2840
2841 pch = pci_get_drvdata(bus->dev);
2842 if (pch == NULL) {
2843 DHD_ERROR(("%s: pch is NULL\n", __FUNCTION__));
2844 return;
2845 }
2846
2847 dhdpcie_osinfo = (dhdpcie_os_info_t *)pch->os_cxt;
2848 if (!dhdpcie_osinfo->oob_irq_registered) {
2849 DHD_ERROR(("%s: irq is not registered\n", __FUNCTION__));
2850 return;
2851 }
2852 if (dhdpcie_osinfo->oob_irq_num > 0) {
2853 if (dhdpcie_osinfo->oob_irq_wake_enabled) {
2854 err = disable_irq_wake(dhdpcie_osinfo->oob_irq_num);
2855 if (!err) {
2856 dhdpcie_osinfo->oob_irq_wake_enabled = FALSE;
2857 }
2858 }
2859 if (dhdpcie_osinfo->oob_irq_enabled) {
2860 disable_irq(dhdpcie_osinfo->oob_irq_num);
2861 dhdpcie_osinfo->oob_irq_enabled = FALSE;
2862 }
2863 free_irq(dhdpcie_osinfo->oob_irq_num, bus);
2864 }
2865 dhdpcie_osinfo->oob_irq_registered = FALSE;
2866 }
2867 #endif /* BCMPCIE_OOB_HOST_WAKE */
2868
2869 #ifdef DHD_PCIE_RUNTIMEPM
2870 bool dhd_runtimepm_state(dhd_pub_t *dhd)
2871 {
2872 dhd_bus_t *bus;
2873 unsigned long flags;
2874 bus = dhd->bus;
2875
2876 DHD_GENERAL_LOCK(dhd, flags);
2877 bus->idlecount++;
2878
2879 DHD_TRACE(("%s : Enter \n", __FUNCTION__));
2880 if ((bus->idletime > 0) && (bus->idlecount >= bus->idletime)) {
2881 bus->idlecount = 0;
2882 if (DHD_BUS_BUSY_CHECK_IDLE(dhd) && !DHD_BUS_CHECK_DOWN_OR_DOWN_IN_PROGRESS(dhd)) {
2883 bus->bus_wake = 0;
2884 DHD_BUS_BUSY_SET_RPM_SUSPEND_IN_PROGRESS(dhd);
2885 bus->runtime_resume_done = FALSE;
2886 /* stop all interface network queue. */
2887 dhd_bus_stop_queue(bus);
2888 DHD_GENERAL_UNLOCK(dhd, flags);
2889 DHD_ERROR(("%s: DHD Idle state!! - idletime :%d, wdtick :%d \n",
2890 __FUNCTION__, bus->idletime, dhd_runtimepm_ms));
2891 /* RPM suspend is failed, return FALSE then re-trying */
2892 if (dhdpcie_set_suspend_resume(bus, TRUE)) {
2893 DHD_ERROR(("%s: exit with wakelock \n", __FUNCTION__));
2894 DHD_GENERAL_LOCK(dhd, flags);
2895 DHD_BUS_BUSY_CLEAR_RPM_SUSPEND_IN_PROGRESS(dhd);
2896 dhd_os_busbusy_wake(bus->dhd);
2897 bus->runtime_resume_done = TRUE;
2898 /* It can make stuck NET TX Queue without below */
2899 dhd_bus_start_queue(bus);
2900 DHD_GENERAL_UNLOCK(dhd, flags);
2901 smp_wmb();
2902 wake_up_interruptible(&bus->rpm_queue);
2903 return FALSE;
2904 }
2905
2906 DHD_GENERAL_LOCK(dhd, flags);
2907 DHD_BUS_BUSY_CLEAR_RPM_SUSPEND_IN_PROGRESS(dhd);
2908 DHD_BUS_BUSY_SET_RPM_SUSPEND_DONE(dhd);
2909 /* For making sure NET TX Queue active */
2910 dhd_bus_start_queue(bus);
2911 DHD_GENERAL_UNLOCK(dhd, flags);
2912
2913 wait_event_interruptible(bus->rpm_queue, bus->bus_wake);
2914
2915 DHD_GENERAL_LOCK(dhd, flags);
2916 DHD_BUS_BUSY_CLEAR_RPM_SUSPEND_DONE(dhd);
2917 DHD_BUS_BUSY_SET_RPM_RESUME_IN_PROGRESS(dhd);
2918 DHD_GENERAL_UNLOCK(dhd, flags);
2919
2920 dhdpcie_set_suspend_resume(bus, FALSE);
2921
2922 DHD_GENERAL_LOCK(dhd, flags);
2923 DHD_BUS_BUSY_CLEAR_RPM_RESUME_IN_PROGRESS(dhd);
2924 dhd_os_busbusy_wake(bus->dhd);
2925 /* Inform the wake up context that Resume is over */
2926 bus->runtime_resume_done = TRUE;
2927 /* For making sure NET TX Queue active */
2928 dhd_bus_start_queue(bus);
2929 DHD_GENERAL_UNLOCK(dhd, flags);
2930
2931 smp_wmb();
2932 wake_up_interruptible(&bus->rpm_queue);
2933 DHD_ERROR(("%s : runtime resume ended \n", __FUNCTION__));
2934 return TRUE;
2935 } else {
2936 DHD_GENERAL_UNLOCK(dhd, flags);
2937 /* Since one of the contexts are busy (TX, IOVAR or RX)
2938 * we should not suspend
2939 */
2940 DHD_ERROR(("%s : bus is active with dhd_bus_busy_state = 0x%x\n",
2941 __FUNCTION__, dhd->dhd_bus_busy_state));
2942 return FALSE;
2943 }
2944 }
2945
2946 DHD_GENERAL_UNLOCK(dhd, flags);
2947 return FALSE;
2948 } /* dhd_runtimepm_state */
2949
2950 /*
2951 * dhd_runtime_bus_wake
2952 * TRUE - related with runtime pm context
2953 * FALSE - It isn't invloved in runtime pm context
2954 */
2955 bool dhd_runtime_bus_wake(dhd_bus_t *bus, bool wait, void *func_addr)
2956 {
2957 unsigned long flags;
2958 bus->idlecount = 0;
2959 DHD_TRACE(("%s : enter\n", __FUNCTION__));
2960 if (bus->dhd->up == FALSE) {
2961 DHD_INFO(("%s : dhd is not up\n", __FUNCTION__));
2962 return FALSE;
2963 }
2964
2965 DHD_GENERAL_LOCK(bus->dhd, flags);
2966 if (DHD_BUS_BUSY_CHECK_RPM_ALL(bus->dhd)) {
2967 /* Wake up RPM state thread if it is suspend in progress or suspended */
2968 if (DHD_BUS_BUSY_CHECK_RPM_SUSPEND_IN_PROGRESS(bus->dhd) ||
2969 DHD_BUS_BUSY_CHECK_RPM_SUSPEND_DONE(bus->dhd)) {
2970 bus->bus_wake = 1;
2971
2972 DHD_GENERAL_UNLOCK(bus->dhd, flags);
2973
2974 DHD_ERROR(("Runtime Resume is called in %pf\n", func_addr));
2975 smp_wmb();
2976 wake_up_interruptible(&bus->rpm_queue);
2977 /* No need to wake up the RPM state thread */
2978 } else if (DHD_BUS_BUSY_CHECK_RPM_RESUME_IN_PROGRESS(bus->dhd)) {
2979 DHD_GENERAL_UNLOCK(bus->dhd, flags);
2980 }
2981
2982 /* If wait is TRUE, function with wait = TRUE will be wait in here */
2983 if (wait) {
2984 wait_event_interruptible(bus->rpm_queue, bus->runtime_resume_done);
2985 } else {
2986 DHD_INFO(("%s: bus wakeup but no wait until resume done\n", __FUNCTION__));
2987 }
2988 /* If it is called from RPM context, it returns TRUE */
2989 return TRUE;
2990 }
2991
2992 DHD_GENERAL_UNLOCK(bus->dhd, flags);
2993
2994 return FALSE;
2995 }
2996
2997 bool dhdpcie_runtime_bus_wake(dhd_pub_t *dhdp, bool wait, void* func_addr)
2998 {
2999 dhd_bus_t *bus = dhdp->bus;
3000 return dhd_runtime_bus_wake(bus, wait, func_addr);
3001 }
3002
3003 void dhdpcie_block_runtime_pm(dhd_pub_t *dhdp)
3004 {
3005 dhd_bus_t *bus = dhdp->bus;
3006 bus->idletime = 0;
3007 }
3008
3009 bool dhdpcie_is_resume_done(dhd_pub_t *dhdp)
3010 {
3011 dhd_bus_t *bus = dhdp->bus;
3012 return bus->runtime_resume_done;
3013 }
3014 #endif /* DHD_PCIE_RUNTIMEPM */
3015
3016 struct device * dhd_bus_to_dev(dhd_bus_t *bus)
3017 {
3018 struct pci_dev *pdev;
3019 pdev = bus->dev;
3020
3021 if (pdev)
3022 return &pdev->dev;
3023 else
3024 return NULL;
3025 }
3026
3027 #define KIRQ_PRINT_BUF_LEN 256
3028
3029 void
3030 dhd_print_kirqstats(dhd_pub_t *dhd, unsigned int irq_num)
3031 {
3032 unsigned long flags = 0;
3033 struct irq_desc *desc;
3034 int i; /* cpu iterator */
3035 struct bcmstrbuf strbuf;
3036 char tmp_buf[KIRQ_PRINT_BUF_LEN];
3037
3038 desc = irq_to_desc(irq_num);
3039 if (!desc) {
3040 DHD_ERROR(("%s : irqdesc is not found \n", __FUNCTION__));
3041 return;
3042 }
3043 bcm_binit(&strbuf, tmp_buf, KIRQ_PRINT_BUF_LEN);
3044 raw_spin_lock_irqsave(&desc->lock, flags);
3045 bcm_bprintf(&strbuf, "dhd irq %u:", irq_num);
3046 for_each_online_cpu(i)
3047 bcm_bprintf(&strbuf, "%10u ",
3048 desc->kstat_irqs ? *per_cpu_ptr(desc->kstat_irqs, i) : 0);
3049 if (desc->irq_data.chip) {
3050 if (desc->irq_data.chip->name)
3051 bcm_bprintf(&strbuf, " %8s", desc->irq_data.chip->name);
3052 else
3053 bcm_bprintf(&strbuf, " %8s", "-");
3054 } else {
3055 bcm_bprintf(&strbuf, " %8s", "None");
3056 }
3057 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0))
3058 if (desc->irq_data.domain)
3059 bcm_bprintf(&strbuf, " %d", (int)desc->irq_data.hwirq);
3060 #ifdef CONFIG_GENERIC_IRQ_SHOW_LEVEL
3061 bcm_bprintf(&strbuf, " %-8s", irqd_is_level_type(&desc->irq_data) ? "Level" : "Edge");
3062 #endif // endif
3063 #endif /* LINUX VERSION > 3.1.0 */
3064
3065 if (desc->name)
3066 bcm_bprintf(&strbuf, "-%-8s", desc->name);
3067
3068 DHD_ERROR(("%s\n", strbuf.origbuf));
3069 raw_spin_unlock_irqrestore(&desc->lock, flags);
3070 }
3071
3072 void
3073 dhd_show_kirqstats(dhd_pub_t *dhd)
3074 {
3075 unsigned int irq = -1;
3076 #ifdef BCMPCIE
3077 dhdpcie_get_pcieirq(dhd->bus, &irq);
3078 #endif /* BCMPCIE */
3079 #ifdef BCMSDIO
3080 irq = ((wifi_adapter_info_t *)dhd->info->adapter)->irq_num;
3081 #endif /* BCMSDIO */
3082 if (irq != -1) {
3083 #ifdef BCMPCIE
3084 DHD_ERROR(("DUMP data kernel irq stats : \n"));
3085 #endif /* BCMPCIE */
3086 #ifdef BCMSDIO
3087 DHD_ERROR(("DUMP data/host wakeup kernel irq stats : \n"));
3088 #endif /* BCMSDIO */
3089 dhd_print_kirqstats(dhd, irq);
3090 }
3091 #ifdef BCMPCIE_OOB_HOST_WAKE
3092 irq = dhdpcie_get_oob_irq_num(dhd->bus);
3093 if (irq) {
3094 DHD_ERROR(("DUMP PCIE host wakeup kernel irq stats : \n"));
3095 dhd_print_kirqstats(dhd, irq);
3096 }
3097 #endif /* BCMPCIE_OOB_HOST_WAKE */
3098 }
3099
3100 #ifdef DHD_FW_COREDUMP
3101 #ifdef BCMDHDX
3102 int
3103 dhdx_dongle_mem_dump()
3104 {
3105 if (!g_dhd_bus) {
3106 DHD_ERROR(("%s: Bus is NULL\n", __FUNCTION__));
3107 return -ENODEV;
3108 }
3109
3110 dhd_bus_dump_console_buffer(g_dhd_bus);
3111 dhd_prot_debug_info_print(g_dhd_bus->dhd);
3112
3113 g_dhd_bus->dhd->memdump_enabled = DUMP_MEMFILE_BUGON;
3114 g_dhd_bus->dhd->memdump_type = DUMP_TYPE_AP_ABNORMAL_ACCESS;
3115
3116 #ifdef DHD_PCIE_RUNTIMEPM
3117 dhdpcie_runtime_bus_wake(g_dhd_bus->dhd, TRUE, __builtin_return_address(0));
3118 #endif /* DHD_PCIE_RUNTIMEPM */
3119
3120 dhd_bus_mem_dump(g_dhd_bus->dhd);
3121 return 0;
3122 }
3123 #else
3124 int
3125 dhd_dongle_mem_dump(void)
3126 {
3127 if (!g_dhd_bus) {
3128 DHD_ERROR(("%s: Bus is NULL\n", __FUNCTION__));
3129 return -ENODEV;
3130 }
3131
3132 dhd_bus_dump_console_buffer(g_dhd_bus);
3133 dhd_prot_debug_info_print(g_dhd_bus->dhd);
3134
3135 g_dhd_bus->dhd->memdump_enabled = DUMP_MEMFILE_BUGON;
3136 g_dhd_bus->dhd->memdump_type = DUMP_TYPE_AP_ABNORMAL_ACCESS;
3137
3138 #ifdef DHD_PCIE_RUNTIMEPM
3139 dhdpcie_runtime_bus_wake(g_dhd_bus->dhd, TRUE, __builtin_return_address(0));
3140 #endif /* DHD_PCIE_RUNTIMEPM */
3141
3142 dhd_bus_mem_dump(g_dhd_bus->dhd);
3143 return 0;
3144 }
3145 #endif /* BCMDHDX */
3146 #endif /* DHD_FW_COREDUMP */
3147
3148 #ifdef BCMDHDX
3149 bool
3150 dhdx_bus_check_driver_up(void)
3151 {
3152 dhd_bus_t *bus;
3153 dhd_pub_t *dhdp;
3154 bool isup = FALSE;
3155
3156 bus = (dhd_bus_t *)g_dhd_bus;
3157 if (!bus) {
3158 DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__));
3159 return isup;
3160 }
3161
3162 dhdp = bus->dhd;
3163 if (dhdp) {
3164 isup = dhdp->up;
3165 }
3166
3167 return isup;
3168 }
3169 #else
3170 bool
3171 dhd_bus_check_driver_up(void)
3172 {
3173 dhd_bus_t *bus;
3174 dhd_pub_t *dhdp;
3175 bool isup = FALSE;
3176
3177 bus = (dhd_bus_t *)g_dhd_bus;
3178 if (!bus) {
3179 DHD_ERROR(("%s: bus is NULL\n", __FUNCTION__));
3180 return isup;
3181 }
3182
3183 dhdp = bus->dhd;
3184 if (dhdp) {
3185 isup = dhdp->up;
3186 }
3187
3188 return isup;
3189 }
3190 #endif /* BCMDHDX */
3191