1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Header file describing the internal (inter-module) DHD interfaces.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Provides type definitions and function prototypes used to link the
5*4882a593Smuzhiyun * DHD OS, bus, and protocol modules.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Portions of this code are copyright (c) 2021 Cypress Semiconductor Corporation
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Copyright (C) 1999-2017, Broadcom Corporation
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * Unless you and Broadcom execute a separate written software license
12*4882a593Smuzhiyun * agreement governing use of this software, this software is licensed to you
13*4882a593Smuzhiyun * under the terms of the GNU General Public License version 2 (the "GPL"),
14*4882a593Smuzhiyun * available at http://www.broadcom.com/licenses/GPLv2.php, with the
15*4882a593Smuzhiyun * following added to such license:
16*4882a593Smuzhiyun *
17*4882a593Smuzhiyun * As a special exception, the copyright holders of this software give you
18*4882a593Smuzhiyun * permission to link this software with independent modules, and to copy and
19*4882a593Smuzhiyun * distribute the resulting executable under terms of your choice, provided that
20*4882a593Smuzhiyun * you also meet, for each linked independent module, the terms and conditions of
21*4882a593Smuzhiyun * the license of that module. An independent module is a module which is not
22*4882a593Smuzhiyun * derived from this software. The special exception does not apply to any
23*4882a593Smuzhiyun * modifications of the software.
24*4882a593Smuzhiyun *
25*4882a593Smuzhiyun * Notwithstanding the above, under no circumstances may you combine this
26*4882a593Smuzhiyun * software in any way with any other Broadcom software provided under a license
27*4882a593Smuzhiyun * other than the GPL, without Broadcom's express prior written consent.
28*4882a593Smuzhiyun *
29*4882a593Smuzhiyun *
30*4882a593Smuzhiyun * <<Broadcom-WL-IPTag/Open:>>
31*4882a593Smuzhiyun *
32*4882a593Smuzhiyun * $Id: dhd.h 701844 2017-05-26 18:56:40Z $
33*4882a593Smuzhiyun */
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /****************
36*4882a593Smuzhiyun * Common types *
37*4882a593Smuzhiyun */
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #ifndef _dhd_h_
40*4882a593Smuzhiyun #define _dhd_h_
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #include <linux/init.h>
43*4882a593Smuzhiyun #include <linux/kernel.h>
44*4882a593Smuzhiyun #include <linux/slab.h>
45*4882a593Smuzhiyun #include <linux/skbuff.h>
46*4882a593Smuzhiyun #include <linux/netdevice.h>
47*4882a593Smuzhiyun #include <linux/etherdevice.h>
48*4882a593Smuzhiyun #include <linux/random.h>
49*4882a593Smuzhiyun #include <linux/spinlock.h>
50*4882a593Smuzhiyun #include <linux/ethtool.h>
51*4882a593Smuzhiyun #include <linux/fs.h>
52*4882a593Smuzhiyun #include <linux/proc_fs.h>
53*4882a593Smuzhiyun #include <asm/uaccess.h>
54*4882a593Smuzhiyun #include <asm/unaligned.h>
55*4882a593Smuzhiyun #if defined(CONFIG_PM_WAKELOCKS) || defined(CONFIG_HAS_WAKELOCK)
56*4882a593Smuzhiyun #include <linux/wakelock.h>
57*4882a593Smuzhiyun #endif /* CONFIG_PM_WAKELOCKS || CONFIG_HAS_WAKELOCK */
58*4882a593Smuzhiyun #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0)
59*4882a593Smuzhiyun #include <linux/sched/types.h>
60*4882a593Smuzhiyun #endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0) */
61*4882a593Smuzhiyun /* The kernel threading is sdio-specific */
62*4882a593Smuzhiyun struct task_struct;
63*4882a593Smuzhiyun struct sched_param;
64*4882a593Smuzhiyun #if defined(BT_OVER_SDIO)
65*4882a593Smuzhiyun #include <dhd_bt_interface.h>
66*4882a593Smuzhiyun #endif /* defined (BT_OVER_SDIO) */
67*4882a593Smuzhiyun int setScheduler(struct task_struct *p, int policy, struct sched_param *param);
68*4882a593Smuzhiyun int get_scheduler_policy(struct task_struct *p);
69*4882a593Smuzhiyun #define MAX_EVENT 16
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun #define ALL_INTERFACES 0xff
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /* H2D and D2H ring dump is enabled by default */
74*4882a593Smuzhiyun #ifdef PCIE_FULL_DONGLE
75*4882a593Smuzhiyun #define DHD_DUMP_PCIE_RINGS
76*4882a593Smuzhiyun #endif /* PCIE_FULL_DONGLE */
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun #include <wlioctl.h>
79*4882a593Smuzhiyun #include <bcmstdlib_s.h>
80*4882a593Smuzhiyun #include <dhdioctl.h>
81*4882a593Smuzhiyun #include <wlfc_proto.h>
82*4882a593Smuzhiyun #include <hnd_armtrap.h>
83*4882a593Smuzhiyun #if defined(DUMP_IOCTL_IOV_LIST) || defined(DHD_DEBUG)
84*4882a593Smuzhiyun #include <bcmutils.h>
85*4882a593Smuzhiyun #endif /* DUMP_IOCTL_IOV_LIST || DHD_DEBUG */
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun #if defined(BCMWDF)
88*4882a593Smuzhiyun #include <wdf.h>
89*4882a593Smuzhiyun #include <WdfMiniport.h>
90*4882a593Smuzhiyun #endif /* (BCMWDF) */
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun #ifdef WL_CFGVENDOR_SEND_HANG_EVENT
93*4882a593Smuzhiyun #include <rte_ioctl.h>
94*4882a593Smuzhiyun #endif /* WL_CFGVENDOR_SEND_HANG_EVENT */
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun #ifdef DHD_ERPOM
97*4882a593Smuzhiyun #include <pom.h>
98*4882a593Smuzhiyun #endif /* DHD_ERPOM */
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun #include <dngl_stats.h>
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun #ifdef DEBUG_DPC_THREAD_WATCHDOG
103*4882a593Smuzhiyun #define MAX_RESCHED_CNT 600
104*4882a593Smuzhiyun #endif /* DEBUG_DPC_THREAD_WATCHDOG */
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun #if defined(KEEP_ALIVE)
107*4882a593Smuzhiyun /* Default KEEP_ALIVE Period is 55 sec to prevent AP from sending Keep Alive probe frame */
108*4882a593Smuzhiyun #define KEEP_ALIVE_PERIOD 55000
109*4882a593Smuzhiyun #define NULL_PKT_STR "null_pkt"
110*4882a593Smuzhiyun #endif /* KEEP_ALIVE */
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun /* By default enabled from here, later the WQ code will be removed */
113*4882a593Smuzhiyun #define DHD_USE_KTHREAD_FOR_LOGTRACE
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun /*
116*4882a593Smuzhiyun * Earlier DHD used to have it own time stamp for printk and
117*4882a593Smuzhiyun * Dongle used to have its own time stamp for console messages
118*4882a593Smuzhiyun * With this flag, DHD and Dongle console messges will have same time zone
119*4882a593Smuzhiyun */
120*4882a593Smuzhiyun #define DHD_H2D_LOG_TIME_SYNC
121*4882a593Smuzhiyun /* Forward decls */
122*4882a593Smuzhiyun struct dhd_bus;
123*4882a593Smuzhiyun struct dhd_prot;
124*4882a593Smuzhiyun struct dhd_info;
125*4882a593Smuzhiyun struct dhd_ioctl;
126*4882a593Smuzhiyun struct dhd_dbg;
127*4882a593Smuzhiyun struct dhd_ts;
128*4882a593Smuzhiyun #ifdef DNGL_AXI_ERROR_LOGGING
129*4882a593Smuzhiyun struct dhd_axi_error_dump;
130*4882a593Smuzhiyun #endif /* DNGL_AXI_ERROR_LOGGING */
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun /* The level of bus communication with the dongle */
133*4882a593Smuzhiyun enum dhd_bus_state {
134*4882a593Smuzhiyun DHD_BUS_DOWN, /* Not ready for frame transfers */
135*4882a593Smuzhiyun DHD_BUS_LOAD, /* Download access only (CPU reset) */
136*4882a593Smuzhiyun DHD_BUS_DATA, /* Ready for frame transfers */
137*4882a593Smuzhiyun DHD_BUS_SUSPEND, /* Bus has been suspended */
138*4882a593Smuzhiyun DHD_BUS_DOWN_IN_PROGRESS, /* Bus going Down */
139*4882a593Smuzhiyun };
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun /* The level of bus communication with the dongle */
142*4882a593Smuzhiyun enum dhd_bus_devreset_type {
143*4882a593Smuzhiyun DHD_BUS_DEVRESET_ON = 0, /* ON */
144*4882a593Smuzhiyun DHD_BUS_DEVRESET_OFF = 1, /* OFF */
145*4882a593Smuzhiyun DHD_BUS_DEVRESET_FLR = 2, /* FLR */
146*4882a593Smuzhiyun DHD_BUS_DEVRESET_FLR_FORCE_FAIL = 3, /* FLR FORCE FAIL */
147*4882a593Smuzhiyun DHD_BUS_DEVRESET_QUIESCE = 4, /* FLR */
148*4882a593Smuzhiyun };
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun /*
151*4882a593Smuzhiyun * Bit fields to Indicate clean up process that wait till they are finished.
152*4882a593Smuzhiyun * Future synchronizable processes can add their bit filed below and update
153*4882a593Smuzhiyun * their functionalities accordingly
154*4882a593Smuzhiyun */
155*4882a593Smuzhiyun #define DHD_BUS_BUSY_IN_TX 0x01
156*4882a593Smuzhiyun #define DHD_BUS_BUSY_IN_SEND_PKT 0x02
157*4882a593Smuzhiyun #define DHD_BUS_BUSY_IN_DPC 0x04
158*4882a593Smuzhiyun #define DHD_BUS_BUSY_IN_WD 0x08
159*4882a593Smuzhiyun #define DHD_BUS_BUSY_IN_IOVAR 0x10
160*4882a593Smuzhiyun #define DHD_BUS_BUSY_IN_DHD_IOVAR 0x20
161*4882a593Smuzhiyun #define DHD_BUS_BUSY_SUSPEND_IN_PROGRESS 0x40
162*4882a593Smuzhiyun #define DHD_BUS_BUSY_RESUME_IN_PROGRESS 0x80
163*4882a593Smuzhiyun #define DHD_BUS_BUSY_RPM_SUSPEND_IN_PROGRESS 0x100
164*4882a593Smuzhiyun #define DHD_BUS_BUSY_RPM_SUSPEND_DONE 0x200
165*4882a593Smuzhiyun #define DHD_BUS_BUSY_RPM_RESUME_IN_PROGRESS 0x400
166*4882a593Smuzhiyun #define DHD_BUS_BUSY_RPM_ALL (DHD_BUS_BUSY_RPM_SUSPEND_DONE | \
167*4882a593Smuzhiyun DHD_BUS_BUSY_RPM_SUSPEND_IN_PROGRESS | \
168*4882a593Smuzhiyun DHD_BUS_BUSY_RPM_RESUME_IN_PROGRESS)
169*4882a593Smuzhiyun #define DHD_BUS_BUSY_IN_CHECKDIED 0x800
170*4882a593Smuzhiyun #define DHD_BUS_BUSY_IN_MEMDUMP 0x1000
171*4882a593Smuzhiyun #define DHD_BUS_BUSY_IN_SSSRDUMP 0x2000
172*4882a593Smuzhiyun #define DHD_BUS_BUSY_IN_LOGDUMP 0x4000
173*4882a593Smuzhiyun #define DHD_BUS_BUSY_IN_HALDUMP 0x8000
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun #define DHD_BUS_BUSY_SET_IN_TX(dhdp) \
176*4882a593Smuzhiyun (dhdp)->dhd_bus_busy_state |= DHD_BUS_BUSY_IN_TX
177*4882a593Smuzhiyun #define DHD_BUS_BUSY_SET_IN_SEND_PKT(dhdp) \
178*4882a593Smuzhiyun (dhdp)->dhd_bus_busy_state |= DHD_BUS_BUSY_IN_SEND_PKT
179*4882a593Smuzhiyun #define DHD_BUS_BUSY_SET_IN_DPC(dhdp) \
180*4882a593Smuzhiyun (dhdp)->dhd_bus_busy_state |= DHD_BUS_BUSY_IN_DPC
181*4882a593Smuzhiyun #define DHD_BUS_BUSY_SET_IN_WD(dhdp) \
182*4882a593Smuzhiyun (dhdp)->dhd_bus_busy_state |= DHD_BUS_BUSY_IN_WD
183*4882a593Smuzhiyun #define DHD_BUS_BUSY_SET_IN_IOVAR(dhdp) \
184*4882a593Smuzhiyun (dhdp)->dhd_bus_busy_state |= DHD_BUS_BUSY_IN_IOVAR
185*4882a593Smuzhiyun #define DHD_BUS_BUSY_SET_IN_DHD_IOVAR(dhdp) \
186*4882a593Smuzhiyun (dhdp)->dhd_bus_busy_state |= DHD_BUS_BUSY_IN_DHD_IOVAR
187*4882a593Smuzhiyun #define DHD_BUS_BUSY_SET_SUSPEND_IN_PROGRESS(dhdp) \
188*4882a593Smuzhiyun (dhdp)->dhd_bus_busy_state |= DHD_BUS_BUSY_SUSPEND_IN_PROGRESS
189*4882a593Smuzhiyun #define DHD_BUS_BUSY_SET_RESUME_IN_PROGRESS(dhdp) \
190*4882a593Smuzhiyun (dhdp)->dhd_bus_busy_state |= DHD_BUS_BUSY_RESUME_IN_PROGRESS
191*4882a593Smuzhiyun #define DHD_BUS_BUSY_SET_RPM_SUSPEND_IN_PROGRESS(dhdp) \
192*4882a593Smuzhiyun (dhdp)->dhd_bus_busy_state |= DHD_BUS_BUSY_RPM_SUSPEND_IN_PROGRESS
193*4882a593Smuzhiyun #define DHD_BUS_BUSY_SET_RPM_SUSPEND_DONE(dhdp) \
194*4882a593Smuzhiyun (dhdp)->dhd_bus_busy_state |= DHD_BUS_BUSY_RPM_SUSPEND_DONE
195*4882a593Smuzhiyun #define DHD_BUS_BUSY_SET_RPM_RESUME_IN_PROGRESS(dhdp) \
196*4882a593Smuzhiyun (dhdp)->dhd_bus_busy_state |= DHD_BUS_BUSY_RPM_RESUME_IN_PROGRESS
197*4882a593Smuzhiyun #define DHD_BUS_BUSY_SET_IN_CHECKDIED(dhdp) \
198*4882a593Smuzhiyun (dhdp)->dhd_bus_busy_state |= DHD_BUS_BUSY_IN_CHECKDIED
199*4882a593Smuzhiyun #define DHD_BUS_BUSY_SET_IN_MEMDUMP(dhdp) \
200*4882a593Smuzhiyun (dhdp)->dhd_bus_busy_state |= DHD_BUS_BUSY_IN_MEMDUMP
201*4882a593Smuzhiyun #define DHD_BUS_BUSY_SET_IN_SSSRDUMP(dhdp) \
202*4882a593Smuzhiyun (dhdp)->dhd_bus_busy_state |= DHD_BUS_BUSY_IN_SSSRDUMP
203*4882a593Smuzhiyun #define DHD_BUS_BUSY_SET_IN_LOGDUMP(dhdp) \
204*4882a593Smuzhiyun (dhdp)->dhd_bus_busy_state |= DHD_BUS_BUSY_IN_LOGDUMP
205*4882a593Smuzhiyun #define DHD_BUS_BUSY_SET_IN_HALDUMP(dhdp) \
206*4882a593Smuzhiyun (dhdp)->dhd_bus_busy_state |= DHD_BUS_BUSY_IN_HALDUMP
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun #define DHD_BUS_BUSY_CLEAR_IN_TX(dhdp) \
209*4882a593Smuzhiyun (dhdp)->dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_TX
210*4882a593Smuzhiyun #define DHD_BUS_BUSY_CLEAR_IN_SEND_PKT(dhdp) \
211*4882a593Smuzhiyun (dhdp)->dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_SEND_PKT
212*4882a593Smuzhiyun #define DHD_BUS_BUSY_CLEAR_IN_DPC(dhdp) \
213*4882a593Smuzhiyun (dhdp)->dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_DPC
214*4882a593Smuzhiyun #define DHD_BUS_BUSY_CLEAR_IN_WD(dhdp) \
215*4882a593Smuzhiyun (dhdp)->dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_WD
216*4882a593Smuzhiyun #define DHD_BUS_BUSY_CLEAR_IN_IOVAR(dhdp) \
217*4882a593Smuzhiyun (dhdp)->dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_IOVAR
218*4882a593Smuzhiyun #define DHD_BUS_BUSY_CLEAR_IN_DHD_IOVAR(dhdp) \
219*4882a593Smuzhiyun (dhdp)->dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_DHD_IOVAR
220*4882a593Smuzhiyun #define DHD_BUS_BUSY_CLEAR_SUSPEND_IN_PROGRESS(dhdp) \
221*4882a593Smuzhiyun (dhdp)->dhd_bus_busy_state &= ~DHD_BUS_BUSY_SUSPEND_IN_PROGRESS
222*4882a593Smuzhiyun #define DHD_BUS_BUSY_CLEAR_RESUME_IN_PROGRESS(dhdp) \
223*4882a593Smuzhiyun (dhdp)->dhd_bus_busy_state &= ~DHD_BUS_BUSY_RESUME_IN_PROGRESS
224*4882a593Smuzhiyun #define DHD_BUS_BUSY_CLEAR_RPM_SUSPEND_IN_PROGRESS(dhdp) \
225*4882a593Smuzhiyun (dhdp)->dhd_bus_busy_state &= ~DHD_BUS_BUSY_RPM_SUSPEND_IN_PROGRESS
226*4882a593Smuzhiyun #define DHD_BUS_BUSY_CLEAR_RPM_SUSPEND_DONE(dhdp) \
227*4882a593Smuzhiyun (dhdp)->dhd_bus_busy_state &= ~DHD_BUS_BUSY_RPM_SUSPEND_DONE
228*4882a593Smuzhiyun #define DHD_BUS_BUSY_CLEAR_RPM_RESUME_IN_PROGRESS(dhdp) \
229*4882a593Smuzhiyun (dhdp)->dhd_bus_busy_state &= ~DHD_BUS_BUSY_RPM_RESUME_IN_PROGRESS
230*4882a593Smuzhiyun #define DHD_BUS_BUSY_CLEAR_IN_CHECKDIED(dhdp) \
231*4882a593Smuzhiyun (dhdp)->dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_CHECKDIED
232*4882a593Smuzhiyun #define DHD_BUS_BUSY_CLEAR_IN_MEMDUMP(dhdp) \
233*4882a593Smuzhiyun (dhdp)->dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_MEMDUMP
234*4882a593Smuzhiyun #define DHD_BUS_BUSY_CLEAR_IN_SSSRDUMP(dhdp) \
235*4882a593Smuzhiyun (dhdp)->dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_SSSRDUMP
236*4882a593Smuzhiyun #define DHD_BUS_BUSY_CLEAR_IN_LOGDUMP(dhdp) \
237*4882a593Smuzhiyun (dhdp)->dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_LOGDUMP
238*4882a593Smuzhiyun #define DHD_BUS_BUSY_CLEAR_IN_HALDUMP(dhdp) \
239*4882a593Smuzhiyun (dhdp)->dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_HALDUMP
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun #define DHD_BUS_BUSY_CHECK_IN_TX(dhdp) \
242*4882a593Smuzhiyun ((dhdp)->dhd_bus_busy_state & DHD_BUS_BUSY_IN_TX)
243*4882a593Smuzhiyun #define DHD_BUS_BUSY_CHECK_IN_SEND_PKT(dhdp) \
244*4882a593Smuzhiyun ((dhdp)->dhd_bus_busy_state & DHD_BUS_BUSY_IN_SEND_PKT)
245*4882a593Smuzhiyun #define DHD_BUS_BUSY_CHECK_IN_DPC(dhdp) \
246*4882a593Smuzhiyun ((dhdp)->dhd_bus_busy_state & DHD_BUS_BUSY_IN_DPC)
247*4882a593Smuzhiyun #define DHD_BUS_BUSY_CHECK_IN_WD(dhdp) \
248*4882a593Smuzhiyun ((dhdp)->dhd_bus_busy_state & DHD_BUS_BUSY_IN_WD)
249*4882a593Smuzhiyun #define DHD_BUS_BUSY_CHECK_IN_IOVAR(dhdp) \
250*4882a593Smuzhiyun ((dhdp)->dhd_bus_busy_state & DHD_BUS_BUSY_IN_IOVAR)
251*4882a593Smuzhiyun #define DHD_BUS_BUSY_CHECK_IN_DHD_IOVAR(dhdp) \
252*4882a593Smuzhiyun ((dhdp)->dhd_bus_busy_state & DHD_BUS_BUSY_IN_DHD_IOVAR)
253*4882a593Smuzhiyun #define DHD_BUS_BUSY_CHECK_SUSPEND_IN_PROGRESS(dhdp) \
254*4882a593Smuzhiyun ((dhdp)->dhd_bus_busy_state & DHD_BUS_BUSY_SUSPEND_IN_PROGRESS)
255*4882a593Smuzhiyun #define DHD_BUS_BUSY_CHECK_RESUME_IN_PROGRESS(dhdp) \
256*4882a593Smuzhiyun ((dhdp)->dhd_bus_busy_state & DHD_BUS_BUSY_RESUME_IN_PROGRESS)
257*4882a593Smuzhiyun #define DHD_BUS_BUSY_CHECK_RPM_SUSPEND_IN_PROGRESS(dhdp) \
258*4882a593Smuzhiyun ((dhdp)->dhd_bus_busy_state & DHD_BUS_BUSY_RPM_SUSPEND_IN_PROGRESS)
259*4882a593Smuzhiyun #define DHD_BUS_BUSY_CHECK_RPM_SUSPEND_DONE(dhdp) \
260*4882a593Smuzhiyun ((dhdp)->dhd_bus_busy_state & DHD_BUS_BUSY_RPM_SUSPEND_DONE)
261*4882a593Smuzhiyun #define DHD_BUS_BUSY_CHECK_RPM_RESUME_IN_PROGRESS(dhdp) \
262*4882a593Smuzhiyun ((dhdp)->dhd_bus_busy_state & DHD_BUS_BUSY_RPM_RESUME_IN_PROGRESS)
263*4882a593Smuzhiyun #define DHD_BUS_BUSY_CHECK_RPM_ALL(dhdp) \
264*4882a593Smuzhiyun ((dhdp)->dhd_bus_busy_state & DHD_BUS_BUSY_RPM_ALL)
265*4882a593Smuzhiyun #define DHD_BUS_BUSY_CHECK_IN_CHECKDIED(dhdp) \
266*4882a593Smuzhiyun ((dhdp)->dhd_bus_busy_state & DHD_BUS_BUSY_IN_CHECKDIED)
267*4882a593Smuzhiyun #define DHD_BUS_BUSY_CHECK_IN_MEMDUMP(dhdp) \
268*4882a593Smuzhiyun ((dhdp)->dhd_bus_busy_state & DHD_BUS_BUSY_IN_MEMDUMP)
269*4882a593Smuzhiyun #define DHD_BUS_BUSY_CHECK_IN_SSSRDUMP(dhdp) \
270*4882a593Smuzhiyun ((dhdp)->dhd_bus_busy_state & DHD_BUS_BUSY_IN_SSSRDUMP)
271*4882a593Smuzhiyun #define DHD_BUS_BUSY_CHECK_IN_LOGDUMP(dhdp) \
272*4882a593Smuzhiyun ((dhdp)->dhd_bus_busy_state & DHD_BUS_BUSY_IN_LOGDUMP)
273*4882a593Smuzhiyun #define DHD_BUS_BUSY_CHECK_IN_HALDUMP(dhdp) \
274*4882a593Smuzhiyun ((dhdp)->dhd_bus_busy_state & DHD_BUS_BUSY_IN_HALDUMP)
275*4882a593Smuzhiyun #define DHD_BUS_BUSY_CHECK_IDLE(dhdp) \
276*4882a593Smuzhiyun ((dhdp)->dhd_bus_busy_state == 0)
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun #define DHD_BUS_CHECK_SUSPEND_OR_SUSPEND_IN_PROGRESS(dhdp) \
279*4882a593Smuzhiyun ((dhdp)->busstate == DHD_BUS_SUSPEND || DHD_BUS_BUSY_CHECK_SUSPEND_IN_PROGRESS(dhdp))
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun #define DHD_BUS_CHECK_ANY_SUSPEND_IN_PROGRESS(dhdp) \
282*4882a593Smuzhiyun (DHD_BUS_BUSY_CHECK_SUSPEND_IN_PROGRESS(dhdp) || \
283*4882a593Smuzhiyun DHD_BUS_BUSY_CHECK_RPM_SUSPEND_IN_PROGRESS(dhdp))
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun #define DHD_BUS_CHECK_SUSPEND_OR_ANY_SUSPEND_IN_PROGRESS(dhdp) \
286*4882a593Smuzhiyun ((dhdp)->busstate == DHD_BUS_SUSPEND || DHD_BUS_CHECK_ANY_SUSPEND_IN_PROGRESS(dhdp))
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun #define DHD_BUS_CHECK_DOWN_OR_DOWN_IN_PROGRESS(dhdp) \
289*4882a593Smuzhiyun ((dhdp)->busstate == DHD_BUS_DOWN || (dhdp)->busstate == DHD_BUS_DOWN_IN_PROGRESS)
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun /* IOVar flags for common error checks */
292*4882a593Smuzhiyun #define DHD_IOVF_PWRREQ_BYPASS (1<<0) /* flags to prevent bp access during host sleep state */
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun #define MAX_MTU_SZ (1600u)
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun /* (u64)result = (u64)dividend / (u64)divisor */
297*4882a593Smuzhiyun #define DIV_U64_BY_U64(dividend, divisor) div64_u64(dividend, divisor)
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun /* (u64)result = (u64)dividend / (u32)divisor */
300*4882a593Smuzhiyun #define DIV_U64_BY_U32(dividend, divisor) div_u64(dividend, divisor)
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun /* Be careful while using this, as it divides dividend also
303*4882a593Smuzhiyun * (u32)remainder = (u64)dividend % (u32)divisor
304*4882a593Smuzhiyun * (u64)dividend = (u64)dividend / (u32)divisor
305*4882a593Smuzhiyun */
306*4882a593Smuzhiyun #define DIV_AND_MOD_U64_BY_U32(dividend, divisor) do_div(dividend, divisor)
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun /* (u32)remainder = (u64)dividend % (u32)divisor */
309*4882a593Smuzhiyun #define MOD_U64_BY_U32(dividend, divisor) ({ \
310*4882a593Smuzhiyun uint64 temp_dividend = (dividend); \
311*4882a593Smuzhiyun uint32 rem = DIV_AND_MOD_U64_BY_U32(temp_dividend, (divisor)); \
312*4882a593Smuzhiyun rem; \
313*4882a593Smuzhiyun })
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun #define SEC_USEC_FMT \
316*4882a593Smuzhiyun "%5llu.%06u"
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun /* t: time in nano second */
319*4882a593Smuzhiyun #define GET_SEC_USEC(t) \
320*4882a593Smuzhiyun DIV_U64_BY_U32(t, NSEC_PER_SEC), \
321*4882a593Smuzhiyun ((uint32)(MOD_U64_BY_U32(t, NSEC_PER_SEC) / (uint32)NSEC_PER_USEC))
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun /* Download Types */
324*4882a593Smuzhiyun typedef enum download_type {
325*4882a593Smuzhiyun FW,
326*4882a593Smuzhiyun NVRAM,
327*4882a593Smuzhiyun CLM_BLOB,
328*4882a593Smuzhiyun TXCAP_BLOB
329*4882a593Smuzhiyun } download_type_t;
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun /* For supporting multiple interfaces */
332*4882a593Smuzhiyun #define DHD_MAX_IFS 16
333*4882a593Smuzhiyun #define DHD_MAX_STATIC_IFS 5
334*4882a593Smuzhiyun #define DHD_DEL_IF -0xE
335*4882a593Smuzhiyun #define DHD_BAD_IF -0xF
336*4882a593Smuzhiyun #define DHD_DUMMY_INFO_IF 0xDEAF /* Hack i/f to handle events from INFO Ring */
337*4882a593Smuzhiyun #define DHD_EVENT_IF DHD_DUMMY_INFO_IF
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun enum dhd_op_flags {
340*4882a593Smuzhiyun /* Firmware requested operation mode */
341*4882a593Smuzhiyun DHD_FLAG_STA_MODE = (1 << (0)), /* STA only */
342*4882a593Smuzhiyun DHD_FLAG_HOSTAP_MODE = (1 << (1)), /* SOFTAP only */
343*4882a593Smuzhiyun DHD_FLAG_P2P_MODE = (1 << (2)), /* P2P Only */
344*4882a593Smuzhiyun /* STA + P2P */
345*4882a593Smuzhiyun DHD_FLAG_CONCURR_SINGLE_CHAN_MODE = (DHD_FLAG_STA_MODE | DHD_FLAG_P2P_MODE),
346*4882a593Smuzhiyun /* STA + SoftAP */
347*4882a593Smuzhiyun DHD_FLAG_CONCURR_STA_HOSTAP_MODE = (DHD_FLAG_STA_MODE | DHD_FLAG_HOSTAP_MODE),
348*4882a593Smuzhiyun DHD_FLAG_CONCURR_MULTI_CHAN_MODE = (1 << (4)), /* STA + P2P */
349*4882a593Smuzhiyun /* Current P2P mode for P2P connection */
350*4882a593Smuzhiyun DHD_FLAG_P2P_GC_MODE = (1 << (5)),
351*4882a593Smuzhiyun DHD_FLAG_P2P_GO_MODE = (1 << (6)),
352*4882a593Smuzhiyun DHD_FLAG_MBSS_MODE = (1 << (7)), /* MBSS in future */
353*4882a593Smuzhiyun DHD_FLAG_IBSS_MODE = (1 << (8)),
354*4882a593Smuzhiyun DHD_FLAG_MFG_MODE = (1 << (9)),
355*4882a593Smuzhiyun DHD_FLAG_RSDB_MODE = (1 << (10)),
356*4882a593Smuzhiyun DHD_FLAG_MP2P_MODE = (1 << (11))
357*4882a593Smuzhiyun };
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun #define DHD_OPMODE_SUPPORTED(dhd, opmode_flag) \
360*4882a593Smuzhiyun (dhd ? ((((dhd_pub_t *)dhd)->op_mode) & opmode_flag) : -1)
361*4882a593Smuzhiyun #define DHD_OPMODE_STA_SOFTAP_CONCURR(dhd) \
362*4882a593Smuzhiyun (dhd ? (((dhd->op_mode) & DHD_FLAG_CONCURR_STA_HOSTAP_MODE) == \
363*4882a593Smuzhiyun DHD_FLAG_CONCURR_STA_HOSTAP_MODE) : 0)
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun /* Max sequential TX/RX Control timeouts to set HANG event */
366*4882a593Smuzhiyun #ifndef MAX_CNTL_TX_TIMEOUT
367*4882a593Smuzhiyun #define MAX_CNTL_TX_TIMEOUT 2
368*4882a593Smuzhiyun #endif /* MAX_CNTL_TX_TIMEOUT */
369*4882a593Smuzhiyun #ifndef MAX_CNTL_RX_TIMEOUT
370*4882a593Smuzhiyun #define MAX_CNTL_RX_TIMEOUT 1
371*4882a593Smuzhiyun #endif /* MAX_CNTL_RX_TIMEOUT */
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun #define DHD_SCAN_ASSOC_ACTIVE_TIME 40 /* ms: Embedded default Active setting from DHD */
374*4882a593Smuzhiyun #define DHD_SCAN_UNASSOC_ACTIVE_TIME 80 /* ms: Embedded def. Unassoc Active setting from DHD */
375*4882a593Smuzhiyun #define DHD_SCAN_HOME_TIME 45 /* ms: Embedded default Home time setting from DHD */
376*4882a593Smuzhiyun #define DHD_SCAN_HOME_AWAY_TIME 100 /* ms: Embedded default Home Away time setting from DHD */
377*4882a593Smuzhiyun #ifndef CUSTOM_SCAN_PASSIVE_TIME
378*4882a593Smuzhiyun #define DHD_SCAN_PASSIVE_TIME 130 /* ms: Embedded default Passive setting from DHD */
379*4882a593Smuzhiyun #else
380*4882a593Smuzhiyun #define DHD_SCAN_PASSIVE_TIME CUSTOM_SCAN_PASSIVE_TIME /* ms: Custom Passive setting from DHD */
381*4882a593Smuzhiyun #endif /* CUSTOM_SCAN_PASSIVE_TIME */
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun #ifndef POWERUP_MAX_RETRY
384*4882a593Smuzhiyun #define POWERUP_MAX_RETRY 3 /* how many times we retry to power up the chip */
385*4882a593Smuzhiyun #endif // endif
386*4882a593Smuzhiyun #ifndef POWERUP_WAIT_MS
387*4882a593Smuzhiyun #define POWERUP_WAIT_MS 2000 /* ms: time out in waiting wifi to come up */
388*4882a593Smuzhiyun #endif // endif
389*4882a593Smuzhiyun /*
390*4882a593Smuzhiyun * MAX_NVRAMBUF_SIZE determines the size of the Buffer in the DHD that holds
391*4882a593Smuzhiyun * the NVRAM data. That is the size of the buffer pointed by bus->vars
392*4882a593Smuzhiyun * This also needs to be increased to 16K to support NVRAM size higher than 8K
393*4882a593Smuzhiyun */
394*4882a593Smuzhiyun #define MAX_NVRAMBUF_SIZE (16 * 1024) /* max nvram buf size */
395*4882a593Smuzhiyun #define MAX_CLM_BUF_SIZE (48 * 1024) /* max clm blob size */
396*4882a593Smuzhiyun #define MAX_TXCAP_BUF_SIZE (16 * 1024) /* max txcap blob size */
397*4882a593Smuzhiyun #ifdef DHD_DEBUG
398*4882a593Smuzhiyun #define DHD_JOIN_MAX_TIME_DEFAULT 10000 /* ms: Max time out for joining AP */
399*4882a593Smuzhiyun #define DHD_SCAN_DEF_TIMEOUT 10000 /* ms: Max time out for scan in progress */
400*4882a593Smuzhiyun #endif /* DHD_DEBUG */
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun #ifndef CONFIG_BCMDHD_CLM_PATH
403*4882a593Smuzhiyun #ifdef OEM_ANDROID
404*4882a593Smuzhiyun #define CONFIG_BCMDHD_CLM_PATH "/etc/wifi/bcmdhd_clm.blob"
405*4882a593Smuzhiyun #else
406*4882a593Smuzhiyun #define CONFIG_BCMDHD_CLM_PATH "/var/run/bcmdhd_clm.blob"
407*4882a593Smuzhiyun #endif /* OEM_ANDROID */
408*4882a593Smuzhiyun #endif /* CONFIG_BCMDHD_CLM_PATH */
409*4882a593Smuzhiyun #define WL_CCODE_NULL_COUNTRY "#n"
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun #define FW_VER_STR_LEN 128
412*4882a593Smuzhiyun #define FWID_STR_LEN 256
413*4882a593Smuzhiyun #define CLM_VER_STR_LEN 128
414*4882a593Smuzhiyun #define BUS_API_REV_STR_LEN 128
415*4882a593Smuzhiyun #define FW_VER_STR "Version"
416*4882a593Smuzhiyun #define FWID_STR_1 "FWID: 01-"
417*4882a593Smuzhiyun #define FWID_STR_2 "FWID=01-"
418*4882a593Smuzhiyun extern char bus_api_revision[];
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun enum dhd_bus_wake_state {
421*4882a593Smuzhiyun WAKE_LOCK_OFF = 0,
422*4882a593Smuzhiyun WAKE_LOCK_PRIV = 1,
423*4882a593Smuzhiyun WAKE_LOCK_DPC = 2,
424*4882a593Smuzhiyun WAKE_LOCK_IOCTL = 3,
425*4882a593Smuzhiyun WAKE_LOCK_DOWNLOAD = 4,
426*4882a593Smuzhiyun WAKE_LOCK_TMOUT = 5,
427*4882a593Smuzhiyun WAKE_LOCK_WATCHDOG = 6,
428*4882a593Smuzhiyun WAKE_LOCK_LINK_DOWN_TMOUT = 7,
429*4882a593Smuzhiyun WAKE_LOCK_PNO_FIND_TMOUT = 8,
430*4882a593Smuzhiyun WAKE_LOCK_SOFTAP_SET = 9,
431*4882a593Smuzhiyun WAKE_LOCK_SOFTAP_STOP = 10,
432*4882a593Smuzhiyun WAKE_LOCK_SOFTAP_START = 11,
433*4882a593Smuzhiyun WAKE_LOCK_SOFTAP_THREAD = 12
434*4882a593Smuzhiyun };
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun enum dhd_prealloc_index {
437*4882a593Smuzhiyun DHD_PREALLOC_PROT = 0,
438*4882a593Smuzhiyun DHD_PREALLOC_RXBUF = 1,
439*4882a593Smuzhiyun DHD_PREALLOC_DATABUF = 2,
440*4882a593Smuzhiyun DHD_PREALLOC_OSL_BUF = 3,
441*4882a593Smuzhiyun /* 4 */
442*4882a593Smuzhiyun DHD_PREALLOC_WIPHY_ESCAN0 = 5,
443*4882a593Smuzhiyun DHD_PREALLOC_WIPHY_ESCAN1 = 6,
444*4882a593Smuzhiyun DHD_PREALLOC_DHD_INFO = 7,
445*4882a593Smuzhiyun DHD_PREALLOC_DHD_WLFC_INFO = 8,
446*4882a593Smuzhiyun DHD_PREALLOC_IF_FLOW_LKUP = 9,
447*4882a593Smuzhiyun /* 10 */
448*4882a593Smuzhiyun DHD_PREALLOC_MEMDUMP_RAM = 11,
449*4882a593Smuzhiyun DHD_PREALLOC_DHD_WLFC_HANGER = 12,
450*4882a593Smuzhiyun DHD_PREALLOC_PKTID_MAP = 13,
451*4882a593Smuzhiyun DHD_PREALLOC_PKTID_MAP_IOCTL = 14,
452*4882a593Smuzhiyun DHD_PREALLOC_DHD_LOG_DUMP_BUF = 15,
453*4882a593Smuzhiyun DHD_PREALLOC_DHD_LOG_DUMP_BUF_EX = 16,
454*4882a593Smuzhiyun DHD_PREALLOC_DHD_PKTLOG_DUMP_BUF = 17
455*4882a593Smuzhiyun };
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun enum dhd_dongledump_mode {
458*4882a593Smuzhiyun DUMP_DISABLED = 0,
459*4882a593Smuzhiyun DUMP_MEMONLY = 1,
460*4882a593Smuzhiyun DUMP_MEMFILE = 2,
461*4882a593Smuzhiyun DUMP_MEMFILE_BUGON = 3,
462*4882a593Smuzhiyun DUMP_MEMFILE_MAX = 4
463*4882a593Smuzhiyun };
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun enum dhd_dongledump_type {
466*4882a593Smuzhiyun DUMP_TYPE_RESUMED_ON_TIMEOUT = 1,
467*4882a593Smuzhiyun DUMP_TYPE_D3_ACK_TIMEOUT = 2,
468*4882a593Smuzhiyun DUMP_TYPE_DONGLE_TRAP = 3,
469*4882a593Smuzhiyun DUMP_TYPE_MEMORY_CORRUPTION = 4,
470*4882a593Smuzhiyun DUMP_TYPE_PKTID_AUDIT_FAILURE = 5,
471*4882a593Smuzhiyun DUMP_TYPE_PKTID_INVALID = 6,
472*4882a593Smuzhiyun DUMP_TYPE_SCAN_TIMEOUT = 7,
473*4882a593Smuzhiyun DUMP_TYPE_SCAN_BUSY = 8,
474*4882a593Smuzhiyun DUMP_TYPE_BY_SYSDUMP = 9,
475*4882a593Smuzhiyun DUMP_TYPE_BY_LIVELOCK = 10,
476*4882a593Smuzhiyun DUMP_TYPE_AP_LINKUP_FAILURE = 11,
477*4882a593Smuzhiyun DUMP_TYPE_AP_ABNORMAL_ACCESS = 12,
478*4882a593Smuzhiyun DUMP_TYPE_CFG_VENDOR_TRIGGERED = 13,
479*4882a593Smuzhiyun DUMP_TYPE_RESUMED_ON_TIMEOUT_TX = 14,
480*4882a593Smuzhiyun DUMP_TYPE_RESUMED_ON_TIMEOUT_RX = 15,
481*4882a593Smuzhiyun DUMP_TYPE_RESUMED_ON_INVALID_RING_RDWR = 16,
482*4882a593Smuzhiyun DUMP_TYPE_TRANS_ID_MISMATCH = 17,
483*4882a593Smuzhiyun DUMP_TYPE_IFACE_OP_FAILURE = 18,
484*4882a593Smuzhiyun DUMP_TYPE_DONGLE_INIT_FAILURE = 19,
485*4882a593Smuzhiyun DUMP_TYPE_READ_SHM_FAIL = 20,
486*4882a593Smuzhiyun DUMP_TYPE_DONGLE_HOST_EVENT = 21,
487*4882a593Smuzhiyun DUMP_TYPE_SMMU_FAULT = 22,
488*4882a593Smuzhiyun DUMP_TYPE_RESUMED_UNKNOWN = 23,
489*4882a593Smuzhiyun DUMP_TYPE_DUE_TO_BT = 24,
490*4882a593Smuzhiyun DUMP_TYPE_LOGSET_BEYOND_RANGE = 25,
491*4882a593Smuzhiyun DUMP_TYPE_BY_USER = 26,
492*4882a593Smuzhiyun DUMP_TYPE_CTO_RECOVERY = 27,
493*4882a593Smuzhiyun DUMP_TYPE_SEQUENTIAL_PRIVCMD_ERROR = 28,
494*4882a593Smuzhiyun DUMP_TYPE_PROXD_TIMEOUT = 29,
495*4882a593Smuzhiyun DUMP_TYPE_PKTID_POOL_DEPLETED = 30
496*4882a593Smuzhiyun };
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun enum dhd_hang_reason {
499*4882a593Smuzhiyun HANG_REASON_MASK = 0x8000,
500*4882a593Smuzhiyun HANG_REASON_IOCTL_RESP_TIMEOUT = 0x8001,
501*4882a593Smuzhiyun HANG_REASON_DONGLE_TRAP = 0x8002,
502*4882a593Smuzhiyun HANG_REASON_D3_ACK_TIMEOUT = 0x8003,
503*4882a593Smuzhiyun HANG_REASON_BUS_DOWN = 0x8004,
504*4882a593Smuzhiyun HANG_REASON_MSGBUF_LIVELOCK = 0x8006,
505*4882a593Smuzhiyun HANG_REASON_IFACE_DEL_FAILURE = 0x8007,
506*4882a593Smuzhiyun HANG_REASON_HT_AVAIL_ERROR = 0x8008,
507*4882a593Smuzhiyun HANG_REASON_PCIE_RC_LINK_UP_FAIL = 0x8009,
508*4882a593Smuzhiyun HANG_REASON_PCIE_PKTID_ERROR = 0x800A,
509*4882a593Smuzhiyun HANG_REASON_IFACE_ADD_FAILURE = 0x800B,
510*4882a593Smuzhiyun HANG_REASON_IOCTL_RESP_TIMEOUT_SCHED_ERROR = 0x800C,
511*4882a593Smuzhiyun HANG_REASON_D3_ACK_TIMEOUT_SCHED_ERROR = 0x800D,
512*4882a593Smuzhiyun HANG_REASON_SEQUENTIAL_PRIVCMD_ERROR = 0x800E,
513*4882a593Smuzhiyun HANG_REASON_PCIE_LINK_DOWN_RC_DETECT = 0x8805,
514*4882a593Smuzhiyun HANG_REASON_INVALID_EVENT_OR_DATA = 0x8806,
515*4882a593Smuzhiyun HANG_REASON_UNKNOWN = 0x8807,
516*4882a593Smuzhiyun HANG_REASON_PCIE_LINK_DOWN_EP_DETECT = 0x8808,
517*4882a593Smuzhiyun HANG_REASON_PCIE_CTO_DETECT = 0x8809,
518*4882a593Smuzhiyun HANG_REASON_MAX = 0x880A
519*4882a593Smuzhiyun };
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun #define WLC_E_DEAUTH_MAX_REASON 0x0FFF
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun enum dhd_rsdb_scan_features {
524*4882a593Smuzhiyun /* Downgraded scan feature for AP active */
525*4882a593Smuzhiyun RSDB_SCAN_DOWNGRADED_AP_SCAN = 0x01,
526*4882a593Smuzhiyun /* Downgraded scan feature for P2P Discovery */
527*4882a593Smuzhiyun RSDB_SCAN_DOWNGRADED_P2P_DISC_SCAN = 0x02,
528*4882a593Smuzhiyun /* Enable channel pruning for ROAM SCAN */
529*4882a593Smuzhiyun RSDB_SCAN_DOWNGRADED_CH_PRUNE_ROAM = 0x10,
530*4882a593Smuzhiyun /* Enable channel pruning for any SCAN */
531*4882a593Smuzhiyun RSDB_SCAN_DOWNGRADED_CH_PRUNE_ALL = 0x20
532*4882a593Smuzhiyun };
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun #define VENDOR_SEND_HANG_EXT_INFO_LEN (800 + 1)
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun #ifdef DHD_EWPR_VER2
537*4882a593Smuzhiyun #define VENDOR_SEND_HANG_EXT_INFO_VER 20181111
538*4882a593Smuzhiyun #else
539*4882a593Smuzhiyun #define VENDOR_SEND_HANG_EXT_INFO_VER 20170905
540*4882a593Smuzhiyun #endif // endif
541*4882a593Smuzhiyun
542*4882a593Smuzhiyun #define HANG_INFO_TRAP_T_NAME_MAX 6
543*4882a593Smuzhiyun #define HANG_INFO_TRAP_T_REASON_IDX 0
544*4882a593Smuzhiyun #define HANG_INFO_TRAP_T_SUBTYPE_IDX 2
545*4882a593Smuzhiyun #define HANG_INFO_TRAP_T_OFFSET_IDX 3
546*4882a593Smuzhiyun #define HANG_INFO_TRAP_T_EPC_IDX 4
547*4882a593Smuzhiyun #define HANG_FIELD_STR_MAX_LEN 9
548*4882a593Smuzhiyun #define HANG_FIELD_CNT_MAX 69
549*4882a593Smuzhiyun #define HANG_FIELD_IF_FAILURE_CNT 10
550*4882a593Smuzhiyun #define HANG_FIELD_IOCTL_RESP_TIMEOUT_CNT 8
551*4882a593Smuzhiyun #define HANG_FIELD_TRAP_T_STACK_CNT_MAX 16
552*4882a593Smuzhiyun #define HANG_FIELD_MISMATCH_CNT 10
553*4882a593Smuzhiyun #define HANG_INFO_BIGDATA_KEY_STACK_CNT 4
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun #define DEBUG_DUMP_TIME_BUF_LEN (16 + 1)
556*4882a593Smuzhiyun /* delimiter between values */
557*4882a593Smuzhiyun #define HANG_KEY_DEL ' '
558*4882a593Smuzhiyun #define HANG_RAW_DEL '_'
559*4882a593Smuzhiyun
560*4882a593Smuzhiyun #ifdef DHD_EWPR_VER2
561*4882a593Smuzhiyun #define HANG_INFO_BIGDATA_EXTRA_KEY 4
562*4882a593Smuzhiyun #define HANG_INFO_TRAP_T_EXTRA_KEY_IDX 5
563*4882a593Smuzhiyun #endif // endif
564*4882a593Smuzhiyun
565*4882a593Smuzhiyun /* Packet alignment for most efficient SDIO (can change based on platform) */
566*4882a593Smuzhiyun #ifndef DHD_SDALIGN
567*4882a593Smuzhiyun #if defined(BCMSPI)
568*4882a593Smuzhiyun #define DHD_SDALIGN 4
569*4882a593Smuzhiyun #else
570*4882a593Smuzhiyun #define DHD_SDALIGN 32
571*4882a593Smuzhiyun #endif /* BCMSPI */
572*4882a593Smuzhiyun #endif /* !DHD_SDALIGN */
573*4882a593Smuzhiyun
574*4882a593Smuzhiyun #define DHD_TX_CONTEXT_MASK 0xff
575*4882a593Smuzhiyun #define DHD_TX_START_XMIT 0x01
576*4882a593Smuzhiyun #define DHD_TX_SEND_PKT 0x02
577*4882a593Smuzhiyun #define DHD_IF_SET_TX_ACTIVE(ifp, context) \
578*4882a593Smuzhiyun ifp->tx_paths_active |= context;
579*4882a593Smuzhiyun #define DHD_IF_CLR_TX_ACTIVE(ifp, context) \
580*4882a593Smuzhiyun ifp->tx_paths_active &= ~context;
581*4882a593Smuzhiyun #define DHD_IF_IS_TX_ACTIVE(ifp) \
582*4882a593Smuzhiyun (ifp->tx_paths_active)
583*4882a593Smuzhiyun /**
584*4882a593Smuzhiyun * DMA-able buffer parameters
585*4882a593Smuzhiyun * - dmaaddr_t is 32bits on a 32bit host.
586*4882a593Smuzhiyun * dhd_dma_buf::pa may not be used as a sh_addr_t, bcm_addr64_t or uintptr
587*4882a593Smuzhiyun * - dhd_dma_buf::_alloced is ONLY for freeing a DMA-able buffer.
588*4882a593Smuzhiyun */
589*4882a593Smuzhiyun typedef struct dhd_dma_buf {
590*4882a593Smuzhiyun void *va; /* virtual address of buffer */
591*4882a593Smuzhiyun uint32 len; /* user requested buffer length */
592*4882a593Smuzhiyun dmaaddr_t pa; /* physical address of buffer */
593*4882a593Smuzhiyun void *dmah; /* dma mapper handle */
594*4882a593Smuzhiyun void *secdma; /* secure dma sec_cma_info handle */
595*4882a593Smuzhiyun uint32 _alloced; /* actual size of buffer allocated with align and pad */
596*4882a593Smuzhiyun } dhd_dma_buf_t;
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun /* host reordering packts logic */
599*4882a593Smuzhiyun /* followed the structure to hold the reorder buffers (void **p) */
600*4882a593Smuzhiyun typedef struct reorder_info {
601*4882a593Smuzhiyun void **p;
602*4882a593Smuzhiyun uint8 flow_id;
603*4882a593Smuzhiyun uint8 cur_idx;
604*4882a593Smuzhiyun uint8 exp_idx;
605*4882a593Smuzhiyun uint8 max_idx;
606*4882a593Smuzhiyun uint8 pend_pkts;
607*4882a593Smuzhiyun } reorder_info_t;
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun /* throughput test packet format */
610*4882a593Smuzhiyun typedef struct tput_pkt {
611*4882a593Smuzhiyun /* header */
612*4882a593Smuzhiyun uint8 mac_sta[ETHER_ADDR_LEN];
613*4882a593Smuzhiyun uint8 mac_ap[ETHER_ADDR_LEN];
614*4882a593Smuzhiyun uint16 pkt_type;
615*4882a593Smuzhiyun uint8 PAD[2];
616*4882a593Smuzhiyun /* data */
617*4882a593Smuzhiyun uint32 crc32;
618*4882a593Smuzhiyun uint32 pkt_id;
619*4882a593Smuzhiyun uint32 num_pkts;
620*4882a593Smuzhiyun } tput_pkt_t;
621*4882a593Smuzhiyun
622*4882a593Smuzhiyun typedef enum {
623*4882a593Smuzhiyun TPUT_PKT_TYPE_NORMAL,
624*4882a593Smuzhiyun TPUT_PKT_TYPE_STOP
625*4882a593Smuzhiyun } tput_pkt_type_t;
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun #define TPUT_TEST_MAX_PAYLOAD 1500
628*4882a593Smuzhiyun #define TPUT_TEST_WAIT_TIMEOUT_DEFAULT 5000
629*4882a593Smuzhiyun
630*4882a593Smuzhiyun #ifdef DHDTCPACK_SUPPRESS
631*4882a593Smuzhiyun
632*4882a593Smuzhiyun enum {
633*4882a593Smuzhiyun /* TCPACK suppress off */
634*4882a593Smuzhiyun TCPACK_SUP_OFF,
635*4882a593Smuzhiyun /* Replace TCPACK in txq when new coming one has higher ACK number. */
636*4882a593Smuzhiyun TCPACK_SUP_REPLACE,
637*4882a593Smuzhiyun /* TCPACK_SUP_REPLACE + delayed TCPACK TX unless ACK to PSH DATA.
638*4882a593Smuzhiyun * This will give benefits to Half-Duplex bus interface(e.g. SDIO) that
639*4882a593Smuzhiyun * 1. we are able to read TCP DATA packets first from the bus
640*4882a593Smuzhiyun * 2. TCPACKs that don't need to hurry delivered remains longer in TXQ so can be suppressed.
641*4882a593Smuzhiyun */
642*4882a593Smuzhiyun TCPACK_SUP_DELAYTX,
643*4882a593Smuzhiyun TCPACK_SUP_HOLD,
644*4882a593Smuzhiyun TCPACK_SUP_LAST_MODE
645*4882a593Smuzhiyun };
646*4882a593Smuzhiyun #endif /* DHDTCPACK_SUPPRESS */
647*4882a593Smuzhiyun
648*4882a593Smuzhiyun #define DHD_NULL_CHK_AND_RET(cond) \
649*4882a593Smuzhiyun if (!cond) { \
650*4882a593Smuzhiyun DHD_ERROR(("%s " #cond " is NULL\n", __FUNCTION__)); \
651*4882a593Smuzhiyun return; \
652*4882a593Smuzhiyun }
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun #define DHD_NULL_CHK_AND_RET_VAL(cond, value) \
655*4882a593Smuzhiyun if (!cond) { \
656*4882a593Smuzhiyun DHD_ERROR(("%s " #cond " is NULL\n", __FUNCTION__)); \
657*4882a593Smuzhiyun return value; \
658*4882a593Smuzhiyun }
659*4882a593Smuzhiyun
660*4882a593Smuzhiyun #define DHD_NULL_CHK_AND_GOTO(cond, label) \
661*4882a593Smuzhiyun if (!cond) { \
662*4882a593Smuzhiyun DHD_ERROR(("%s " #cond " is NULL\n", __FUNCTION__)); \
663*4882a593Smuzhiyun goto label; \
664*4882a593Smuzhiyun }
665*4882a593Smuzhiyun
666*4882a593Smuzhiyun /*
667*4882a593Smuzhiyun * Accumulating the queue lengths of all flowring queues in a parent object,
668*4882a593Smuzhiyun * to assert flow control, when the cummulative queue length crosses an upper
669*4882a593Smuzhiyun * threshold defined on a parent object. Upper threshold may be maintained
670*4882a593Smuzhiyun * at a station level, at an interface level, or at a dhd instance.
671*4882a593Smuzhiyun *
672*4882a593Smuzhiyun * cumm_ctr_t abstraction:
673*4882a593Smuzhiyun * cumm_ctr_t abstraction may be enhanced to use an object with a hysterisis
674*4882a593Smuzhiyun * pause on/off threshold callback.
675*4882a593Smuzhiyun * All macros use the address of the cummulative length in the parent objects.
676*4882a593Smuzhiyun *
677*4882a593Smuzhiyun * BCM_GMAC3 builds use a single perimeter lock, as opposed to a per queue lock.
678*4882a593Smuzhiyun * Cummulative counters in parent objects may be updated without spinlocks.
679*4882a593Smuzhiyun *
680*4882a593Smuzhiyun * In non BCM_GMAC3, if a cummulative queue length is desired across all flows
681*4882a593Smuzhiyun * belonging to either of (a station, or an interface or a dhd instance), then
682*4882a593Smuzhiyun * an atomic operation is required using an atomic_t cummulative counters or
683*4882a593Smuzhiyun * using a spinlock. BCM_ROUTER_DHD uses the Linux atomic_t construct.
684*4882a593Smuzhiyun */
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun /* Cummulative length not supported. */
687*4882a593Smuzhiyun typedef uint32 cumm_ctr_t;
688*4882a593Smuzhiyun #define DHD_CUMM_CTR_PTR(clen) ((cumm_ctr_t*)(clen))
689*4882a593Smuzhiyun #define DHD_CUMM_CTR(clen) *(DHD_CUMM_CTR_PTR(clen)) /* accessor */
690*4882a593Smuzhiyun #define DHD_CUMM_CTR_READ(clen) DHD_CUMM_CTR(clen) /* read access */
691*4882a593Smuzhiyun #define DHD_CUMM_CTR_INIT(clen) \
692*4882a593Smuzhiyun ASSERT(DHD_CUMM_CTR_PTR(clen) != DHD_CUMM_CTR_PTR(NULL));
693*4882a593Smuzhiyun #define DHD_CUMM_CTR_INCR(clen) \
694*4882a593Smuzhiyun ASSERT(DHD_CUMM_CTR_PTR(clen) != DHD_CUMM_CTR_PTR(NULL));
695*4882a593Smuzhiyun #define DHD_CUMM_CTR_DECR(clen) \
696*4882a593Smuzhiyun ASSERT(DHD_CUMM_CTR_PTR(clen) != DHD_CUMM_CTR_PTR(NULL));
697*4882a593Smuzhiyun
698*4882a593Smuzhiyun #if defined(WLTDLS) && defined(PCIE_FULL_DONGLE)
699*4882a593Smuzhiyun struct tdls_peer_node {
700*4882a593Smuzhiyun uint8 addr[ETHER_ADDR_LEN];
701*4882a593Smuzhiyun struct tdls_peer_node *next;
702*4882a593Smuzhiyun };
703*4882a593Smuzhiyun typedef struct tdls_peer_node tdls_peer_node_t;
704*4882a593Smuzhiyun typedef struct {
705*4882a593Smuzhiyun tdls_peer_node_t *node;
706*4882a593Smuzhiyun uint8 tdls_peer_count;
707*4882a593Smuzhiyun } tdls_peer_tbl_t;
708*4882a593Smuzhiyun #endif /* defined(WLTDLS) && defined(PCIE_FULL_DONGLE) */
709*4882a593Smuzhiyun
710*4882a593Smuzhiyun #ifdef DHD_LOG_DUMP
711*4882a593Smuzhiyun #define DUMP_SSSR_ATTR_START 2
712*4882a593Smuzhiyun #define DUMP_SSSR_ATTR_COUNT 6
713*4882a593Smuzhiyun
714*4882a593Smuzhiyun typedef enum {
715*4882a593Smuzhiyun SSSR_C0_D11_BEFORE = 0,
716*4882a593Smuzhiyun SSSR_C0_D11_AFTER = 1,
717*4882a593Smuzhiyun SSSR_C1_D11_BEFORE = 2,
718*4882a593Smuzhiyun SSSR_C1_D11_AFTER = 3,
719*4882a593Smuzhiyun SSSR_DIG_BEFORE = 4,
720*4882a593Smuzhiyun SSSR_DIG_AFTER = 5
721*4882a593Smuzhiyun } EWP_SSSR_DUMP;
722*4882a593Smuzhiyun
723*4882a593Smuzhiyun typedef enum {
724*4882a593Smuzhiyun DLD_BUF_TYPE_GENERAL = 0,
725*4882a593Smuzhiyun DLD_BUF_TYPE_PRESERVE = 1,
726*4882a593Smuzhiyun DLD_BUF_TYPE_SPECIAL = 2,
727*4882a593Smuzhiyun DLD_BUF_TYPE_ECNTRS = 3,
728*4882a593Smuzhiyun DLD_BUF_TYPE_FILTER = 4,
729*4882a593Smuzhiyun DLD_BUF_TYPE_ALL = 5
730*4882a593Smuzhiyun } log_dump_type_t;
731*4882a593Smuzhiyun
732*4882a593Smuzhiyun #define LOG_DUMP_MAGIC 0xDEB3DEB3
733*4882a593Smuzhiyun #define HEALTH_CHK_BUF_SIZE 256
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun #ifdef EWP_ECNTRS_LOGGING
736*4882a593Smuzhiyun #define ECNTR_RING_ID 0xECDB
737*4882a593Smuzhiyun #define ECNTR_RING_NAME "ewp_ecntr_ring"
738*4882a593Smuzhiyun #endif /* EWP_ECNTRS_LOGGING */
739*4882a593Smuzhiyun
740*4882a593Smuzhiyun #ifdef EWP_RTT_LOGGING
741*4882a593Smuzhiyun #define RTT_RING_ID 0xADCD
742*4882a593Smuzhiyun #define RTT_RING_NAME "ewp_rtt_ring"
743*4882a593Smuzhiyun #endif /* EWP_ECNTRS_LOGGING */
744*4882a593Smuzhiyun
745*4882a593Smuzhiyun #if defined(DEBUGABILITY) && defined(EWP_ECNTRS_LOGGING)
746*4882a593Smuzhiyun #error "Duplicate rings will be created since both the features are enabled"
747*4882a593Smuzhiyun #endif /* DEBUGABILITY && EWP_ECNTRS_LOGGING */
748*4882a593Smuzhiyun
749*4882a593Smuzhiyun typedef enum {
750*4882a593Smuzhiyun LOG_DUMP_SECTION_GENERAL = 0,
751*4882a593Smuzhiyun LOG_DUMP_SECTION_ECNTRS,
752*4882a593Smuzhiyun LOG_DUMP_SECTION_SPECIAL,
753*4882a593Smuzhiyun LOG_DUMP_SECTION_DHD_DUMP,
754*4882a593Smuzhiyun LOG_DUMP_SECTION_EXT_TRAP,
755*4882a593Smuzhiyun LOG_DUMP_SECTION_HEALTH_CHK,
756*4882a593Smuzhiyun LOG_DUMP_SECTION_PRESERVE,
757*4882a593Smuzhiyun LOG_DUMP_SECTION_COOKIE,
758*4882a593Smuzhiyun LOG_DUMP_SECTION_FLOWRING,
759*4882a593Smuzhiyun LOG_DUMP_SECTION_STATUS,
760*4882a593Smuzhiyun LOG_DUMP_SECTION_RTT
761*4882a593Smuzhiyun } log_dump_section_type_t;
762*4882a593Smuzhiyun
763*4882a593Smuzhiyun /* Each section in the debug_dump log file shall begin with a header */
764*4882a593Smuzhiyun typedef struct {
765*4882a593Smuzhiyun uint32 magic; /* 0xDEB3DEB3 */
766*4882a593Smuzhiyun uint32 type; /* of type log_dump_section_type_t */
767*4882a593Smuzhiyun uint64 timestamp;
768*4882a593Smuzhiyun uint32 length; /* length of the section that follows */
769*4882a593Smuzhiyun uint32 pad;
770*4882a593Smuzhiyun } log_dump_section_hdr_t;
771*4882a593Smuzhiyun
772*4882a593Smuzhiyun /* below structure describe ring buffer. */
773*4882a593Smuzhiyun struct dhd_log_dump_buf
774*4882a593Smuzhiyun {
775*4882a593Smuzhiyun spinlock_t lock;
776*4882a593Smuzhiyun void *dhd_pub;
777*4882a593Smuzhiyun unsigned int enable;
778*4882a593Smuzhiyun unsigned int wraparound;
779*4882a593Smuzhiyun unsigned long max;
780*4882a593Smuzhiyun unsigned int remain;
781*4882a593Smuzhiyun char* present;
782*4882a593Smuzhiyun char* front;
783*4882a593Smuzhiyun char* buffer;
784*4882a593Smuzhiyun };
785*4882a593Smuzhiyun
786*4882a593Smuzhiyun #define DHD_LOG_DUMP_MAX_TEMP_BUFFER_SIZE 256
787*4882a593Smuzhiyun #define DHD_LOG_DUMP_MAX_TAIL_FLUSH_SIZE (80 * 1024)
788*4882a593Smuzhiyun
789*4882a593Smuzhiyun extern void dhd_log_dump_write(int type, char *binary_data,
790*4882a593Smuzhiyun int binary_len, const char *fmt, ...);
791*4882a593Smuzhiyun #endif /* DHD_LOG_DUMP */
792*4882a593Smuzhiyun
793*4882a593Smuzhiyun /* DEBUG_DUMP SUB COMMAND */
794*4882a593Smuzhiyun enum {
795*4882a593Smuzhiyun CMD_DEFAULT,
796*4882a593Smuzhiyun CMD_UNWANTED,
797*4882a593Smuzhiyun CMD_DISCONNECTED,
798*4882a593Smuzhiyun CMD_MAX
799*4882a593Smuzhiyun };
800*4882a593Smuzhiyun
801*4882a593Smuzhiyun #define DHD_LOG_DUMP_TS_MULTIPLIER_VALUE 60
802*4882a593Smuzhiyun #define DHD_LOG_DUMP_TS_FMT_YYMMDDHHMMSSMSMS "%02d%02d%02d%02d%02d%02d%04d"
803*4882a593Smuzhiyun #define DHD_DEBUG_DUMP_TYPE "debug_dump_FORUSER"
804*4882a593Smuzhiyun #define DHD_DUMP_SUBSTR_UNWANTED "_unwanted"
805*4882a593Smuzhiyun #define DHD_DUMP_SUBSTR_DISCONNECTED "_disconnected"
806*4882a593Smuzhiyun
807*4882a593Smuzhiyun #ifdef DNGL_AXI_ERROR_LOGGING
808*4882a593Smuzhiyun #define DHD_DUMP_AXI_ERROR_FILENAME "axi_error"
809*4882a593Smuzhiyun #define DHD_DUMP_HAL_FILENAME_SUFFIX "_hal"
810*4882a593Smuzhiyun #endif /* DNGL_AXI_ERROR_LOGGING */
811*4882a593Smuzhiyun
812*4882a593Smuzhiyun extern void get_debug_dump_time(char *str);
813*4882a593Smuzhiyun extern void clear_debug_dump_time(char *str);
814*4882a593Smuzhiyun #if defined(WL_CFGVENDOR_SEND_HANG_EVENT) || defined(DHD_PKT_LOGGING)
815*4882a593Smuzhiyun extern void copy_debug_dump_time(char *dest, char *src);
816*4882a593Smuzhiyun #endif /* WL_CFGVENDOR_SEND_HANG_EVENT || DHD_PKT_LOGGING */
817*4882a593Smuzhiyun
818*4882a593Smuzhiyun #define FW_LOGSET_MASK_ALL 0xFF
819*4882a593Smuzhiyun
820*4882a593Smuzhiyun #ifdef WL_MONITOR
821*4882a593Smuzhiyun #define MONPKT_EXTRA_LEN 48u
822*4882a593Smuzhiyun #endif /* WL_MONITOR */
823*4882a593Smuzhiyun
824*4882a593Smuzhiyun #define DHDIF_FWDER(dhdif) FALSE
825*4882a593Smuzhiyun
826*4882a593Smuzhiyun #if defined(CUSTOMER_HW2) || defined(BOARD_HIKEY)
827*4882a593Smuzhiyun #define DHD_COMMON_DUMP_PATH "/data/misc/wifi/"
828*4882a593Smuzhiyun #elif defined(OEM_ANDROID) && defined(CONFIG_DHD_PLAT_ROCKCHIP)
829*4882a593Smuzhiyun #define DHD_COMMON_DUMP_PATH "/data/misc/wifi/"
830*4882a593Smuzhiyun #elif defined(OEM_ANDROID) && (defined(BOARD_PANDA) || defined(__ARM_ARCH_7A__))
831*4882a593Smuzhiyun #define DHD_COMMON_DUMP_PATH "/data/vendor/wifi/"
832*4882a593Smuzhiyun #elif defined(OEM_ANDROID) /* For Brix Live Image */
833*4882a593Smuzhiyun #define DHD_COMMON_DUMP_PATH "/installmedia/"
834*4882a593Smuzhiyun #else /* Default */
835*4882a593Smuzhiyun #define DHD_COMMON_DUMP_PATH "/root/"
836*4882a593Smuzhiyun #endif // endif
837*4882a593Smuzhiyun
838*4882a593Smuzhiyun struct cntry_locales_custom {
839*4882a593Smuzhiyun char iso_abbrev[WLC_CNTRY_BUF_SZ]; /* ISO 3166-1 country abbreviation */
840*4882a593Smuzhiyun char custom_locale[WLC_CNTRY_BUF_SZ]; /* Custom firmware locale */
841*4882a593Smuzhiyun int32 custom_locale_rev; /* Custom local revisin default -1 */
842*4882a593Smuzhiyun };
843*4882a593Smuzhiyun
844*4882a593Smuzhiyun int dhd_send_msg_to_daemon(struct sk_buff *skb, void *data, int size);
845*4882a593Smuzhiyun
846*4882a593Smuzhiyun #ifdef DMAMAP_STATS
847*4882a593Smuzhiyun typedef struct dmamap_stats {
848*4882a593Smuzhiyun uint64 txdata;
849*4882a593Smuzhiyun uint64 txdata_sz;
850*4882a593Smuzhiyun uint64 rxdata;
851*4882a593Smuzhiyun uint64 rxdata_sz;
852*4882a593Smuzhiyun uint64 ioctl_rx;
853*4882a593Smuzhiyun uint64 ioctl_rx_sz;
854*4882a593Smuzhiyun uint64 event_rx;
855*4882a593Smuzhiyun uint64 event_rx_sz;
856*4882a593Smuzhiyun uint64 info_rx;
857*4882a593Smuzhiyun uint64 info_rx_sz;
858*4882a593Smuzhiyun uint64 tsbuf_rx;
859*4882a593Smuzhiyun uint64 tsbuf_rx_sz;
860*4882a593Smuzhiyun } dma_stats_t;
861*4882a593Smuzhiyun #endif /* DMAMAP_STATS */
862*4882a593Smuzhiyun
863*4882a593Smuzhiyun /* see wlfc_proto.h for tx status details */
864*4882a593Smuzhiyun #define DHD_MAX_TX_STATUS_MSGS 9u
865*4882a593Smuzhiyun
866*4882a593Smuzhiyun #ifdef TX_STATUS_LATENCY_STATS
867*4882a593Smuzhiyun typedef struct dhd_if_tx_status_latency {
868*4882a593Smuzhiyun /* total number of tx_status received on this interface */
869*4882a593Smuzhiyun uint64 num_tx_status;
870*4882a593Smuzhiyun /* cumulative tx_status latency for this interface */
871*4882a593Smuzhiyun uint64 cum_tx_status_latency;
872*4882a593Smuzhiyun } dhd_if_tx_status_latency_t;
873*4882a593Smuzhiyun #endif /* TX_STATUS_LATENCY_STATS */
874*4882a593Smuzhiyun
875*4882a593Smuzhiyun #if defined(SHOW_LOGTRACE) && defined(DHD_USE_KTHREAD_FOR_LOGTRACE)
876*4882a593Smuzhiyun /* Timestamps to trace dhd_logtrace_thread() */
877*4882a593Smuzhiyun struct dhd_logtrace_thr_ts {
878*4882a593Smuzhiyun uint64 entry_time;
879*4882a593Smuzhiyun uint64 sem_down_time;
880*4882a593Smuzhiyun uint64 flush_time;
881*4882a593Smuzhiyun uint64 unexpected_break_time;
882*4882a593Smuzhiyun uint64 complete_time;
883*4882a593Smuzhiyun };
884*4882a593Smuzhiyun #endif /* SHOW_LOGTRACE && DHD_USE_KTHREAD_FOR_LOGTRACE */
885*4882a593Smuzhiyun
886*4882a593Smuzhiyun /* Enable Reserve STA flowrings only for Android */
887*4882a593Smuzhiyun #if defined(OEM_ANDROID)
888*4882a593Smuzhiyun #define DHD_LIMIT_MULTI_CLIENT_FLOWRINGS
889*4882a593Smuzhiyun #endif /* OEM_ANDROID */
890*4882a593Smuzhiyun
891*4882a593Smuzhiyun typedef enum dhd_induce_error_states
892*4882a593Smuzhiyun {
893*4882a593Smuzhiyun DHD_INDUCE_ERROR_CLEAR = 0x0,
894*4882a593Smuzhiyun DHD_INDUCE_IOCTL_TIMEOUT = 0x1,
895*4882a593Smuzhiyun DHD_INDUCE_D3_ACK_TIMEOUT = 0x2,
896*4882a593Smuzhiyun DHD_INDUCE_LIVELOCK = 0x3,
897*4882a593Smuzhiyun DHD_INDUCE_DROP_OOB_IRQ = 0x4,
898*4882a593Smuzhiyun DHD_INDUCE_DROP_AXI_SIG = 0x5,
899*4882a593Smuzhiyun DHD_INDUCE_ERROR_MAX = 0x6
900*4882a593Smuzhiyun } dhd_induce_error_states_t;
901*4882a593Smuzhiyun
902*4882a593Smuzhiyun #ifdef DHD_HP2P
903*4882a593Smuzhiyun #define MAX_TX_HIST_BIN 16
904*4882a593Smuzhiyun #define MAX_RX_HIST_BIN 10
905*4882a593Smuzhiyun #define MAX_HP2P_FLOWS 16
906*4882a593Smuzhiyun #define HP2P_PRIO 7
907*4882a593Smuzhiyun #define HP2P_PKT_THRESH 48
908*4882a593Smuzhiyun #define HP2P_TIME_THRESH 200
909*4882a593Smuzhiyun #define HP2P_PKT_EXPIRY 40
910*4882a593Smuzhiyun #define HP2P_TIME_SCALE 32
911*4882a593Smuzhiyun
912*4882a593Smuzhiyun typedef struct hp2p_info {
913*4882a593Smuzhiyun void *dhd_pub;
914*4882a593Smuzhiyun uint16 flowid;
915*4882a593Smuzhiyun bool hrtimer_init;
916*4882a593Smuzhiyun void *ring;
917*4882a593Smuzhiyun #if (LINUX_VERSION_CODE <= KERNEL_VERSION(5, 1, 21))
918*4882a593Smuzhiyun struct tasklet_hrtimer timer;
919*4882a593Smuzhiyun #else
920*4882a593Smuzhiyun struct hrtimer timer;
921*4882a593Smuzhiyun #endif /* (LINUX_VERSION_CODE <= KERNEL_VERSION(5, 1, 21) */
922*4882a593Smuzhiyun uint64 num_pkt_limit;
923*4882a593Smuzhiyun uint64 num_timer_limit;
924*4882a593Smuzhiyun uint64 num_timer_start;
925*4882a593Smuzhiyun uint64 tx_t0[MAX_TX_HIST_BIN];
926*4882a593Smuzhiyun uint64 tx_t1[MAX_TX_HIST_BIN];
927*4882a593Smuzhiyun uint64 rx_t0[MAX_RX_HIST_BIN];
928*4882a593Smuzhiyun } hp2p_info_t;
929*4882a593Smuzhiyun #endif /* DHD_HP2P */
930*4882a593Smuzhiyun
931*4882a593Smuzhiyun typedef enum {
932*4882a593Smuzhiyun FW_UNLOADED = 0,
933*4882a593Smuzhiyun FW_DOWNLOAD_IN_PROGRESS = 1,
934*4882a593Smuzhiyun FW_DOWNLOAD_DONE = 2
935*4882a593Smuzhiyun } fw_download_status_t;
936*4882a593Smuzhiyun
937*4882a593Smuzhiyun /**
938*4882a593Smuzhiyun * Common structure for module and instance linkage.
939*4882a593Smuzhiyun * Instantiated once per hardware (dongle) instance that this DHD manages.
940*4882a593Smuzhiyun */
941*4882a593Smuzhiyun typedef struct dhd_pub {
942*4882a593Smuzhiyun /* Linkage ponters */
943*4882a593Smuzhiyun osl_t *osh; /* OSL handle */
944*4882a593Smuzhiyun struct dhd_bus *bus; /* Bus module handle */
945*4882a593Smuzhiyun struct dhd_prot *prot; /* Protocol module handle */
946*4882a593Smuzhiyun struct dhd_info *info; /* Info module handle */
947*4882a593Smuzhiyun struct dhd_dbg *dbg; /* Debugability module handle */
948*4882a593Smuzhiyun #if defined(SHOW_LOGTRACE) && defined(DHD_USE_KTHREAD_FOR_LOGTRACE)
949*4882a593Smuzhiyun struct dhd_logtrace_thr_ts logtrace_thr_ts;
950*4882a593Smuzhiyun #endif /* SHOW_LOGTRACE && DHD_USE_KTHREAD_FOR_LOGTRACE */
951*4882a593Smuzhiyun
952*4882a593Smuzhiyun /* to NDIS developer, the structure dhd_common is redundant,
953*4882a593Smuzhiyun * please do NOT merge it back from other branches !!!
954*4882a593Smuzhiyun */
955*4882a593Smuzhiyun
956*4882a593Smuzhiyun /* Internal dhd items */
957*4882a593Smuzhiyun bool up; /* Driver up/down (to OS) */
958*4882a593Smuzhiyun #ifdef WL_CFG80211
959*4882a593Smuzhiyun spinlock_t up_lock; /* Synchronization with CFG80211 down */
960*4882a593Smuzhiyun #endif /* WL_CFG80211 */
961*4882a593Smuzhiyun bool txoff; /* Transmit flow-controlled */
962*4882a593Smuzhiyun bool dongle_reset; /* TRUE = DEVRESET put dongle into reset */
963*4882a593Smuzhiyun enum dhd_bus_state busstate;
964*4882a593Smuzhiyun uint dhd_bus_busy_state; /* Bus busy state */
965*4882a593Smuzhiyun uint hdrlen; /* Total DHD header length (proto + bus) */
966*4882a593Smuzhiyun uint maxctl; /* Max size rxctl request from proto to bus */
967*4882a593Smuzhiyun uint rxsz; /* Rx buffer size bus module should use */
968*4882a593Smuzhiyun uint8 wme_dp; /* wme discard priority */
969*4882a593Smuzhiyun #ifdef DNGL_AXI_ERROR_LOGGING
970*4882a593Smuzhiyun uint32 axierror_logbuf_addr;
971*4882a593Smuzhiyun bool axi_error;
972*4882a593Smuzhiyun struct dhd_axi_error_dump *axi_err_dump;
973*4882a593Smuzhiyun #endif /* DNGL_AXI_ERROR_LOGGING */
974*4882a593Smuzhiyun /* Dongle media info */
975*4882a593Smuzhiyun bool iswl; /* Dongle-resident driver is wl */
976*4882a593Smuzhiyun ulong drv_version; /* Version of dongle-resident driver */
977*4882a593Smuzhiyun struct ether_addr mac; /* MAC address obtained from dongle */
978*4882a593Smuzhiyun dngl_stats_t dstats; /* Stats for dongle-based data */
979*4882a593Smuzhiyun
980*4882a593Smuzhiyun /* Additional stats for the bus level */
981*4882a593Smuzhiyun ulong tx_packets; /* Data packets sent to dongle */
982*4882a593Smuzhiyun ulong tx_dropped; /* Data packets dropped in dhd */
983*4882a593Smuzhiyun ulong tx_multicast; /* Multicast data packets sent to dongle */
984*4882a593Smuzhiyun ulong tx_errors; /* Errors in sending data to dongle */
985*4882a593Smuzhiyun ulong tx_ctlpkts; /* Control packets sent to dongle */
986*4882a593Smuzhiyun ulong tx_ctlerrs; /* Errors sending control frames to dongle */
987*4882a593Smuzhiyun ulong rx_packets; /* Packets sent up the network interface */
988*4882a593Smuzhiyun ulong rx_multicast; /* Multicast packets sent up the network interface */
989*4882a593Smuzhiyun ulong rx_errors; /* Errors processing rx data packets */
990*4882a593Smuzhiyun ulong rx_ctlpkts; /* Control frames processed from dongle */
991*4882a593Smuzhiyun ulong rx_ctlerrs; /* Errors in processing rx control frames */
992*4882a593Smuzhiyun ulong rx_dropped; /* Packets dropped locally (no memory) */
993*4882a593Smuzhiyun ulong rx_flushed; /* Packets flushed due to unscheduled sendup thread */
994*4882a593Smuzhiyun ulong wd_dpc_sched; /* Number of times dhd dpc scheduled by watchdog timer */
995*4882a593Smuzhiyun ulong rx_pktgetfail; /* Number of PKTGET failures in DHD on RX */
996*4882a593Smuzhiyun ulong tx_pktgetfail; /* Number of PKTGET failures in DHD on TX */
997*4882a593Smuzhiyun ulong rx_readahead_cnt; /* Number of packets where header read-ahead was used. */
998*4882a593Smuzhiyun ulong tx_realloc; /* Number of tx packets we had to realloc for headroom */
999*4882a593Smuzhiyun ulong fc_packets; /* Number of flow control pkts recvd */
1000*4882a593Smuzhiyun ulong tx_big_packets; /* Dropped data packets that are larger than MAX_MTU_SZ */
1001*4882a593Smuzhiyun #ifdef DMAMAP_STATS
1002*4882a593Smuzhiyun /* DMA Mapping statistics */
1003*4882a593Smuzhiyun dma_stats_t dma_stats;
1004*4882a593Smuzhiyun #endif /* DMAMAP_STATS */
1005*4882a593Smuzhiyun
1006*4882a593Smuzhiyun /* Last error return */
1007*4882a593Smuzhiyun int bcmerror;
1008*4882a593Smuzhiyun uint tickcnt;
1009*4882a593Smuzhiyun
1010*4882a593Smuzhiyun /* Last error from dongle */
1011*4882a593Smuzhiyun int dongle_error;
1012*4882a593Smuzhiyun
1013*4882a593Smuzhiyun uint8 country_code[WLC_CNTRY_BUF_SZ];
1014*4882a593Smuzhiyun
1015*4882a593Smuzhiyun /* Suspend disable flag and "in suspend" flag */
1016*4882a593Smuzhiyun int suspend_disable_flag; /* "1" to disable all extra powersaving during suspend */
1017*4882a593Smuzhiyun int in_suspend; /* flag set to 1 when early suspend called */
1018*4882a593Smuzhiyun #ifdef PNO_SUPPORT
1019*4882a593Smuzhiyun int pno_enable; /* pno status : "1" is pno enable */
1020*4882a593Smuzhiyun int pno_suspend; /* pno suspend status : "1" is pno suspended */
1021*4882a593Smuzhiyun #endif /* PNO_SUPPORT */
1022*4882a593Smuzhiyun /* DTIM skip value, default 0(or 1) means wake each DTIM
1023*4882a593Smuzhiyun * 3 means skip 2 DTIMs and wake up 3rd DTIM(9th beacon when AP DTIM is 3)
1024*4882a593Smuzhiyun */
1025*4882a593Smuzhiyun int suspend_bcn_li_dtim; /* bcn_li_dtim value in suspend mode */
1026*4882a593Smuzhiyun #ifdef PKT_FILTER_SUPPORT
1027*4882a593Smuzhiyun int early_suspended; /* Early suspend status */
1028*4882a593Smuzhiyun int dhcp_in_progress; /* DHCP period */
1029*4882a593Smuzhiyun #endif // endif
1030*4882a593Smuzhiyun
1031*4882a593Smuzhiyun /* Pkt filter defination */
1032*4882a593Smuzhiyun char * pktfilter[100];
1033*4882a593Smuzhiyun int pktfilter_count;
1034*4882a593Smuzhiyun
1035*4882a593Smuzhiyun wl_country_t dhd_cspec; /* Current Locale info */
1036*4882a593Smuzhiyun #ifdef CUSTOM_COUNTRY_CODE
1037*4882a593Smuzhiyun uint dhd_cflags;
1038*4882a593Smuzhiyun #endif /* CUSTOM_COUNTRY_CODE */
1039*4882a593Smuzhiyun #if defined(DHD_BLOB_EXISTENCE_CHECK)
1040*4882a593Smuzhiyun bool is_blob; /* Checking for existance of Blob file */
1041*4882a593Smuzhiyun #endif /* DHD_BLOB_EXISTENCE_CHECK */
1042*4882a593Smuzhiyun bool force_country_change;
1043*4882a593Smuzhiyun char eventmask[WL_EVENTING_MASK_LEN];
1044*4882a593Smuzhiyun int op_mode; /* STA, HostAPD, WFD, SoftAP */
1045*4882a593Smuzhiyun
1046*4882a593Smuzhiyun /* Set this to 1 to use a seperate interface (p2p0) for p2p operations.
1047*4882a593Smuzhiyun * For ICS MR1 releases it should be disable to be compatable with ICS MR1 Framework
1048*4882a593Smuzhiyun * see target dhd-cdc-sdmmc-panda-cfg80211-icsmr1-gpl-debug in Makefile
1049*4882a593Smuzhiyun */
1050*4882a593Smuzhiyun /* #define WL_ENABLE_P2P_IF 1 */
1051*4882a593Smuzhiyun
1052*4882a593Smuzhiyun #if defined(OEM_ANDROID)
1053*4882a593Smuzhiyun struct mutex wl_start_stop_lock; /* lock/unlock for Android start/stop */
1054*4882a593Smuzhiyun struct mutex wl_softap_lock; /* lock/unlock for any SoftAP/STA settings */
1055*4882a593Smuzhiyun #endif /* defined(OEM_ANDROID) */
1056*4882a593Smuzhiyun
1057*4882a593Smuzhiyun #ifdef PROP_TXSTATUS
1058*4882a593Smuzhiyun bool wlfc_enabled;
1059*4882a593Smuzhiyun int wlfc_mode;
1060*4882a593Smuzhiyun void* wlfc_state;
1061*4882a593Smuzhiyun /*
1062*4882a593Smuzhiyun Mode in which the dhd flow control shall operate. Must be set before
1063*4882a593Smuzhiyun traffic starts to the device.
1064*4882a593Smuzhiyun 0 - Do not do any proptxtstatus flow control
1065*4882a593Smuzhiyun 1 - Use implied credit from a packet status
1066*4882a593Smuzhiyun 2 - Use explicit credit
1067*4882a593Smuzhiyun 3 - Only AMPDU hostreorder used. no wlfc.
1068*4882a593Smuzhiyun */
1069*4882a593Smuzhiyun uint8 proptxstatus_mode;
1070*4882a593Smuzhiyun bool proptxstatus_txoff;
1071*4882a593Smuzhiyun bool proptxstatus_module_ignore;
1072*4882a593Smuzhiyun bool proptxstatus_credit_ignore;
1073*4882a593Smuzhiyun bool proptxstatus_txstatus_ignore;
1074*4882a593Smuzhiyun
1075*4882a593Smuzhiyun bool wlfc_rxpkt_chk;
1076*4882a593Smuzhiyun #ifdef LIMIT_BORROW
1077*4882a593Smuzhiyun bool wlfc_borrow_allowed;
1078*4882a593Smuzhiyun #endif /* LIMIT_BORROW */
1079*4882a593Smuzhiyun /*
1080*4882a593Smuzhiyun * implement below functions in each platform if needed.
1081*4882a593Smuzhiyun */
1082*4882a593Smuzhiyun /* platform specific function whether to skip flow control */
1083*4882a593Smuzhiyun bool (*skip_fc)(void * dhdp, uint8 ifx);
1084*4882a593Smuzhiyun /* platform specific function for wlfc_enable and wlfc_deinit */
1085*4882a593Smuzhiyun void (*plat_init)(void *dhd);
1086*4882a593Smuzhiyun void (*plat_deinit)(void *dhd);
1087*4882a593Smuzhiyun #ifdef DHD_WLFC_THREAD
1088*4882a593Smuzhiyun bool wlfc_thread_go;
1089*4882a593Smuzhiyun struct task_struct* wlfc_thread;
1090*4882a593Smuzhiyun wait_queue_head_t wlfc_wqhead;
1091*4882a593Smuzhiyun #endif /* DHD_WLFC_THREAD */
1092*4882a593Smuzhiyun #endif /* PROP_TXSTATUS */
1093*4882a593Smuzhiyun #ifdef PNO_SUPPORT
1094*4882a593Smuzhiyun void *pno_state;
1095*4882a593Smuzhiyun #endif // endif
1096*4882a593Smuzhiyun #ifdef RTT_SUPPORT
1097*4882a593Smuzhiyun void *rtt_state;
1098*4882a593Smuzhiyun #endif // endif
1099*4882a593Smuzhiyun #ifdef ROAM_AP_ENV_DETECTION
1100*4882a593Smuzhiyun bool roam_env_detection;
1101*4882a593Smuzhiyun #endif // endif
1102*4882a593Smuzhiyun bool dongle_isolation;
1103*4882a593Smuzhiyun bool is_pcie_watchdog_reset;
1104*4882a593Smuzhiyun
1105*4882a593Smuzhiyun /* Begin - Variables to track Bus Errors */
1106*4882a593Smuzhiyun bool dongle_trap_occured; /* flag for sending HANG event to upper layer */
1107*4882a593Smuzhiyun bool iovar_timeout_occured; /* flag to indicate iovar resumed on timeout */
1108*4882a593Smuzhiyun bool is_sched_error; /* flag to indicate timeout due to scheduling issue */
1109*4882a593Smuzhiyun #ifdef PCIE_FULL_DONGLE
1110*4882a593Smuzhiyun bool d3ack_timeout_occured; /* flag to indicate d3ack resumed on timeout */
1111*4882a593Smuzhiyun bool livelock_occured; /* flag to indicate livelock occured */
1112*4882a593Smuzhiyun bool pktid_audit_failed; /* flag to indicate pktid audit failure */
1113*4882a593Smuzhiyun #endif /* PCIE_FULL_DONGLE */
1114*4882a593Smuzhiyun bool iface_op_failed; /* flag to indicate interface operation failed */
1115*4882a593Smuzhiyun bool scan_timeout_occurred; /* flag to indicate scan has timedout */
1116*4882a593Smuzhiyun bool scan_busy_occurred; /* flag to indicate scan busy occurred */
1117*4882a593Smuzhiyun #ifdef BT_OVER_SDIO
1118*4882a593Smuzhiyun bool is_bt_recovery_required;
1119*4882a593Smuzhiyun #endif // endif
1120*4882a593Smuzhiyun bool smmu_fault_occurred; /* flag to indicate SMMU Fault */
1121*4882a593Smuzhiyun /*
1122*4882a593Smuzhiyun * Add any new variables to track Bus errors above
1123*4882a593Smuzhiyun * this line. Also ensure that the variable is
1124*4882a593Smuzhiyun * cleared from dhd_clear_bus_errors
1125*4882a593Smuzhiyun */
1126*4882a593Smuzhiyun /* End - Variables to track Bus Errors */
1127*4882a593Smuzhiyun
1128*4882a593Smuzhiyun int hang_was_sent;
1129*4882a593Smuzhiyun int hang_was_pending;
1130*4882a593Smuzhiyun int rxcnt_timeout; /* counter rxcnt timeout to send HANG */
1131*4882a593Smuzhiyun int txcnt_timeout; /* counter txcnt timeout to send HANG */
1132*4882a593Smuzhiyun #ifdef BCMPCIE
1133*4882a593Smuzhiyun int d3ackcnt_timeout; /* counter d3ack timeout to send HANG */
1134*4882a593Smuzhiyun #endif /* BCMPCIE */
1135*4882a593Smuzhiyun bool hang_report; /* enable hang report by default */
1136*4882a593Smuzhiyun uint16 hang_reason; /* reason codes for HANG event */
1137*4882a593Smuzhiyun #if defined(DHD_HANG_SEND_UP_TEST)
1138*4882a593Smuzhiyun uint req_hang_type;
1139*4882a593Smuzhiyun #endif /* DHD_HANG_SEND_UP_TEST */
1140*4882a593Smuzhiyun #if defined(CONFIG_BCM_DETECT_CONSECUTIVE_HANG)
1141*4882a593Smuzhiyun uint hang_counts;
1142*4882a593Smuzhiyun #endif /* CONFIG_BCM_DETECT_CONSECUTIVE_HANG */
1143*4882a593Smuzhiyun #ifdef WLTDLS
1144*4882a593Smuzhiyun bool tdls_enable;
1145*4882a593Smuzhiyun #endif // endif
1146*4882a593Smuzhiyun struct reorder_info *reorder_bufs[WLHOST_REORDERDATA_MAXFLOWS];
1147*4882a593Smuzhiyun #define WLC_IOCTL_MAXBUF_FWCAP 1024
1148*4882a593Smuzhiyun char fw_capabilities[WLC_IOCTL_MAXBUF_FWCAP];
1149*4882a593Smuzhiyun #define MAXSKBPEND 1024
1150*4882a593Smuzhiyun void *skbbuf[MAXSKBPEND];
1151*4882a593Smuzhiyun uint32 store_idx;
1152*4882a593Smuzhiyun uint32 sent_idx;
1153*4882a593Smuzhiyun #ifdef DHDTCPACK_SUPPRESS
1154*4882a593Smuzhiyun uint8 tcpack_sup_mode; /* TCPACK suppress mode */
1155*4882a593Smuzhiyun void *tcpack_sup_module; /* TCPACK suppress module */
1156*4882a593Smuzhiyun uint32 tcpack_sup_ratio;
1157*4882a593Smuzhiyun uint32 tcpack_sup_delay;
1158*4882a593Smuzhiyun #endif /* DHDTCPACK_SUPPRESS */
1159*4882a593Smuzhiyun #if defined(ARP_OFFLOAD_SUPPORT)
1160*4882a593Smuzhiyun uint32 arp_version;
1161*4882a593Smuzhiyun #endif // endif
1162*4882a593Smuzhiyun #if defined(BCMSUP_4WAY_HANDSHAKE)
1163*4882a593Smuzhiyun bool fw_4way_handshake; /* Whether firmware will to do the 4way handshake. */
1164*4882a593Smuzhiyun #endif // endif
1165*4882a593Smuzhiyun #ifdef DEBUG_DPC_THREAD_WATCHDOG
1166*4882a593Smuzhiyun bool dhd_bug_on;
1167*4882a593Smuzhiyun #endif /* DEBUG_DPC_THREAD_WATCHDOG */
1168*4882a593Smuzhiyun #ifdef CUSTOM_SET_CPUCORE
1169*4882a593Smuzhiyun struct task_struct * current_dpc;
1170*4882a593Smuzhiyun struct task_struct * current_rxf;
1171*4882a593Smuzhiyun int chan_isvht80;
1172*4882a593Smuzhiyun #endif /* CUSTOM_SET_CPUCORE */
1173*4882a593Smuzhiyun
1174*4882a593Smuzhiyun void *sta_pool; /* pre-allocated pool of sta objects */
1175*4882a593Smuzhiyun void *staid_allocator; /* allocator of sta indexes */
1176*4882a593Smuzhiyun #ifdef PCIE_FULL_DONGLE
1177*4882a593Smuzhiyun bool flow_rings_inited; /* set this flag after initializing flow rings */
1178*4882a593Smuzhiyun #endif /* PCIE_FULL_DONGLE */
1179*4882a593Smuzhiyun void *flowid_allocator; /* unique flowid allocator */
1180*4882a593Smuzhiyun void *flow_ring_table; /* flow ring table, include prot and bus info */
1181*4882a593Smuzhiyun void *if_flow_lkup; /* per interface flowid lkup hash table */
1182*4882a593Smuzhiyun void *flowid_lock; /* per os lock for flowid info protection */
1183*4882a593Smuzhiyun void *flowring_list_lock; /* per os lock for flowring list protection */
1184*4882a593Smuzhiyun uint8 max_multi_client_flow_rings;
1185*4882a593Smuzhiyun uint8 multi_client_flow_rings;
1186*4882a593Smuzhiyun uint32 num_flow_rings;
1187*4882a593Smuzhiyun cumm_ctr_t cumm_ctr; /* cumm queue length placeholder */
1188*4882a593Smuzhiyun cumm_ctr_t l2cumm_ctr; /* level 2 cumm queue length placeholder */
1189*4882a593Smuzhiyun uint32 d2h_sync_mode; /* D2H DMA completion sync mode */
1190*4882a593Smuzhiyun uint8 flow_prio_map[NUMPRIO];
1191*4882a593Smuzhiyun uint8 flow_prio_map_type;
1192*4882a593Smuzhiyun char enable_log[MAX_EVENT];
1193*4882a593Smuzhiyun bool dma_d2h_ring_upd_support;
1194*4882a593Smuzhiyun bool dma_h2d_ring_upd_support;
1195*4882a593Smuzhiyun bool dma_ring_upd_overwrite; /* host overwrites support setting */
1196*4882a593Smuzhiyun
1197*4882a593Smuzhiyun bool hwa_enable;
1198*4882a593Smuzhiyun uint hwa_inited;
1199*4882a593Smuzhiyun
1200*4882a593Smuzhiyun bool idma_enable;
1201*4882a593Smuzhiyun uint idma_inited;
1202*4882a593Smuzhiyun
1203*4882a593Smuzhiyun bool ifrm_enable; /* implicit frm enable */
1204*4882a593Smuzhiyun uint ifrm_inited; /* implicit frm init */
1205*4882a593Smuzhiyun
1206*4882a593Smuzhiyun bool dar_enable; /* use DAR registers */
1207*4882a593Smuzhiyun uint dar_inited;
1208*4882a593Smuzhiyun
1209*4882a593Smuzhiyun bool fast_delete_ring_support; /* fast delete ring supported */
1210*4882a593Smuzhiyun
1211*4882a593Smuzhiyun #ifdef DHD_L2_FILTER
1212*4882a593Smuzhiyun unsigned long l2_filter_cnt; /* for L2_FILTER ARP table timeout */
1213*4882a593Smuzhiyun #endif /* DHD_L2_FILTER */
1214*4882a593Smuzhiyun #ifdef DHD_SSSR_DUMP
1215*4882a593Smuzhiyun bool sssr_inited;
1216*4882a593Smuzhiyun bool sssr_dump_collected; /* Flag to indicate sssr dump is collected */
1217*4882a593Smuzhiyun sssr_reg_info_v1_t sssr_reg_info;
1218*4882a593Smuzhiyun uint8 *sssr_mempool;
1219*4882a593Smuzhiyun uint *sssr_d11_before[MAX_NUM_D11CORES];
1220*4882a593Smuzhiyun uint *sssr_d11_after[MAX_NUM_D11CORES];
1221*4882a593Smuzhiyun bool sssr_d11_outofreset[MAX_NUM_D11CORES];
1222*4882a593Smuzhiyun uint *sssr_dig_buf_before;
1223*4882a593Smuzhiyun uint *sssr_dig_buf_after;
1224*4882a593Smuzhiyun uint32 sssr_dump_mode;
1225*4882a593Smuzhiyun bool collect_sssr; /* Flag to indicate SSSR dump is required */
1226*4882a593Smuzhiyun #endif /* DHD_SSSR_DUMP */
1227*4882a593Smuzhiyun uint8 *soc_ram;
1228*4882a593Smuzhiyun uint32 soc_ram_length;
1229*4882a593Smuzhiyun uint32 memdump_type;
1230*4882a593Smuzhiyun #ifdef DHD_RND_DEBUG
1231*4882a593Smuzhiyun uint8 *rnd_buf;
1232*4882a593Smuzhiyun uint32 rnd_len;
1233*4882a593Smuzhiyun #endif /* DHD_RND_DEBUG */
1234*4882a593Smuzhiyun #ifdef DHD_FW_COREDUMP
1235*4882a593Smuzhiyun uint32 memdump_enabled;
1236*4882a593Smuzhiyun #ifdef DHD_DEBUG_UART
1237*4882a593Smuzhiyun bool memdump_success;
1238*4882a593Smuzhiyun #endif /* DHD_DEBUG_UART */
1239*4882a593Smuzhiyun #endif /* DHD_FW_COREDUMP */
1240*4882a593Smuzhiyun #ifdef PCIE_FULL_DONGLE
1241*4882a593Smuzhiyun #ifdef WLTDLS
1242*4882a593Smuzhiyun tdls_peer_tbl_t peer_tbl;
1243*4882a593Smuzhiyun #endif /* WLTDLS */
1244*4882a593Smuzhiyun uint8 tx_in_progress;
1245*4882a593Smuzhiyun #endif /* PCIE_FULL_DONGLE */
1246*4882a593Smuzhiyun #ifdef DHD_ULP
1247*4882a593Smuzhiyun void *dhd_ulp;
1248*4882a593Smuzhiyun #endif // endif
1249*4882a593Smuzhiyun #ifdef WLTDLS
1250*4882a593Smuzhiyun uint32 tdls_mode;
1251*4882a593Smuzhiyun #endif // endif
1252*4882a593Smuzhiyun #ifdef GSCAN_SUPPORT
1253*4882a593Smuzhiyun bool lazy_roam_enable;
1254*4882a593Smuzhiyun #endif // endif
1255*4882a593Smuzhiyun #if defined(PKT_FILTER_SUPPORT) && defined(APF)
1256*4882a593Smuzhiyun bool apf_set;
1257*4882a593Smuzhiyun #endif /* PKT_FILTER_SUPPORT && APF */
1258*4882a593Smuzhiyun void *macdbg_info;
1259*4882a593Smuzhiyun #ifdef DHD_WET
1260*4882a593Smuzhiyun void *wet_info;
1261*4882a593Smuzhiyun #endif // endif
1262*4882a593Smuzhiyun bool h2d_phase_supported;
1263*4882a593Smuzhiyun bool force_dongletrap_on_bad_h2d_phase;
1264*4882a593Smuzhiyun uint32 dongle_trap_data;
1265*4882a593Smuzhiyun fw_download_status_t fw_download_status;
1266*4882a593Smuzhiyun trap_t last_trap_info; /* trap info from the last trap */
1267*4882a593Smuzhiyun uint8 rand_mac_oui[DOT11_OUI_LEN];
1268*4882a593Smuzhiyun #ifdef DHD_LOSSLESS_ROAMING
1269*4882a593Smuzhiyun uint8 dequeue_prec_map;
1270*4882a593Smuzhiyun uint8 prio_8021x;
1271*4882a593Smuzhiyun #endif // endif
1272*4882a593Smuzhiyun #ifdef WL_NATOE
1273*4882a593Smuzhiyun struct dhd_nfct_info *nfct;
1274*4882a593Smuzhiyun spinlock_t nfct_lock;
1275*4882a593Smuzhiyun #endif /* WL_NATOE */
1276*4882a593Smuzhiyun /* timesync link */
1277*4882a593Smuzhiyun struct dhd_ts *ts;
1278*4882a593Smuzhiyun bool d2h_hostrdy_supported;
1279*4882a593Smuzhiyun #ifdef DHD_PCIE_NATIVE_RUNTIMEPM
1280*4882a593Smuzhiyun atomic_t block_bus;
1281*4882a593Smuzhiyun #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
1282*4882a593Smuzhiyun #if defined(DBG_PKT_MON) || defined(DHD_PKT_LOGGING)
1283*4882a593Smuzhiyun bool d11_tx_status;
1284*4882a593Smuzhiyun #endif /* DBG_PKT_MON || DHD_PKT_LOGGING */
1285*4882a593Smuzhiyun uint16 ndo_version; /* ND offload version supported */
1286*4882a593Smuzhiyun #ifdef NDO_CONFIG_SUPPORT
1287*4882a593Smuzhiyun bool ndo_enable; /* ND offload feature enable */
1288*4882a593Smuzhiyun bool ndo_host_ip_overflow; /* # of host ip addr exceed FW capacity */
1289*4882a593Smuzhiyun uint32 ndo_max_host_ip; /* # of host ip addr supported by FW */
1290*4882a593Smuzhiyun #endif /* NDO_CONFIG_SUPPORT */
1291*4882a593Smuzhiyun #if defined(DHD_LOG_DUMP)
1292*4882a593Smuzhiyun /* buffer to hold 'dhd dump' data before dumping to file */
1293*4882a593Smuzhiyun uint8 *concise_dbg_buf;
1294*4882a593Smuzhiyun uint64 last_file_posn;
1295*4882a593Smuzhiyun int logdump_periodic_flush;
1296*4882a593Smuzhiyun /* ecounter debug ring */
1297*4882a593Smuzhiyun #ifdef EWP_ECNTRS_LOGGING
1298*4882a593Smuzhiyun void *ecntr_dbg_ring;
1299*4882a593Smuzhiyun #endif // endif
1300*4882a593Smuzhiyun #ifdef EWP_RTT_LOGGING
1301*4882a593Smuzhiyun void *rtt_dbg_ring;
1302*4882a593Smuzhiyun #endif // endif
1303*4882a593Smuzhiyun #ifdef DNGL_EVENT_SUPPORT
1304*4882a593Smuzhiyun uint8 health_chk_event_data[HEALTH_CHK_BUF_SIZE];
1305*4882a593Smuzhiyun #endif // endif
1306*4882a593Smuzhiyun void *logdump_cookie;
1307*4882a593Smuzhiyun #endif /* DHD_LOG_DUMP */
1308*4882a593Smuzhiyun uint32 dhd_console_ms; /** interval for polling the dongle for console (log) messages */
1309*4882a593Smuzhiyun bool ext_trap_data_supported;
1310*4882a593Smuzhiyun uint32 *extended_trap_data;
1311*4882a593Smuzhiyun #ifdef DUMP_IOCTL_IOV_LIST
1312*4882a593Smuzhiyun /* dump iovar list */
1313*4882a593Smuzhiyun dll_t dump_iovlist_head;
1314*4882a593Smuzhiyun uint8 dump_iovlist_len;
1315*4882a593Smuzhiyun #endif /* DUMP_IOCTL_IOV_LIST */
1316*4882a593Smuzhiyun #ifdef CUSTOM_SET_ANTNPM
1317*4882a593Smuzhiyun uint32 mimo_ant_set;
1318*4882a593Smuzhiyun #endif /* CUSTOM_SET_ANTNPM */
1319*4882a593Smuzhiyun #ifdef CUSTOM_SET_OCLOFF
1320*4882a593Smuzhiyun bool ocl_off;
1321*4882a593Smuzhiyun #endif /* CUSTOM_SET_OCLOFF */
1322*4882a593Smuzhiyun #ifdef DHD_DEBUG
1323*4882a593Smuzhiyun /* memwaste feature */
1324*4882a593Smuzhiyun dll_t mw_list_head; /* memwaste list head */
1325*4882a593Smuzhiyun uint32 mw_id; /* memwaste list unique id */
1326*4882a593Smuzhiyun #endif /* DHD_DEBUG */
1327*4882a593Smuzhiyun #ifdef WLTDLS
1328*4882a593Smuzhiyun spinlock_t tdls_lock;
1329*4882a593Smuzhiyun #endif /* WLTDLS */
1330*4882a593Smuzhiyun uint pcie_txs_metadata_enable;
1331*4882a593Smuzhiyun uint wbtext_policy; /* wbtext policy of dongle */
1332*4882a593Smuzhiyun bool wbtext_support; /* for product policy only */
1333*4882a593Smuzhiyun bool max_dtim_enable; /* use MAX bcn_li_dtim value in suspend mode */
1334*4882a593Smuzhiyun tput_test_t tput_data;
1335*4882a593Smuzhiyun uint64 tput_start_ts;
1336*4882a593Smuzhiyun uint64 tput_stop_ts;
1337*4882a593Smuzhiyun #ifdef WL_MONITOR
1338*4882a593Smuzhiyun bool monitor_enable;
1339*4882a593Smuzhiyun #endif // endif
1340*4882a593Smuzhiyun #ifdef DHD_PKT_LOGGING
1341*4882a593Smuzhiyun struct dhd_pktlog *pktlog;
1342*4882a593Smuzhiyun char debug_dump_time_pktlog_str[DEBUG_DUMP_TIME_BUF_LEN];
1343*4882a593Smuzhiyun #endif /* DHD_PKT_LOGGING */
1344*4882a593Smuzhiyun uint dhd_watchdog_ms_backup;
1345*4882a593Smuzhiyun void *event_log_filter;
1346*4882a593Smuzhiyun #ifdef WL_CFGVENDOR_SEND_HANG_EVENT
1347*4882a593Smuzhiyun char *hang_info;
1348*4882a593Smuzhiyun int hang_info_cnt;
1349*4882a593Smuzhiyun char debug_dump_time_hang_str[DEBUG_DUMP_TIME_BUF_LEN];
1350*4882a593Smuzhiyun #endif /* WL_CFGVENDOR_SEND_HANG_EVENT */
1351*4882a593Smuzhiyun char debug_dump_time_str[DEBUG_DUMP_TIME_BUF_LEN];
1352*4882a593Smuzhiyun uint32 logset_prsrv_mask;
1353*4882a593Smuzhiyun bool wl_event_enabled;
1354*4882a593Smuzhiyun bool logtrace_pkt_sendup;
1355*4882a593Smuzhiyun #ifdef DHD_DUMP_MNGR
1356*4882a593Smuzhiyun struct _dhd_dump_file_manage *dump_file_manage;
1357*4882a593Smuzhiyun #endif /* DHD_DUMP_MNGR */
1358*4882a593Smuzhiyun int debug_dump_subcmd;
1359*4882a593Smuzhiyun uint64 debug_dump_time_sec;
1360*4882a593Smuzhiyun bool hscb_enable;
1361*4882a593Smuzhiyun wait_queue_head_t tx_completion_wait;
1362*4882a593Smuzhiyun uint32 batch_tx_pkts_cmpl;
1363*4882a593Smuzhiyun uint32 batch_tx_num_pkts;
1364*4882a593Smuzhiyun #ifdef DHD_ERPOM
1365*4882a593Smuzhiyun bool enable_erpom;
1366*4882a593Smuzhiyun pom_func_handler_t pom_wlan_handler;
1367*4882a593Smuzhiyun int (*pom_func_register)(pom_func_handler_t *func);
1368*4882a593Smuzhiyun int (*pom_func_deregister)(pom_func_handler_t *func);
1369*4882a593Smuzhiyun int (*pom_toggle_reg_on)(uchar func_id, uchar reason);
1370*4882a593Smuzhiyun #endif /* DHD_ERPOM */
1371*4882a593Smuzhiyun #ifdef EWP_EDL
1372*4882a593Smuzhiyun bool dongle_edl_support;
1373*4882a593Smuzhiyun dhd_dma_buf_t edl_ring_mem;
1374*4882a593Smuzhiyun #endif /* EWP_EDL */
1375*4882a593Smuzhiyun #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25))
1376*4882a593Smuzhiyun struct mutex ndev_op_sync;
1377*4882a593Smuzhiyun #endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 25)) */
1378*4882a593Smuzhiyun
1379*4882a593Smuzhiyun bool debug_buf_dest_support;
1380*4882a593Smuzhiyun uint32 debug_buf_dest_stat[DEBUG_BUF_DEST_MAX];
1381*4882a593Smuzhiyun #if defined(DHD_H2D_LOG_TIME_SYNC)
1382*4882a593Smuzhiyun #define DHD_H2D_LOG_TIME_STAMP_MATCH (10000) /* 10 Seconds */
1383*4882a593Smuzhiyun /*
1384*4882a593Smuzhiyun * Interval for updating the dongle console message time stamp with the Host (DHD)
1385*4882a593Smuzhiyun * time stamp
1386*4882a593Smuzhiyun */
1387*4882a593Smuzhiyun uint32 dhd_rte_time_sync_ms;
1388*4882a593Smuzhiyun #endif /* DHD_H2D_LOG_TIME_SYNC */
1389*4882a593Smuzhiyun int wlc_ver_major;
1390*4882a593Smuzhiyun int wlc_ver_minor;
1391*4882a593Smuzhiyun #ifdef DHD_STATUS_LOGGING
1392*4882a593Smuzhiyun void *statlog;
1393*4882a593Smuzhiyun #endif /* DHD_STATUS_LOGGING */
1394*4882a593Smuzhiyun #ifdef DHD_HP2P
1395*4882a593Smuzhiyun bool hp2p_enable;
1396*4882a593Smuzhiyun bool hp2p_infra_enable;
1397*4882a593Smuzhiyun bool hp2p_capable;
1398*4882a593Smuzhiyun bool hp2p_ts_capable;
1399*4882a593Smuzhiyun uint16 pkt_thresh;
1400*4882a593Smuzhiyun uint16 time_thresh;
1401*4882a593Smuzhiyun uint16 pkt_expiry;
1402*4882a593Smuzhiyun hp2p_info_t hp2p_info[MAX_HP2P_FLOWS];
1403*4882a593Smuzhiyun bool hp2p_ring_active;
1404*4882a593Smuzhiyun #endif /* D2H_HP2P */
1405*4882a593Smuzhiyun #ifdef DHD_DB0TS
1406*4882a593Smuzhiyun bool db0ts_capable;
1407*4882a593Smuzhiyun #endif /* DHD_DB0TS */
1408*4882a593Smuzhiyun bool event_log_max_sets_queried;
1409*4882a593Smuzhiyun uint32 event_log_max_sets;
1410*4882a593Smuzhiyun uint16 dhd_induce_error;
1411*4882a593Smuzhiyun #ifdef CONFIG_SILENT_ROAM
1412*4882a593Smuzhiyun bool sroam_turn_on; /* Silent roam monitor enable flags */
1413*4882a593Smuzhiyun bool sroamed; /* Silent roam monitor check flags */
1414*4882a593Smuzhiyun #endif /* CONFIG_SILENT_ROAM */
1415*4882a593Smuzhiyun bool extdtxs_in_txcpl;
1416*4882a593Smuzhiyun bool hostrdy_after_init;
1417*4882a593Smuzhiyun #ifdef SUPPORT_SET_TID
1418*4882a593Smuzhiyun uint8 tid_mode;
1419*4882a593Smuzhiyun uint32 target_uid;
1420*4882a593Smuzhiyun uint8 target_tid;
1421*4882a593Smuzhiyun #endif /* SUPPORT_SET_TID */
1422*4882a593Smuzhiyun #ifdef DHD_PKTDUMP_ROAM
1423*4882a593Smuzhiyun void *pktcnts;
1424*4882a593Smuzhiyun #endif /* DHD_PKTDUMP_ROAM */
1425*4882a593Smuzhiyun bool disable_dtim_in_suspend; /* Disable set bcn_li_dtim in suspend */
1426*4882a593Smuzhiyun #ifdef REVERSE_AIFSN
1427*4882a593Smuzhiyun bool aifsn_reverse;
1428*4882a593Smuzhiyun #endif /* REVERSE_AIFSN */
1429*4882a593Smuzhiyun } dhd_pub_t;
1430*4882a593Smuzhiyun
1431*4882a593Smuzhiyun typedef struct {
1432*4882a593Smuzhiyun uint rxwake;
1433*4882a593Smuzhiyun uint rcwake;
1434*4882a593Smuzhiyun #ifdef DHD_WAKE_RX_STATUS
1435*4882a593Smuzhiyun uint rx_bcast;
1436*4882a593Smuzhiyun uint rx_arp;
1437*4882a593Smuzhiyun uint rx_mcast;
1438*4882a593Smuzhiyun uint rx_multi_ipv6;
1439*4882a593Smuzhiyun uint rx_icmpv6;
1440*4882a593Smuzhiyun uint rx_icmpv6_ra;
1441*4882a593Smuzhiyun uint rx_icmpv6_na;
1442*4882a593Smuzhiyun uint rx_icmpv6_ns;
1443*4882a593Smuzhiyun uint rx_multi_ipv4;
1444*4882a593Smuzhiyun uint rx_multi_other;
1445*4882a593Smuzhiyun uint rx_ucast;
1446*4882a593Smuzhiyun #endif /* DHD_WAKE_RX_STATUS */
1447*4882a593Smuzhiyun #ifdef DHD_WAKE_EVENT_STATUS
1448*4882a593Smuzhiyun uint rc_event[WLC_E_LAST];
1449*4882a593Smuzhiyun #endif /* DHD_WAKE_EVENT_STATUS */
1450*4882a593Smuzhiyun } wake_counts_t;
1451*4882a593Smuzhiyun
1452*4882a593Smuzhiyun #if defined(PCIE_FULL_DONGLE)
1453*4882a593Smuzhiyun
1454*4882a593Smuzhiyun /* Packet Tag for PCIE Full Dongle DHD */
1455*4882a593Smuzhiyun typedef struct dhd_pkttag_fd {
1456*4882a593Smuzhiyun uint16 flowid; /* Flowring Id */
1457*4882a593Smuzhiyun uint16 ifid;
1458*4882a593Smuzhiyun #ifndef DHD_PCIE_PKTID
1459*4882a593Smuzhiyun uint16 dma_len; /* pkt len for DMA_MAP/UNMAP */
1460*4882a593Smuzhiyun dmaaddr_t pa; /* physical address */
1461*4882a593Smuzhiyun void *dmah; /* dma mapper handle */
1462*4882a593Smuzhiyun void *secdma; /* secure dma sec_cma_info handle */
1463*4882a593Smuzhiyun #endif /* !DHD_PCIE_PKTID */
1464*4882a593Smuzhiyun #if defined(TX_STATUS_LATENCY_STATS)
1465*4882a593Smuzhiyun uint64 q_time_us; /* time when tx pkt queued to flowring */
1466*4882a593Smuzhiyun #endif // endif
1467*4882a593Smuzhiyun uint16 flags;
1468*4882a593Smuzhiyun } dhd_pkttag_fd_t;
1469*4882a593Smuzhiyun
1470*4882a593Smuzhiyun /* Packet Tag for DHD PCIE Full Dongle */
1471*4882a593Smuzhiyun #define DHD_PKTTAG_FD(pkt) ((dhd_pkttag_fd_t *)(PKTTAG(pkt)))
1472*4882a593Smuzhiyun
1473*4882a593Smuzhiyun #define DHD_PKT_GET_FLOWID(pkt) ((DHD_PKTTAG_FD(pkt))->flowid)
1474*4882a593Smuzhiyun #define DHD_PKT_SET_FLOWID(pkt, pkt_flowid) \
1475*4882a593Smuzhiyun DHD_PKTTAG_FD(pkt)->flowid = (uint16)(pkt_flowid)
1476*4882a593Smuzhiyun
1477*4882a593Smuzhiyun #define DHD_PKT_GET_DATAOFF(pkt) ((DHD_PKTTAG_FD(pkt))->dataoff)
1478*4882a593Smuzhiyun #define DHD_PKT_SET_DATAOFF(pkt, pkt_dataoff) \
1479*4882a593Smuzhiyun DHD_PKTTAG_FD(pkt)->dataoff = (uint16)(pkt_dataoff)
1480*4882a593Smuzhiyun
1481*4882a593Smuzhiyun #define DHD_PKT_GET_DMA_LEN(pkt) ((DHD_PKTTAG_FD(pkt))->dma_len)
1482*4882a593Smuzhiyun #define DHD_PKT_SET_DMA_LEN(pkt, pkt_dma_len) \
1483*4882a593Smuzhiyun DHD_PKTTAG_FD(pkt)->dma_len = (uint16)(pkt_dma_len)
1484*4882a593Smuzhiyun
1485*4882a593Smuzhiyun #define DHD_PKT_GET_PA(pkt) ((DHD_PKTTAG_FD(pkt))->pa)
1486*4882a593Smuzhiyun #define DHD_PKT_SET_PA(pkt, pkt_pa) \
1487*4882a593Smuzhiyun DHD_PKTTAG_FD(pkt)->pa = (dmaaddr_t)(pkt_pa)
1488*4882a593Smuzhiyun
1489*4882a593Smuzhiyun #define DHD_PKT_GET_DMAH(pkt) ((DHD_PKTTAG_FD(pkt))->dmah)
1490*4882a593Smuzhiyun #define DHD_PKT_SET_DMAH(pkt, pkt_dmah) \
1491*4882a593Smuzhiyun DHD_PKTTAG_FD(pkt)->dmah = (void *)(pkt_dmah)
1492*4882a593Smuzhiyun
1493*4882a593Smuzhiyun #define DHD_PKT_GET_SECDMA(pkt) ((DHD_PKTTAG_FD(pkt))->secdma)
1494*4882a593Smuzhiyun #define DHD_PKT_SET_SECDMA(pkt, pkt_secdma) \
1495*4882a593Smuzhiyun DHD_PKTTAG_FD(pkt)->secdma = (void *)(pkt_secdma)
1496*4882a593Smuzhiyun
1497*4882a593Smuzhiyun #if defined(TX_STATUS_LATENCY_STATS)
1498*4882a593Smuzhiyun #define DHD_PKT_GET_QTIME(pkt) ((DHD_PKTTAG_FD(pkt))->q_time_us)
1499*4882a593Smuzhiyun #define DHD_PKT_SET_QTIME(pkt, pkt_q_time_us) \
1500*4882a593Smuzhiyun DHD_PKTTAG_FD(pkt)->q_time_us = (uint64)(pkt_q_time_us)
1501*4882a593Smuzhiyun #endif // endif
1502*4882a593Smuzhiyun
1503*4882a593Smuzhiyun #define DHD_PKT_GET_FLAGS(pkt) ((DHD_PKTTAG_FD(pkt))->flags)
1504*4882a593Smuzhiyun #define DHD_PKT_SET_FLAGS(pkt, pkt_flags) \
1505*4882a593Smuzhiyun DHD_PKTTAG_FD(pkt)->flags = (uint16)(pkt_flags)
1506*4882a593Smuzhiyun
1507*4882a593Smuzhiyun #define PKTFLAG_NO_FWD 0x8000
1508*4882a593Smuzhiyun
1509*4882a593Smuzhiyun #define DHD_PKT_FLAGS_SET_NO_FWD(pkt) \
1510*4882a593Smuzhiyun DHD_PKTTAG_FD(pkt)->flags |= PKTFLAG_NO_FWD
1511*4882a593Smuzhiyun #define DHD_PKT_FLAGS_CLEAR_NO_FWD(pkt) \
1512*4882a593Smuzhiyun DHD_PKTTAG_FD(pkt)->flags &= ~PKTFLAG_NO_FWD
1513*4882a593Smuzhiyun #define DHD_PKT_FLAGS_IS_NO_FWD(pkt) \
1514*4882a593Smuzhiyun (DHD_PKTTAG_FD(pkt)->flags & PKTFLAG_NO_FWD)
1515*4882a593Smuzhiyun
1516*4882a593Smuzhiyun #endif /* PCIE_FULL_DONGLE */
1517*4882a593Smuzhiyun
1518*4882a593Smuzhiyun #if defined(BCMWDF)
1519*4882a593Smuzhiyun typedef struct {
1520*4882a593Smuzhiyun dhd_pub_t *dhd_pub;
1521*4882a593Smuzhiyun } dhd_workitem_context_t;
1522*4882a593Smuzhiyun
1523*4882a593Smuzhiyun WDF_DECLARE_CONTEXT_TYPE_WITH_NAME(dhd_workitem_context_t, dhd_get_dhd_workitem_context)
1524*4882a593Smuzhiyun #endif /* (BCMWDF) */
1525*4882a593Smuzhiyun
1526*4882a593Smuzhiyun #if defined(CONFIG_PM_SLEEP)
1527*4882a593Smuzhiyun
1528*4882a593Smuzhiyun #define DHD_PM_RESUME_WAIT_INIT(a) DECLARE_WAIT_QUEUE_HEAD(a);
1529*4882a593Smuzhiyun #define _DHD_PM_RESUME_WAIT(a, b) do {\
1530*4882a593Smuzhiyun int retry = 0; \
1531*4882a593Smuzhiyun SMP_RD_BARRIER_DEPENDS(); \
1532*4882a593Smuzhiyun while (dhd_mmc_suspend && retry++ != b) { \
1533*4882a593Smuzhiyun SMP_RD_BARRIER_DEPENDS(); \
1534*4882a593Smuzhiyun wait_event_interruptible_timeout(a, !dhd_mmc_suspend, 1); \
1535*4882a593Smuzhiyun } \
1536*4882a593Smuzhiyun } while (0)
1537*4882a593Smuzhiyun #define DHD_PM_RESUME_WAIT(a) _DHD_PM_RESUME_WAIT(a, 200)
1538*4882a593Smuzhiyun #define DHD_PM_RESUME_WAIT_FOREVER(a) _DHD_PM_RESUME_WAIT(a, ~0)
1539*4882a593Smuzhiyun #define DHD_PM_RESUME_RETURN_ERROR(a) do { \
1540*4882a593Smuzhiyun if (dhd_mmc_suspend) { \
1541*4882a593Smuzhiyun printf("%s[%d]: mmc is still in suspend state!!!\n", \
1542*4882a593Smuzhiyun __FUNCTION__, __LINE__); \
1543*4882a593Smuzhiyun return a; \
1544*4882a593Smuzhiyun } \
1545*4882a593Smuzhiyun } while (0)
1546*4882a593Smuzhiyun #define DHD_PM_RESUME_RETURN do { if (dhd_mmc_suspend) return; } while (0)
1547*4882a593Smuzhiyun
1548*4882a593Smuzhiyun #define DHD_SPINWAIT_SLEEP_INIT(a) DECLARE_WAIT_QUEUE_HEAD(a);
1549*4882a593Smuzhiyun #define SPINWAIT_SLEEP(a, exp, us) do { \
1550*4882a593Smuzhiyun uint countdown = (us) + 9999; \
1551*4882a593Smuzhiyun while ((exp) && (countdown >= 10000)) { \
1552*4882a593Smuzhiyun wait_event_interruptible_timeout(a, FALSE, 1); \
1553*4882a593Smuzhiyun countdown -= 10000; \
1554*4882a593Smuzhiyun } \
1555*4882a593Smuzhiyun } while (0)
1556*4882a593Smuzhiyun
1557*4882a593Smuzhiyun #else
1558*4882a593Smuzhiyun
1559*4882a593Smuzhiyun #define DHD_PM_RESUME_WAIT_INIT(a)
1560*4882a593Smuzhiyun #define DHD_PM_RESUME_WAIT(a)
1561*4882a593Smuzhiyun #define DHD_PM_RESUME_WAIT_FOREVER(a)
1562*4882a593Smuzhiyun #define DHD_PM_RESUME_RETURN_ERROR(a)
1563*4882a593Smuzhiyun #define DHD_PM_RESUME_RETURN
1564*4882a593Smuzhiyun
1565*4882a593Smuzhiyun #define DHD_SPINWAIT_SLEEP_INIT(a)
1566*4882a593Smuzhiyun #define SPINWAIT_SLEEP(a, exp, us) do { \
1567*4882a593Smuzhiyun uint countdown = (us) + 9; \
1568*4882a593Smuzhiyun while ((exp) && (countdown >= 10)) { \
1569*4882a593Smuzhiyun OSL_DELAY(10); \
1570*4882a593Smuzhiyun countdown -= 10; \
1571*4882a593Smuzhiyun } \
1572*4882a593Smuzhiyun } while (0)
1573*4882a593Smuzhiyun
1574*4882a593Smuzhiyun #endif /* CONFIG_PM_SLEEP */
1575*4882a593Smuzhiyun
1576*4882a593Smuzhiyun #ifndef OSL_SLEEP
1577*4882a593Smuzhiyun #define OSL_SLEEP(ms) OSL_DELAY(ms*1000)
1578*4882a593Smuzhiyun #endif /* OSL_SLEEP */
1579*4882a593Smuzhiyun
1580*4882a593Smuzhiyun #define DHD_IF_VIF 0x01 /* Virtual IF (Hidden from user) */
1581*4882a593Smuzhiyun
1582*4882a593Smuzhiyun #ifdef PNO_SUPPORT
1583*4882a593Smuzhiyun int dhd_pno_clean(dhd_pub_t *dhd);
1584*4882a593Smuzhiyun #endif /* PNO_SUPPORT */
1585*4882a593Smuzhiyun
1586*4882a593Smuzhiyun /*
1587*4882a593Smuzhiyun * Wake locks are an Android power management concept. They are used by applications and services
1588*4882a593Smuzhiyun * to request CPU resources.
1589*4882a593Smuzhiyun */
1590*4882a593Smuzhiyun #if defined(OEM_ANDROID)
1591*4882a593Smuzhiyun extern int dhd_os_wake_lock(dhd_pub_t *pub);
1592*4882a593Smuzhiyun extern int dhd_os_wake_unlock(dhd_pub_t *pub);
1593*4882a593Smuzhiyun extern int dhd_os_wake_lock_waive(dhd_pub_t *pub);
1594*4882a593Smuzhiyun extern int dhd_os_wake_lock_restore(dhd_pub_t *pub);
1595*4882a593Smuzhiyun extern void dhd_event_wake_lock(dhd_pub_t *pub);
1596*4882a593Smuzhiyun extern void dhd_event_wake_unlock(dhd_pub_t *pub);
1597*4882a593Smuzhiyun extern void dhd_pm_wake_lock_timeout(dhd_pub_t *pub, int val);
1598*4882a593Smuzhiyun extern void dhd_pm_wake_unlock(dhd_pub_t *pub);
1599*4882a593Smuzhiyun extern void dhd_txfl_wake_lock_timeout(dhd_pub_t *pub, int val);
1600*4882a593Smuzhiyun extern void dhd_txfl_wake_unlock(dhd_pub_t *pub);
1601*4882a593Smuzhiyun extern int dhd_os_wake_lock_timeout(dhd_pub_t *pub);
1602*4882a593Smuzhiyun extern int dhd_os_wake_lock_rx_timeout_enable(dhd_pub_t *pub, int val);
1603*4882a593Smuzhiyun extern int dhd_os_wake_lock_ctrl_timeout_enable(dhd_pub_t *pub, int val);
1604*4882a593Smuzhiyun extern int dhd_os_wake_lock_ctrl_timeout_cancel(dhd_pub_t *pub);
1605*4882a593Smuzhiyun extern int dhd_os_wd_wake_lock(dhd_pub_t *pub);
1606*4882a593Smuzhiyun extern int dhd_os_wd_wake_unlock(dhd_pub_t *pub);
1607*4882a593Smuzhiyun extern void dhd_os_wake_lock_init(struct dhd_info *dhd);
1608*4882a593Smuzhiyun extern void dhd_os_wake_lock_destroy(struct dhd_info *dhd);
1609*4882a593Smuzhiyun #ifdef DHD_USE_SCAN_WAKELOCK
1610*4882a593Smuzhiyun extern void dhd_os_scan_wake_lock_timeout(dhd_pub_t *pub, int val);
1611*4882a593Smuzhiyun extern void dhd_os_scan_wake_unlock(dhd_pub_t *pub);
1612*4882a593Smuzhiyun #endif /* BCMPCIE_SCAN_WAKELOCK */
1613*4882a593Smuzhiyun
MUTEX_LOCK_SOFTAP_SET_INIT(dhd_pub_t * dhdp)1614*4882a593Smuzhiyun inline static void MUTEX_LOCK_SOFTAP_SET_INIT(dhd_pub_t * dhdp)
1615*4882a593Smuzhiyun {
1616*4882a593Smuzhiyun #if defined(OEM_ANDROID)
1617*4882a593Smuzhiyun mutex_init(&dhdp->wl_softap_lock);
1618*4882a593Smuzhiyun #endif /* OEM_ANDROID */
1619*4882a593Smuzhiyun }
1620*4882a593Smuzhiyun
MUTEX_LOCK_SOFTAP_SET(dhd_pub_t * dhdp)1621*4882a593Smuzhiyun inline static void MUTEX_LOCK_SOFTAP_SET(dhd_pub_t * dhdp)
1622*4882a593Smuzhiyun {
1623*4882a593Smuzhiyun #if defined(OEM_ANDROID)
1624*4882a593Smuzhiyun mutex_lock(&dhdp->wl_softap_lock);
1625*4882a593Smuzhiyun #endif /* OEM_ANDROID */
1626*4882a593Smuzhiyun }
1627*4882a593Smuzhiyun
MUTEX_UNLOCK_SOFTAP_SET(dhd_pub_t * dhdp)1628*4882a593Smuzhiyun inline static void MUTEX_UNLOCK_SOFTAP_SET(dhd_pub_t * dhdp)
1629*4882a593Smuzhiyun {
1630*4882a593Smuzhiyun #if defined(OEM_ANDROID)
1631*4882a593Smuzhiyun mutex_unlock(&dhdp->wl_softap_lock);
1632*4882a593Smuzhiyun #endif /* OEM_ANDROID */
1633*4882a593Smuzhiyun }
1634*4882a593Smuzhiyun
1635*4882a593Smuzhiyun #ifdef DHD_DEBUG_WAKE_LOCK
1636*4882a593Smuzhiyun #define DHD_OS_WAKE_LOCK(pub) \
1637*4882a593Smuzhiyun do { \
1638*4882a593Smuzhiyun printf("call wake_lock: %s %d\n", \
1639*4882a593Smuzhiyun __FUNCTION__, __LINE__); \
1640*4882a593Smuzhiyun dhd_os_wake_lock(pub); \
1641*4882a593Smuzhiyun } while (0)
1642*4882a593Smuzhiyun #define DHD_OS_WAKE_UNLOCK(pub) \
1643*4882a593Smuzhiyun do { \
1644*4882a593Smuzhiyun printf("call wake_unlock: %s %d\n", \
1645*4882a593Smuzhiyun __FUNCTION__, __LINE__); \
1646*4882a593Smuzhiyun dhd_os_wake_unlock(pub); \
1647*4882a593Smuzhiyun } while (0)
1648*4882a593Smuzhiyun #define DHD_EVENT_WAKE_LOCK(pub) \
1649*4882a593Smuzhiyun do { \
1650*4882a593Smuzhiyun printf("call event wake_lock: %s %d\n", \
1651*4882a593Smuzhiyun __FUNCTION__, __LINE__); \
1652*4882a593Smuzhiyun dhd_event_wake_lock(pub); \
1653*4882a593Smuzhiyun } while (0)
1654*4882a593Smuzhiyun #define DHD_EVENT_WAKE_UNLOCK(pub) \
1655*4882a593Smuzhiyun do { \
1656*4882a593Smuzhiyun printf("call event wake_unlock: %s %d\n", \
1657*4882a593Smuzhiyun __FUNCTION__, __LINE__); \
1658*4882a593Smuzhiyun dhd_event_wake_unlock(pub); \
1659*4882a593Smuzhiyun } while (0)
1660*4882a593Smuzhiyun #define DHD_PM_WAKE_LOCK_TIMEOUT(pub, val) \
1661*4882a593Smuzhiyun do { \
1662*4882a593Smuzhiyun printf("call pm_wake_timeout enable\n"); \
1663*4882a593Smuzhiyun dhd_pm_wake_lock_timeout(pub, val); \
1664*4882a593Smuzhiyun } while (0)
1665*4882a593Smuzhiyun #define DHD_PM_WAKE_UNLOCK(pub) \
1666*4882a593Smuzhiyun do { \
1667*4882a593Smuzhiyun printf("call pm_wake unlock\n"); \
1668*4882a593Smuzhiyun dhd_pm_wake_unlock(pub); \
1669*4882a593Smuzhiyun } while (0)
1670*4882a593Smuzhiyun #define DHD_TXFL_WAKE_LOCK_TIMEOUT(pub, val) \
1671*4882a593Smuzhiyun do { \
1672*4882a593Smuzhiyun printf("call pm_wake_timeout enable\n"); \
1673*4882a593Smuzhiyun dhd_txfl_wake_lock_timeout(pub, val); \
1674*4882a593Smuzhiyun } while (0)
1675*4882a593Smuzhiyun #define DHD_TXFL_WAKE_UNLOCK(pub) \
1676*4882a593Smuzhiyun do { \
1677*4882a593Smuzhiyun printf("call pm_wake unlock\n"); \
1678*4882a593Smuzhiyun dhd_txfl_wake_unlock(pub); \
1679*4882a593Smuzhiyun } while (0)
1680*4882a593Smuzhiyun #define DHD_OS_WAKE_LOCK_TIMEOUT(pub) \
1681*4882a593Smuzhiyun do { \
1682*4882a593Smuzhiyun printf("call wake_lock_timeout: %s %d\n", \
1683*4882a593Smuzhiyun __FUNCTION__, __LINE__); \
1684*4882a593Smuzhiyun dhd_os_wake_lock_timeout(pub); \
1685*4882a593Smuzhiyun } while (0)
1686*4882a593Smuzhiyun #define DHD_OS_WAKE_LOCK_RX_TIMEOUT_ENABLE(pub, val) \
1687*4882a593Smuzhiyun do { \
1688*4882a593Smuzhiyun printf("call wake_lock_rx_timeout_enable[%d]: %s %d\n", \
1689*4882a593Smuzhiyun val, __FUNCTION__, __LINE__); \
1690*4882a593Smuzhiyun dhd_os_wake_lock_rx_timeout_enable(pub, val); \
1691*4882a593Smuzhiyun } while (0)
1692*4882a593Smuzhiyun #define DHD_OS_WAKE_LOCK_CTRL_TIMEOUT_ENABLE(pub, val) \
1693*4882a593Smuzhiyun do { \
1694*4882a593Smuzhiyun printf("call wake_lock_ctrl_timeout_enable[%d]: %s %d\n", \
1695*4882a593Smuzhiyun val, __FUNCTION__, __LINE__); \
1696*4882a593Smuzhiyun dhd_os_wake_lock_ctrl_timeout_enable(pub, val); \
1697*4882a593Smuzhiyun } while (0)
1698*4882a593Smuzhiyun #define DHD_OS_WAKE_LOCK_CTRL_TIMEOUT_CANCEL(pub) \
1699*4882a593Smuzhiyun do { \
1700*4882a593Smuzhiyun printf("call wake_lock_ctrl_timeout_cancel: %s %d\n", \
1701*4882a593Smuzhiyun __FUNCTION__, __LINE__); \
1702*4882a593Smuzhiyun dhd_os_wake_lock_ctrl_timeout_cancel(pub); \
1703*4882a593Smuzhiyun } while (0)
1704*4882a593Smuzhiyun #define DHD_OS_WAKE_LOCK_WAIVE(pub) \
1705*4882a593Smuzhiyun do { \
1706*4882a593Smuzhiyun printf("call wake_lock_waive: %s %d\n", \
1707*4882a593Smuzhiyun __FUNCTION__, __LINE__); \
1708*4882a593Smuzhiyun dhd_os_wake_lock_waive(pub); \
1709*4882a593Smuzhiyun } while (0)
1710*4882a593Smuzhiyun #define DHD_OS_WAKE_LOCK_RESTORE(pub) \
1711*4882a593Smuzhiyun do { \
1712*4882a593Smuzhiyun printf("call wake_lock_restore: %s %d\n", \
1713*4882a593Smuzhiyun __FUNCTION__, __LINE__); \
1714*4882a593Smuzhiyun dhd_os_wake_lock_restore(pub); \
1715*4882a593Smuzhiyun } while (0)
1716*4882a593Smuzhiyun #define DHD_OS_WAKE_LOCK_INIT(dhd) \
1717*4882a593Smuzhiyun do { \
1718*4882a593Smuzhiyun printf("call wake_lock_init: %s %d\n", \
1719*4882a593Smuzhiyun __FUNCTION__, __LINE__); \
1720*4882a593Smuzhiyun dhd_os_wake_lock_init(dhd); \
1721*4882a593Smuzhiyun } while (0)
1722*4882a593Smuzhiyun #define DHD_OS_WAKE_LOCK_DESTROY(dhd) \
1723*4882a593Smuzhiyun do { \
1724*4882a593Smuzhiyun printf("call wake_lock_destroy: %s %d\n", \
1725*4882a593Smuzhiyun __FUNCTION__, __LINE__); \
1726*4882a593Smuzhiyun dhd_os_wake_lock_destroy(dhd); \
1727*4882a593Smuzhiyun } while (0)
1728*4882a593Smuzhiyun #else
1729*4882a593Smuzhiyun #define DHD_OS_WAKE_LOCK(pub) dhd_os_wake_lock(pub)
1730*4882a593Smuzhiyun #define DHD_OS_WAKE_UNLOCK(pub) dhd_os_wake_unlock(pub)
1731*4882a593Smuzhiyun #define DHD_EVENT_WAKE_LOCK(pub) dhd_event_wake_lock(pub)
1732*4882a593Smuzhiyun #define DHD_EVENT_WAKE_UNLOCK(pub) dhd_event_wake_unlock(pub)
1733*4882a593Smuzhiyun #define DHD_PM_WAKE_LOCK_TIMEOUT(pub, val) dhd_pm_wake_lock_timeout(pub, val)
1734*4882a593Smuzhiyun #define DHD_PM_WAKE_UNLOCK(pub) dhd_pm_wake_unlock(pub)
1735*4882a593Smuzhiyun #define DHD_TXFL_WAKE_LOCK_TIMEOUT(pub, val) dhd_txfl_wake_lock_timeout(pub, val)
1736*4882a593Smuzhiyun #define DHD_TXFL_WAKE_UNLOCK(pub) dhd_txfl_wake_unlock(pub)
1737*4882a593Smuzhiyun #define DHD_OS_WAKE_LOCK_TIMEOUT(pub) dhd_os_wake_lock_timeout(pub)
1738*4882a593Smuzhiyun #define DHD_OS_WAKE_LOCK_RX_TIMEOUT_ENABLE(pub, val) \
1739*4882a593Smuzhiyun dhd_os_wake_lock_rx_timeout_enable(pub, val)
1740*4882a593Smuzhiyun #define DHD_OS_WAKE_LOCK_CTRL_TIMEOUT_ENABLE(pub, val) \
1741*4882a593Smuzhiyun dhd_os_wake_lock_ctrl_timeout_enable(pub, val)
1742*4882a593Smuzhiyun #define DHD_OS_WAKE_LOCK_CTRL_TIMEOUT_CANCEL(pub) \
1743*4882a593Smuzhiyun dhd_os_wake_lock_ctrl_timeout_cancel(pub)
1744*4882a593Smuzhiyun #define DHD_OS_WAKE_LOCK_WAIVE(pub) dhd_os_wake_lock_waive(pub)
1745*4882a593Smuzhiyun #define DHD_OS_WAKE_LOCK_RESTORE(pub) dhd_os_wake_lock_restore(pub)
1746*4882a593Smuzhiyun #define DHD_OS_WAKE_LOCK_INIT(dhd) dhd_os_wake_lock_init(dhd);
1747*4882a593Smuzhiyun #define DHD_OS_WAKE_LOCK_DESTROY(dhd) dhd_os_wake_lock_destroy(dhd);
1748*4882a593Smuzhiyun #endif /* DHD_DEBUG_WAKE_LOCK */
1749*4882a593Smuzhiyun
1750*4882a593Smuzhiyun #define DHD_OS_WD_WAKE_LOCK(pub) dhd_os_wd_wake_lock(pub)
1751*4882a593Smuzhiyun #define DHD_OS_WD_WAKE_UNLOCK(pub) dhd_os_wd_wake_unlock(pub)
1752*4882a593Smuzhiyun
1753*4882a593Smuzhiyun #ifdef DHD_USE_SCAN_WAKELOCK
1754*4882a593Smuzhiyun #ifdef DHD_DEBUG_SCAN_WAKELOCK
1755*4882a593Smuzhiyun #define DHD_OS_SCAN_WAKE_LOCK_TIMEOUT(pub, val) \
1756*4882a593Smuzhiyun do { \
1757*4882a593Smuzhiyun printf("call wake_lock_scan: %s %d\n", \
1758*4882a593Smuzhiyun __FUNCTION__, __LINE__); \
1759*4882a593Smuzhiyun dhd_os_scan_wake_lock_timeout(pub, val); \
1760*4882a593Smuzhiyun } while (0)
1761*4882a593Smuzhiyun #define DHD_OS_SCAN_WAKE_UNLOCK(pub) \
1762*4882a593Smuzhiyun do { \
1763*4882a593Smuzhiyun printf("call wake_unlock_scan: %s %d\n", \
1764*4882a593Smuzhiyun __FUNCTION__, __LINE__); \
1765*4882a593Smuzhiyun dhd_os_scan_wake_unlock(pub); \
1766*4882a593Smuzhiyun } while (0)
1767*4882a593Smuzhiyun #else
1768*4882a593Smuzhiyun #define DHD_OS_SCAN_WAKE_LOCK_TIMEOUT(pub, val) dhd_os_scan_wake_lock_timeout(pub, val)
1769*4882a593Smuzhiyun #define DHD_OS_SCAN_WAKE_UNLOCK(pub) dhd_os_scan_wake_unlock(pub)
1770*4882a593Smuzhiyun #endif /* DHD_DEBUG_SCAN_WAKELOCK */
1771*4882a593Smuzhiyun #else
1772*4882a593Smuzhiyun #define DHD_OS_SCAN_WAKE_LOCK_TIMEOUT(pub, val)
1773*4882a593Smuzhiyun #define DHD_OS_SCAN_WAKE_UNLOCK(pub)
1774*4882a593Smuzhiyun #endif /* DHD_USE_SCAN_WAKELOCK */
1775*4882a593Smuzhiyun
1776*4882a593Smuzhiyun #else
1777*4882a593Smuzhiyun
1778*4882a593Smuzhiyun /* Wake lock are used in Android only (until the Linux community accepts it) */
1779*4882a593Smuzhiyun #define DHD_OS_WAKE_LOCK(pub)
1780*4882a593Smuzhiyun #define DHD_OS_WAKE_UNLOCK(pub)
1781*4882a593Smuzhiyun #define DHD_EVENT_WAKE_LOCK(pub)
1782*4882a593Smuzhiyun #define DHD_EVENT_WAKE_UNLOCK(pub)
1783*4882a593Smuzhiyun #define DHD_PM_WAKE_LOCK_TIMEOUT(pub, val)
1784*4882a593Smuzhiyun #define DHD_PM_WAKE_UNLOCK(pub)
1785*4882a593Smuzhiyun #define DHD_TXFL_WAKE_LOCK_TIMEOUT(pub, val)
1786*4882a593Smuzhiyun #define DHD_TXFL_WAKE_UNLOCK(pub)
1787*4882a593Smuzhiyun #define DHD_OS_WD_WAKE_LOCK(pub)
1788*4882a593Smuzhiyun #define DHD_OS_WD_WAKE_UNLOCK(pub)
1789*4882a593Smuzhiyun #define DHD_OS_WAKE_LOCK_TIMEOUT(pub)
1790*4882a593Smuzhiyun #define DHD_OS_WAKE_LOCK_RX_TIMEOUT_ENABLE(pub, val) UNUSED_PARAMETER(val)
1791*4882a593Smuzhiyun #define DHD_OS_WAKE_LOCK_CTRL_TIMEOUT_ENABLE(pub, val) UNUSED_PARAMETER(val)
1792*4882a593Smuzhiyun #define DHD_OS_WAKE_LOCK_CTRL_TIMEOUT_CANCEL(pub, val)
1793*4882a593Smuzhiyun #define DHD_OS_WAKE_LOCK_WAIVE(pub)
1794*4882a593Smuzhiyun #define DHD_OS_WAKE_LOCK_RESTORE(pub)
1795*4882a593Smuzhiyun #define DHD_OS_SCAN_WAKE_LOCK_TIMEOUT(pub, val)
1796*4882a593Smuzhiyun #define DHD_OS_SCAN_WAKE_UNLOCK(pub)
1797*4882a593Smuzhiyun #define DHD_OS_WAKE_LOCK_INIT(dhd)
1798*4882a593Smuzhiyun #define DHD_OS_WAKE_LOCK_DESTROY(dhd)
1799*4882a593Smuzhiyun
1800*4882a593Smuzhiyun #endif // endif
1801*4882a593Smuzhiyun
1802*4882a593Smuzhiyun #ifdef BCMPCIE_OOB_HOST_WAKE
1803*4882a593Smuzhiyun #define OOB_WAKE_LOCK_TIMEOUT 500
1804*4882a593Smuzhiyun extern void dhd_os_oob_irq_wake_lock_timeout(dhd_pub_t *pub, int val);
1805*4882a593Smuzhiyun extern void dhd_os_oob_irq_wake_unlock(dhd_pub_t *pub);
1806*4882a593Smuzhiyun
1807*4882a593Smuzhiyun #define DHD_OS_OOB_IRQ_WAKE_LOCK_TIMEOUT(pub, val) dhd_os_oob_irq_wake_lock_timeout(pub, val)
1808*4882a593Smuzhiyun #define DHD_OS_OOB_IRQ_WAKE_UNLOCK(pub) dhd_os_oob_irq_wake_unlock(pub)
1809*4882a593Smuzhiyun #endif /* BCMPCIE_OOB_HOST_WAKE */
1810*4882a593Smuzhiyun
1811*4882a593Smuzhiyun #define DHD_PACKET_TIMEOUT_MS 500
1812*4882a593Smuzhiyun #define DHD_EVENT_TIMEOUT_MS 1500
1813*4882a593Smuzhiyun #define SCAN_WAKE_LOCK_TIMEOUT 10000
1814*4882a593Smuzhiyun #define MAX_TX_TIMEOUT 500
1815*4882a593Smuzhiyun
1816*4882a593Smuzhiyun /* Enum for IOCTL recieved status */
1817*4882a593Smuzhiyun typedef enum dhd_ioctl_recieved_status
1818*4882a593Smuzhiyun {
1819*4882a593Smuzhiyun IOCTL_WAIT = 0,
1820*4882a593Smuzhiyun IOCTL_RETURN_ON_SUCCESS,
1821*4882a593Smuzhiyun IOCTL_RETURN_ON_TRAP,
1822*4882a593Smuzhiyun IOCTL_RETURN_ON_BUS_STOP,
1823*4882a593Smuzhiyun IOCTL_RETURN_ON_ERROR
1824*4882a593Smuzhiyun } dhd_ioctl_recieved_status_t;
1825*4882a593Smuzhiyun
1826*4882a593Smuzhiyun /* interface operations (register, remove) should be atomic, use this lock to prevent race
1827*4882a593Smuzhiyun * condition among wifi on/off and interface operation functions
1828*4882a593Smuzhiyun */
1829*4882a593Smuzhiyun void dhd_net_if_lock(struct net_device *dev);
1830*4882a593Smuzhiyun void dhd_net_if_unlock(struct net_device *dev);
1831*4882a593Smuzhiyun
1832*4882a593Smuzhiyun #if defined(MULTIPLE_SUPPLICANT)
1833*4882a593Smuzhiyun #if defined(OEM_ANDROID) && defined(BCMSDIO)
1834*4882a593Smuzhiyun extern struct mutex _dhd_sdio_mutex_lock_;
1835*4882a593Smuzhiyun #endif // endif
1836*4882a593Smuzhiyun #endif /* MULTIPLE_SUPPLICANT */
1837*4882a593Smuzhiyun
1838*4882a593Smuzhiyun typedef enum dhd_attach_states
1839*4882a593Smuzhiyun {
1840*4882a593Smuzhiyun DHD_ATTACH_STATE_INIT = 0x0,
1841*4882a593Smuzhiyun DHD_ATTACH_STATE_NET_ALLOC = 0x1,
1842*4882a593Smuzhiyun DHD_ATTACH_STATE_DHD_ALLOC = 0x2,
1843*4882a593Smuzhiyun DHD_ATTACH_STATE_ADD_IF = 0x4,
1844*4882a593Smuzhiyun DHD_ATTACH_STATE_PROT_ATTACH = 0x8,
1845*4882a593Smuzhiyun DHD_ATTACH_STATE_WL_ATTACH = 0x10,
1846*4882a593Smuzhiyun DHD_ATTACH_STATE_THREADS_CREATED = 0x20,
1847*4882a593Smuzhiyun DHD_ATTACH_STATE_WAKELOCKS_INIT = 0x40,
1848*4882a593Smuzhiyun DHD_ATTACH_STATE_CFG80211 = 0x80,
1849*4882a593Smuzhiyun DHD_ATTACH_STATE_EARLYSUSPEND_DONE = 0x100,
1850*4882a593Smuzhiyun DHD_ATTACH_TIMESYNC_ATTACH_DONE = 0x200,
1851*4882a593Smuzhiyun DHD_ATTACH_LOGTRACE_INIT = 0x400,
1852*4882a593Smuzhiyun DHD_ATTACH_STATE_LB_ATTACH_DONE = 0x800,
1853*4882a593Smuzhiyun DHD_ATTACH_STATE_DONE = 0x1000
1854*4882a593Smuzhiyun } dhd_attach_states_t;
1855*4882a593Smuzhiyun
1856*4882a593Smuzhiyun /* Value -1 means we are unsuccessful in creating the kthread. */
1857*4882a593Smuzhiyun #define DHD_PID_KT_INVALID -1
1858*4882a593Smuzhiyun /* Value -2 means we are unsuccessful in both creating the kthread and tasklet */
1859*4882a593Smuzhiyun #define DHD_PID_KT_TL_INVALID -2
1860*4882a593Smuzhiyun
1861*4882a593Smuzhiyun /* default reporting period */
1862*4882a593Smuzhiyun #define ECOUNTERS_DEFAULT_PERIOD 0
1863*4882a593Smuzhiyun
1864*4882a593Smuzhiyun /* default number of reports. '0' indicates forever */
1865*4882a593Smuzhiyun #define ECOUNTERS_NUM_REPORTS 0
1866*4882a593Smuzhiyun
1867*4882a593Smuzhiyun typedef struct ecounters_cfg {
1868*4882a593Smuzhiyun uint16 type;
1869*4882a593Smuzhiyun uint16 if_slice_idx;
1870*4882a593Smuzhiyun uint16 stats_rep;
1871*4882a593Smuzhiyun } ecounters_cfg_t;
1872*4882a593Smuzhiyun
1873*4882a593Smuzhiyun typedef struct event_ecounters_cfg {
1874*4882a593Smuzhiyun uint16 event_id;
1875*4882a593Smuzhiyun uint16 type;
1876*4882a593Smuzhiyun uint16 if_slice_idx;
1877*4882a593Smuzhiyun uint16 stats_rep;
1878*4882a593Smuzhiyun } event_ecounters_cfg_t;
1879*4882a593Smuzhiyun
1880*4882a593Smuzhiyun typedef struct ecountersv2_xtlv_list_elt {
1881*4882a593Smuzhiyun /* Not quite the exact bcm_xtlv_t type as data could be pointing to other pieces in
1882*4882a593Smuzhiyun * memory at the time of parsing arguments.
1883*4882a593Smuzhiyun */
1884*4882a593Smuzhiyun uint16 id;
1885*4882a593Smuzhiyun uint16 len;
1886*4882a593Smuzhiyun uint8 *data;
1887*4882a593Smuzhiyun struct ecountersv2_xtlv_list_elt *next;
1888*4882a593Smuzhiyun } ecountersv2_xtlv_list_elt_t;
1889*4882a593Smuzhiyun
1890*4882a593Smuzhiyun typedef struct ecountersv2_processed_xtlv_list_elt {
1891*4882a593Smuzhiyun uint8 *data;
1892*4882a593Smuzhiyun struct ecountersv2_processed_xtlv_list_elt *next;
1893*4882a593Smuzhiyun } ecountersv2_processed_xtlv_list_elt;
1894*4882a593Smuzhiyun
1895*4882a593Smuzhiyun /*
1896*4882a593Smuzhiyun * Exported from dhd OS modules (dhd_linux/dhd_ndis)
1897*4882a593Smuzhiyun */
1898*4882a593Smuzhiyun
1899*4882a593Smuzhiyun /* Indication from bus module regarding presence/insertion of dongle.
1900*4882a593Smuzhiyun * Return dhd_pub_t pointer, used as handle to OS module in later calls.
1901*4882a593Smuzhiyun * Returned structure should have bus and prot pointers filled in.
1902*4882a593Smuzhiyun * bus_hdrlen specifies required headroom for bus module header.
1903*4882a593Smuzhiyun */
1904*4882a593Smuzhiyun extern dhd_pub_t *dhd_attach(osl_t *osh, struct dhd_bus *bus, uint bus_hdrlen);
1905*4882a593Smuzhiyun extern int dhd_attach_net(dhd_pub_t *dhdp, bool need_rtnl_lock);
1906*4882a593Smuzhiyun #if defined(WLP2P) && defined(WL_CFG80211)
1907*4882a593Smuzhiyun /* To allow attach/detach calls corresponding to p2p0 interface */
1908*4882a593Smuzhiyun extern int dhd_attach_p2p(dhd_pub_t *);
1909*4882a593Smuzhiyun extern int dhd_detach_p2p(dhd_pub_t *);
1910*4882a593Smuzhiyun #endif /* WLP2P && WL_CFG80211 */
1911*4882a593Smuzhiyun extern int dhd_register_if(dhd_pub_t *dhdp, int idx, bool need_rtnl_lock);
1912*4882a593Smuzhiyun #ifdef WL_VIF_SUPPORT
1913*4882a593Smuzhiyun extern int dhd_register_vif(dhd_pub_t *dhdp);
1914*4882a593Smuzhiyun #endif /* WL_VIF_SUPPORT */
1915*4882a593Smuzhiyun
1916*4882a593Smuzhiyun /* Indication from bus module regarding removal/absence of dongle */
1917*4882a593Smuzhiyun extern void dhd_detach(dhd_pub_t *dhdp);
1918*4882a593Smuzhiyun extern void dhd_free(dhd_pub_t *dhdp);
1919*4882a593Smuzhiyun extern void dhd_clear(dhd_pub_t *dhdp);
1920*4882a593Smuzhiyun
1921*4882a593Smuzhiyun /* Indication from bus module to change flow-control state */
1922*4882a593Smuzhiyun extern void dhd_txflowcontrol(dhd_pub_t *dhdp, int ifidx, bool on);
1923*4882a593Smuzhiyun
1924*4882a593Smuzhiyun /* Store the status of a connection attempt for later retrieval by an iovar */
1925*4882a593Smuzhiyun extern void dhd_store_conn_status(uint32 event, uint32 status, uint32 reason);
1926*4882a593Smuzhiyun
1927*4882a593Smuzhiyun extern bool dhd_prec_enq(dhd_pub_t *dhdp, struct pktq *q, void *pkt, int prec);
1928*4882a593Smuzhiyun
1929*4882a593Smuzhiyun extern void dhd_rx_frame(dhd_pub_t *dhdp, int ifidx, void *rxp, int numpkt, uint8 chan);
1930*4882a593Smuzhiyun
1931*4882a593Smuzhiyun /* Return pointer to interface name */
1932*4882a593Smuzhiyun extern char *dhd_ifname(dhd_pub_t *dhdp, int idx);
1933*4882a593Smuzhiyun
1934*4882a593Smuzhiyun #ifdef DHD_UCODE_DOWNLOAD
1935*4882a593Smuzhiyun /* Returns the ucode path */
1936*4882a593Smuzhiyun extern char *dhd_get_ucode_path(dhd_pub_t *dhdp);
1937*4882a593Smuzhiyun #endif /* DHD_UCODE_DOWNLOAD */
1938*4882a593Smuzhiyun
1939*4882a593Smuzhiyun /* Request scheduling of the bus dpc */
1940*4882a593Smuzhiyun extern void dhd_sched_dpc(dhd_pub_t *dhdp);
1941*4882a593Smuzhiyun
1942*4882a593Smuzhiyun /* Notify tx completion */
1943*4882a593Smuzhiyun extern void dhd_txcomplete(dhd_pub_t *dhdp, void *txp, bool success);
1944*4882a593Smuzhiyun #ifdef DHD_4WAYM4_FAIL_DISCONNECT
1945*4882a593Smuzhiyun extern void dhd_eap_txcomplete(dhd_pub_t *dhdp, void *txp, bool success, int ifidx);
1946*4882a593Smuzhiyun extern void dhd_cleanup_m4_state_work(dhd_pub_t *dhdp, int ifidx);
1947*4882a593Smuzhiyun #endif /* DHD_4WAYM4_FAIL_DISCONNECT */
1948*4882a593Smuzhiyun
1949*4882a593Smuzhiyun #ifdef DHD_PCIE_NATIVE_RUNTIMEPM
1950*4882a593Smuzhiyun extern void dhd_bus_wakeup_work(dhd_pub_t *dhdp);
1951*4882a593Smuzhiyun #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
1952*4882a593Smuzhiyun
1953*4882a593Smuzhiyun #define WIFI_FEATURE_INFRA 0x0001 /* Basic infrastructure mode */
1954*4882a593Smuzhiyun #define WIFI_FEATURE_INFRA_5G 0x0002 /* Support for 5 GHz Band */
1955*4882a593Smuzhiyun #define WIFI_FEATURE_HOTSPOT 0x0004 /* Support for GAS/ANQP */
1956*4882a593Smuzhiyun #define WIFI_FEATURE_P2P 0x0008 /* Wifi-Direct */
1957*4882a593Smuzhiyun #define WIFI_FEATURE_SOFT_AP 0x0010 /* Soft AP */
1958*4882a593Smuzhiyun #define WIFI_FEATURE_GSCAN 0x0020 /* Google-Scan APIs */
1959*4882a593Smuzhiyun #define WIFI_FEATURE_NAN 0x0040 /* Neighbor Awareness Networking */
1960*4882a593Smuzhiyun #define WIFI_FEATURE_D2D_RTT 0x0080 /* Device-to-device RTT */
1961*4882a593Smuzhiyun #define WIFI_FEATURE_D2AP_RTT 0x0100 /* Device-to-AP RTT */
1962*4882a593Smuzhiyun #define WIFI_FEATURE_BATCH_SCAN 0x0200 /* Batched Scan (legacy) */
1963*4882a593Smuzhiyun #define WIFI_FEATURE_PNO 0x0400 /* Preferred network offload */
1964*4882a593Smuzhiyun #define WIFI_FEATURE_ADDITIONAL_STA 0x0800 /* Support for two STAs */
1965*4882a593Smuzhiyun #define WIFI_FEATURE_TDLS 0x1000 /* Tunnel directed link setup */
1966*4882a593Smuzhiyun #define WIFI_FEATURE_TDLS_OFFCHANNEL 0x2000 /* Support for TDLS off channel */
1967*4882a593Smuzhiyun #define WIFI_FEATURE_EPR 0x4000 /* Enhanced power reporting */
1968*4882a593Smuzhiyun #define WIFI_FEATURE_AP_STA 0x8000 /* Support for AP STA Concurrency */
1969*4882a593Smuzhiyun #define WIFI_FEATURE_LINKSTAT 0x10000 /* Support for Linkstats */
1970*4882a593Smuzhiyun #define WIFI_FEATURE_LOGGER 0x20000 /* WiFi Logger */
1971*4882a593Smuzhiyun #define WIFI_FEATURE_HAL_EPNO 0x40000 /* WiFi PNO enhanced */
1972*4882a593Smuzhiyun #define WIFI_FEATURE_RSSI_MONITOR 0x80000 /* RSSI Monitor */
1973*4882a593Smuzhiyun #define WIFI_FEATURE_MKEEP_ALIVE 0x100000 /* WiFi mkeep_alive */
1974*4882a593Smuzhiyun #define WIFI_FEATURE_CONFIG_NDO 0x200000 /* ND offload configure */
1975*4882a593Smuzhiyun #define WIFI_FEATURE_TX_TRANSMIT_POWER 0x400000 /* Capture Tx transmit power levels */
1976*4882a593Smuzhiyun #define WIFI_FEATURE_CONTROL_ROAMING 0x800000 /* Enable/Disable firmware roaming */
1977*4882a593Smuzhiyun #define WIFI_FEATURE_FILTER_IE 0x1000000 /* Probe req ie filter */
1978*4882a593Smuzhiyun #define WIFI_FEATURE_SCAN_RAND 0x2000000 /* Support MAC & Prb SN randomization */
1979*4882a593Smuzhiyun #define WIFI_FEATURE_SET_TX_POWER_LIMIT 0x4000000 /* Support Tx Power Limit setting */
1980*4882a593Smuzhiyun #define WIFI_FEATURE_USE_BODY_HEAD_SAR 0x8000000 /* Body/Head Proximity for SAR */
1981*4882a593Smuzhiyun #define WIFI_FEATURE_SET_LATENCY_MODE 0x40000000 /* Support Latency mode setting */
1982*4882a593Smuzhiyun #define WIFI_FEATURE_P2P_RAND_MAC 0x80000000 /* Support P2P MAC randomization */
1983*4882a593Smuzhiyun #define WIFI_FEATURE_INVALID 0xFFFFFFFF /* Invalid Feature */
1984*4882a593Smuzhiyun
1985*4882a593Smuzhiyun #define MAX_FEATURE_SET_CONCURRRENT_GROUPS 3
1986*4882a593Smuzhiyun
1987*4882a593Smuzhiyun extern int dhd_dev_get_feature_set(struct net_device *dev);
1988*4882a593Smuzhiyun extern int dhd_dev_get_feature_set_matrix(struct net_device *dev, int num);
1989*4882a593Smuzhiyun extern int dhd_dev_cfg_rand_mac_oui(struct net_device *dev, uint8 *oui);
1990*4882a593Smuzhiyun #ifdef CUSTOM_FORCE_NODFS_FLAG
1991*4882a593Smuzhiyun extern int dhd_dev_set_nodfs(struct net_device *dev, uint nodfs);
1992*4882a593Smuzhiyun #endif /* CUSTOM_FORCE_NODFS_FLAG */
1993*4882a593Smuzhiyun #ifdef NDO_CONFIG_SUPPORT
1994*4882a593Smuzhiyun #ifndef NDO_MAX_HOST_IP_ENTRIES
1995*4882a593Smuzhiyun #define NDO_MAX_HOST_IP_ENTRIES 10
1996*4882a593Smuzhiyun #endif /* NDO_MAX_HOST_IP_ENTRIES */
1997*4882a593Smuzhiyun
1998*4882a593Smuzhiyun extern int dhd_dev_ndo_cfg(struct net_device *dev, u8 enable);
1999*4882a593Smuzhiyun extern int dhd_dev_ndo_update_inet6addr(struct net_device * dev);
2000*4882a593Smuzhiyun #endif /* NDO_CONFIG_SUPPORT */
2001*4882a593Smuzhiyun extern int dhd_set_rand_mac_oui(dhd_pub_t *dhd);
2002*4882a593Smuzhiyun #ifdef GSCAN_SUPPORT
2003*4882a593Smuzhiyun extern int dhd_dev_set_lazy_roam_cfg(struct net_device *dev,
2004*4882a593Smuzhiyun wlc_roam_exp_params_t *roam_param);
2005*4882a593Smuzhiyun extern int dhd_dev_lazy_roam_enable(struct net_device *dev, uint32 enable);
2006*4882a593Smuzhiyun extern int dhd_dev_set_lazy_roam_bssid_pref(struct net_device *dev,
2007*4882a593Smuzhiyun wl_bssid_pref_cfg_t *bssid_pref, uint32 flush);
2008*4882a593Smuzhiyun #endif /* GSCAN_SUPPORT */
2009*4882a593Smuzhiyun #if defined(GSCAN_SUPPORT) || defined(ROAMEXP_SUPPORT)
2010*4882a593Smuzhiyun extern int dhd_dev_set_blacklist_bssid(struct net_device *dev, maclist_t *blacklist,
2011*4882a593Smuzhiyun uint32 len, uint32 flush);
2012*4882a593Smuzhiyun extern int dhd_dev_set_whitelist_ssid(struct net_device *dev, wl_ssid_whitelist_t *whitelist,
2013*4882a593Smuzhiyun uint32 len, uint32 flush);
2014*4882a593Smuzhiyun #endif /* GSCAN_SUPPORT || ROAMEXP_SUPPORT */
2015*4882a593Smuzhiyun
2016*4882a593Smuzhiyun /* OS independent layer functions */
2017*4882a593Smuzhiyun extern void dhd_os_dhdiovar_lock(dhd_pub_t *pub);
2018*4882a593Smuzhiyun extern void dhd_os_dhdiovar_unlock(dhd_pub_t *pub);
2019*4882a593Smuzhiyun void dhd_os_logdump_lock(dhd_pub_t *pub);
2020*4882a593Smuzhiyun void dhd_os_logdump_unlock(dhd_pub_t *pub);
2021*4882a593Smuzhiyun extern int dhd_os_proto_block(dhd_pub_t * pub);
2022*4882a593Smuzhiyun extern int dhd_os_proto_unblock(dhd_pub_t * pub);
2023*4882a593Smuzhiyun extern int dhd_os_ioctl_resp_wait(dhd_pub_t * pub, uint * condition);
2024*4882a593Smuzhiyun extern int dhd_os_ioctl_resp_wake(dhd_pub_t * pub);
2025*4882a593Smuzhiyun extern unsigned int dhd_os_get_ioctl_resp_timeout(void);
2026*4882a593Smuzhiyun extern void dhd_os_set_ioctl_resp_timeout(unsigned int timeout_msec);
2027*4882a593Smuzhiyun extern void dhd_os_ioctl_resp_lock(dhd_pub_t * pub);
2028*4882a593Smuzhiyun extern void dhd_os_ioctl_resp_unlock(dhd_pub_t * pub);
2029*4882a593Smuzhiyun #ifdef PCIE_FULL_DONGLE
2030*4882a593Smuzhiyun extern void dhd_wakeup_ioctl_event(dhd_pub_t *pub, dhd_ioctl_recieved_status_t reason);
2031*4882a593Smuzhiyun #else
dhd_wakeup_ioctl_event(dhd_pub_t * pub,dhd_ioctl_recieved_status_t reason)2032*4882a593Smuzhiyun static INLINE void dhd_wakeup_ioctl_event(dhd_pub_t *pub, dhd_ioctl_recieved_status_t reason)
2033*4882a593Smuzhiyun { printf("%s is NOT implemented for SDIO", __FUNCTION__); return; }
2034*4882a593Smuzhiyun #endif // endif
2035*4882a593Smuzhiyun #ifdef SHOW_LOGTRACE
2036*4882a593Smuzhiyun /* Bound and delay are fine tuned after several experiments and these
2037*4882a593Smuzhiyun * are the best case values to handle bombarding of console logs.
2038*4882a593Smuzhiyun */
2039*4882a593Smuzhiyun #define DHD_EVENT_LOGTRACE_BOUND 10
2040*4882a593Smuzhiyun /* since FW has event log rate health check (EVENT_LOG_RATE_HC) we can reduce
2041*4882a593Smuzhiyun * the reschedule delay to 10ms
2042*4882a593Smuzhiyun */
2043*4882a593Smuzhiyun #define DHD_EVENT_LOGTRACE_RESCHEDULE_DELAY_MS 10u
2044*4882a593Smuzhiyun extern int dhd_os_read_file(void *file, char *buf, uint32 size);
2045*4882a593Smuzhiyun extern int dhd_os_seek_file(void *file, int64 offset);
2046*4882a593Smuzhiyun void dhd_sendup_info_buf(dhd_pub_t *dhdp, uint8 *msg);
2047*4882a593Smuzhiyun #endif /* SHOW_LOGTRACE */
2048*4882a593Smuzhiyun int dhd_os_write_file_posn(void *fp, unsigned long *posn,
2049*4882a593Smuzhiyun void *buf, unsigned long buflen);
2050*4882a593Smuzhiyun int dhd_msix_message_set(dhd_pub_t *dhdp, uint table_entry,
2051*4882a593Smuzhiyun uint message_number, bool unmask);
2052*4882a593Smuzhiyun
2053*4882a593Smuzhiyun extern void
2054*4882a593Smuzhiyun dhd_pcie_dump_core_regs(dhd_pub_t * pub, uint32 index, uint32 first_addr, uint32 last_addr);
2055*4882a593Smuzhiyun extern void wl_dhdpcie_dump_regs(void * context);
2056*4882a593Smuzhiyun
2057*4882a593Smuzhiyun extern int dhd_os_get_image_block(char * buf, int len, void * image);
2058*4882a593Smuzhiyun extern int dhd_os_get_image_size(void * image);
2059*4882a593Smuzhiyun #if defined(BT_OVER_SDIO)
2060*4882a593Smuzhiyun extern int dhd_os_gets_image(dhd_pub_t *pub, char *str, int len, void *image);
2061*4882a593Smuzhiyun extern void dhdsdio_bus_usr_cnt_inc(dhd_pub_t *pub);
2062*4882a593Smuzhiyun extern void dhdsdio_bus_usr_cnt_dec(dhd_pub_t *pub);
2063*4882a593Smuzhiyun #endif /* (BT_OVER_SDIO) */
2064*4882a593Smuzhiyun extern void *dhd_os_open_image1(dhd_pub_t *pub, char *filename); /* rev1 function signature */
2065*4882a593Smuzhiyun extern void dhd_os_close_image1(dhd_pub_t *pub, void *image);
2066*4882a593Smuzhiyun extern void dhd_os_wd_timer(void *bus, uint wdtick);
2067*4882a593Smuzhiyun #ifdef DHD_PCIE_RUNTIMEPM
2068*4882a593Smuzhiyun extern void dhd_os_runtimepm_timer(void *bus, uint tick);
2069*4882a593Smuzhiyun #endif /* DHD_PCIE_RUNTIMEPM */
2070*4882a593Smuzhiyun extern void dhd_os_sdlock(dhd_pub_t * pub);
2071*4882a593Smuzhiyun extern void dhd_os_sdunlock(dhd_pub_t * pub);
2072*4882a593Smuzhiyun extern void dhd_os_sdlock_txq(dhd_pub_t * pub);
2073*4882a593Smuzhiyun extern void dhd_os_sdunlock_txq(dhd_pub_t * pub);
2074*4882a593Smuzhiyun extern void dhd_os_sdlock_rxq(dhd_pub_t * pub);
2075*4882a593Smuzhiyun extern void dhd_os_sdunlock_rxq(dhd_pub_t * pub);
2076*4882a593Smuzhiyun extern void dhd_os_sdlock_sndup_rxq(dhd_pub_t * pub);
2077*4882a593Smuzhiyun extern void dhd_os_tracelog(const char *format, ...);
2078*4882a593Smuzhiyun #ifdef DHDTCPACK_SUPPRESS
2079*4882a593Smuzhiyun extern unsigned long dhd_os_tcpacklock(dhd_pub_t *pub);
2080*4882a593Smuzhiyun extern void dhd_os_tcpackunlock(dhd_pub_t *pub, unsigned long flags);
2081*4882a593Smuzhiyun #endif /* DHDTCPACK_SUPPRESS */
2082*4882a593Smuzhiyun
2083*4882a593Smuzhiyun extern int dhd_customer_oob_irq_map(void *adapter, unsigned long *irq_flags_ptr);
2084*4882a593Smuzhiyun extern int dhd_customer_gpio_wlan_ctrl(void *adapter, int onoff);
2085*4882a593Smuzhiyun extern int dhd_custom_get_mac_address(void *adapter, unsigned char *buf);
2086*4882a593Smuzhiyun #if defined(CUSTOM_COUNTRY_CODE)
2087*4882a593Smuzhiyun extern void get_customized_country_code(void *adapter, char *country_iso_code,
2088*4882a593Smuzhiyun wl_country_t *cspec, u32 flags);
2089*4882a593Smuzhiyun #else
2090*4882a593Smuzhiyun extern void get_customized_country_code(void *adapter, char *country_iso_code, wl_country_t *cspec);
2091*4882a593Smuzhiyun #endif /* CUSTOM_COUNTRY_CODE */
2092*4882a593Smuzhiyun extern void dhd_os_sdunlock_sndup_rxq(dhd_pub_t * pub);
2093*4882a593Smuzhiyun extern void dhd_os_sdlock_eventq(dhd_pub_t * pub);
2094*4882a593Smuzhiyun extern void dhd_os_sdunlock_eventq(dhd_pub_t * pub);
2095*4882a593Smuzhiyun extern bool dhd_os_check_hang(dhd_pub_t *dhdp, int ifidx, int ret);
2096*4882a593Smuzhiyun extern int dhd_os_send_hang_message(dhd_pub_t *dhdp);
2097*4882a593Smuzhiyun extern void dhd_set_version_info(dhd_pub_t *pub, char *fw);
2098*4882a593Smuzhiyun extern bool dhd_os_check_if_up(dhd_pub_t *pub);
2099*4882a593Smuzhiyun extern int dhd_os_check_wakelock(dhd_pub_t *pub);
2100*4882a593Smuzhiyun extern int dhd_os_check_wakelock_all(dhd_pub_t *pub);
2101*4882a593Smuzhiyun extern int dhd_get_instance(dhd_pub_t *pub);
2102*4882a593Smuzhiyun #ifdef CUSTOM_SET_CPUCORE
2103*4882a593Smuzhiyun extern void dhd_set_cpucore(dhd_pub_t *dhd, int set);
2104*4882a593Smuzhiyun #endif /* CUSTOM_SET_CPUCORE */
2105*4882a593Smuzhiyun
2106*4882a593Smuzhiyun #if defined(KEEP_ALIVE)
2107*4882a593Smuzhiyun extern int dhd_keep_alive_onoff(dhd_pub_t *dhd);
2108*4882a593Smuzhiyun #endif /* KEEP_ALIVE */
2109*4882a593Smuzhiyun
2110*4882a593Smuzhiyun #if defined(DHD_FW_COREDUMP)
2111*4882a593Smuzhiyun void dhd_schedule_memdump(dhd_pub_t *dhdp, uint8 *buf, uint32 size);
2112*4882a593Smuzhiyun #endif /* DHD_FW_COREDUMP */
2113*4882a593Smuzhiyun
2114*4882a593Smuzhiyun void dhd_write_sssr_dump(dhd_pub_t *dhdp, uint32 dump_mode);
2115*4882a593Smuzhiyun #ifdef DNGL_AXI_ERROR_LOGGING
2116*4882a593Smuzhiyun void dhd_schedule_axi_error_dump(dhd_pub_t *dhdp, void *type);
2117*4882a593Smuzhiyun #endif /* DNGL_AXI_ERROR_LOGGING */
2118*4882a593Smuzhiyun #ifdef BCMPCIE
2119*4882a593Smuzhiyun void dhd_schedule_cto_recovery(dhd_pub_t *dhdp);
2120*4882a593Smuzhiyun #endif /* BCMPCIE */
2121*4882a593Smuzhiyun
2122*4882a593Smuzhiyun #ifdef PKT_FILTER_SUPPORT
2123*4882a593Smuzhiyun #define DHD_UNICAST_FILTER_NUM 0
2124*4882a593Smuzhiyun #define DHD_BROADCAST_FILTER_NUM 1
2125*4882a593Smuzhiyun #define DHD_MULTICAST4_FILTER_NUM 2
2126*4882a593Smuzhiyun #define DHD_MULTICAST6_FILTER_NUM 3
2127*4882a593Smuzhiyun #define DHD_MDNS_FILTER_NUM 4
2128*4882a593Smuzhiyun #define DHD_ARP_FILTER_NUM 5
2129*4882a593Smuzhiyun #define DHD_BROADCAST_ARP_FILTER_NUM 6
2130*4882a593Smuzhiyun #define DHD_IP4BCAST_DROP_FILTER_NUM 7
2131*4882a593Smuzhiyun #define DHD_LLC_STP_DROP_FILTER_NUM 8
2132*4882a593Smuzhiyun #define DHD_LLC_XID_DROP_FILTER_NUM 9
2133*4882a593Smuzhiyun #define DISCARD_IPV4_MCAST "102 1 6 IP4_H:16 0xf0 0xe0"
2134*4882a593Smuzhiyun #define DISCARD_IPV6_MCAST "103 1 6 IP6_H:24 0xff 0xff"
2135*4882a593Smuzhiyun #define DISCARD_IPV4_BCAST "107 1 6 IP4_H:16 0xffffffff 0xffffffff"
2136*4882a593Smuzhiyun #define DISCARD_LLC_STP "108 1 6 ETH_H:14 0xFFFFFFFFFFFF 0xAAAA0300000C"
2137*4882a593Smuzhiyun #define DISCARD_LLC_XID "109 1 6 ETH_H:14 0xFFFFFF 0x0001AF"
2138*4882a593Smuzhiyun extern int dhd_os_enable_packet_filter(dhd_pub_t *dhdp, int val);
2139*4882a593Smuzhiyun extern void dhd_enable_packet_filter(int value, dhd_pub_t *dhd);
2140*4882a593Smuzhiyun extern int dhd_packet_filter_add_remove(dhd_pub_t *dhdp, int add_remove, int num);
2141*4882a593Smuzhiyun extern int net_os_enable_packet_filter(struct net_device *dev, int val);
2142*4882a593Smuzhiyun extern int net_os_rxfilter_add_remove(struct net_device *dev, int val, int num);
2143*4882a593Smuzhiyun
2144*4882a593Smuzhiyun #define MAX_PKTFLT_BUF_SIZE 2048
2145*4882a593Smuzhiyun #define MAX_PKTFLT_FIXED_PATTERN_SIZE 32
2146*4882a593Smuzhiyun #define MAX_PKTFLT_FIXED_BUF_SIZE \
2147*4882a593Smuzhiyun (WL_PKT_FILTER_FIXED_LEN + MAX_PKTFLT_FIXED_PATTERN_SIZE * 2)
2148*4882a593Smuzhiyun #define MAXPKT_ARG 16
2149*4882a593Smuzhiyun #endif /* PKT_FILTER_SUPPORT */
2150*4882a593Smuzhiyun
2151*4882a593Smuzhiyun #if defined(OEM_ANDROID) && defined(BCMPCIE)
2152*4882a593Smuzhiyun extern int dhd_get_suspend_bcn_li_dtim(dhd_pub_t *dhd, int *dtim_period, int *bcn_interval);
2153*4882a593Smuzhiyun #else
2154*4882a593Smuzhiyun extern int dhd_get_suspend_bcn_li_dtim(dhd_pub_t *dhd);
2155*4882a593Smuzhiyun #endif /* OEM_ANDROID && BCMPCIE */
2156*4882a593Smuzhiyun
2157*4882a593Smuzhiyun extern bool dhd_support_sta_mode(dhd_pub_t *dhd);
2158*4882a593Smuzhiyun extern int write_to_file(dhd_pub_t *dhd, uint8 *buf, int size);
2159*4882a593Smuzhiyun
2160*4882a593Smuzhiyun #ifdef RSSI_MONITOR_SUPPORT
2161*4882a593Smuzhiyun extern int dhd_dev_set_rssi_monitor_cfg(struct net_device *dev, int start,
2162*4882a593Smuzhiyun int8 max_rssi, int8 min_rssi);
2163*4882a593Smuzhiyun #endif /* RSSI_MONITOR_SUPPORT */
2164*4882a593Smuzhiyun
2165*4882a593Smuzhiyun #ifdef DHDTCPACK_SUPPRESS
2166*4882a593Smuzhiyun int dhd_dev_set_tcpack_sup_mode_cfg(struct net_device *dev, uint8 enable);
2167*4882a593Smuzhiyun #endif /* DHDTCPACK_SUPPRESS */
2168*4882a593Smuzhiyun
2169*4882a593Smuzhiyun #define DHD_RSSI_MONITOR_EVT_VERSION 1
2170*4882a593Smuzhiyun typedef struct {
2171*4882a593Smuzhiyun uint8 version;
2172*4882a593Smuzhiyun int8 cur_rssi;
2173*4882a593Smuzhiyun struct ether_addr BSSID;
2174*4882a593Smuzhiyun } dhd_rssi_monitor_evt_t;
2175*4882a593Smuzhiyun
2176*4882a593Smuzhiyun typedef struct {
2177*4882a593Smuzhiyun uint32 limit; /* Expiration time (usec) */
2178*4882a593Smuzhiyun uint32 increment; /* Current expiration increment (usec) */
2179*4882a593Smuzhiyun uint32 elapsed; /* Current elapsed time (usec) */
2180*4882a593Smuzhiyun uint32 tick; /* O/S tick time (usec) */
2181*4882a593Smuzhiyun } dhd_timeout_t;
2182*4882a593Smuzhiyun
2183*4882a593Smuzhiyun #ifdef SHOW_LOGTRACE
2184*4882a593Smuzhiyun typedef struct {
2185*4882a593Smuzhiyun uint num_fmts;
2186*4882a593Smuzhiyun char **fmts;
2187*4882a593Smuzhiyun char *raw_fmts;
2188*4882a593Smuzhiyun char *raw_sstr;
2189*4882a593Smuzhiyun uint32 fmts_size;
2190*4882a593Smuzhiyun uint32 raw_fmts_size;
2191*4882a593Smuzhiyun uint32 raw_sstr_size;
2192*4882a593Smuzhiyun uint32 ramstart;
2193*4882a593Smuzhiyun uint32 rodata_start;
2194*4882a593Smuzhiyun uint32 rodata_end;
2195*4882a593Smuzhiyun char *rom_raw_sstr;
2196*4882a593Smuzhiyun uint32 rom_raw_sstr_size;
2197*4882a593Smuzhiyun uint32 rom_ramstart;
2198*4882a593Smuzhiyun uint32 rom_rodata_start;
2199*4882a593Smuzhiyun uint32 rom_rodata_end;
2200*4882a593Smuzhiyun } dhd_event_log_t;
2201*4882a593Smuzhiyun #endif /* SHOW_LOGTRACE */
2202*4882a593Smuzhiyun
2203*4882a593Smuzhiyun #ifdef KEEP_ALIVE
2204*4882a593Smuzhiyun extern int dhd_dev_start_mkeep_alive(dhd_pub_t *dhd_pub, uint8 mkeep_alive_id, uint8 *ip_pkt,
2205*4882a593Smuzhiyun uint16 ip_pkt_len, uint8* src_mac_addr, uint8* dst_mac_addr, uint32 period_msec);
2206*4882a593Smuzhiyun extern int dhd_dev_stop_mkeep_alive(dhd_pub_t *dhd_pub, uint8 mkeep_alive_id);
2207*4882a593Smuzhiyun #endif /* KEEP_ALIVE */
2208*4882a593Smuzhiyun
2209*4882a593Smuzhiyun #if defined(PKT_FILTER_SUPPORT) && defined(APF)
2210*4882a593Smuzhiyun /*
2211*4882a593Smuzhiyun * As per Google's current implementation, there will be only one APF filter.
2212*4882a593Smuzhiyun * Therefore, userspace doesn't bother about filter id and because of that
2213*4882a593Smuzhiyun * DHD has to manage the filter id.
2214*4882a593Smuzhiyun */
2215*4882a593Smuzhiyun #define PKT_FILTER_APF_ID 200
2216*4882a593Smuzhiyun #define DHD_APF_LOCK(ndev) dhd_apf_lock(ndev)
2217*4882a593Smuzhiyun #define DHD_APF_UNLOCK(ndev) dhd_apf_unlock(ndev)
2218*4882a593Smuzhiyun
2219*4882a593Smuzhiyun extern void dhd_apf_lock(struct net_device *dev);
2220*4882a593Smuzhiyun extern void dhd_apf_unlock(struct net_device *dev);
2221*4882a593Smuzhiyun extern int dhd_dev_apf_get_version(struct net_device *ndev, uint32 *version);
2222*4882a593Smuzhiyun extern int dhd_dev_apf_get_max_len(struct net_device *ndev, uint32 *max_len);
2223*4882a593Smuzhiyun extern int dhd_dev_apf_add_filter(struct net_device *ndev, u8* program,
2224*4882a593Smuzhiyun uint32 program_len);
2225*4882a593Smuzhiyun extern int dhd_dev_apf_enable_filter(struct net_device *ndev);
2226*4882a593Smuzhiyun extern int dhd_dev_apf_disable_filter(struct net_device *ndev);
2227*4882a593Smuzhiyun extern int dhd_dev_apf_delete_filter(struct net_device *ndev);
2228*4882a593Smuzhiyun #endif /* PKT_FILTER_SUPPORT && APF */
2229*4882a593Smuzhiyun
2230*4882a593Smuzhiyun extern void dhd_timeout_start(dhd_timeout_t *tmo, uint usec);
2231*4882a593Smuzhiyun extern int dhd_timeout_expired(dhd_timeout_t *tmo);
2232*4882a593Smuzhiyun
2233*4882a593Smuzhiyun extern int dhd_ifname2idx(struct dhd_info *dhd, char *name);
2234*4882a593Smuzhiyun extern int dhd_net2idx(struct dhd_info *dhd, struct net_device *net);
2235*4882a593Smuzhiyun extern struct net_device * dhd_idx2net(void *pub, int ifidx);
2236*4882a593Smuzhiyun extern int net_os_send_hang_message(struct net_device *dev);
2237*4882a593Smuzhiyun extern int net_os_send_hang_message_reason(struct net_device *dev, const char *string_num);
2238*4882a593Smuzhiyun extern bool dhd_wowl_cap(void *bus);
2239*4882a593Smuzhiyun extern int wl_host_event(dhd_pub_t *dhd_pub, int *idx, void *pktdata, uint pktlen,
2240*4882a593Smuzhiyun wl_event_msg_t *, void **data_ptr, void *);
2241*4882a593Smuzhiyun extern int wl_process_host_event(dhd_pub_t *dhd_pub, int *idx, void *pktdata, uint pktlen,
2242*4882a593Smuzhiyun wl_event_msg_t *, void **data_ptr, void *);
2243*4882a593Smuzhiyun extern void wl_event_to_host_order(wl_event_msg_t * evt);
2244*4882a593Smuzhiyun extern int wl_host_event_get_data(void *pktdata, uint pktlen, bcm_event_msg_u_t *evu);
2245*4882a593Smuzhiyun extern int dhd_wl_ioctl(dhd_pub_t *dhd_pub, int ifindex, wl_ioctl_t *ioc, void *buf, int len);
2246*4882a593Smuzhiyun extern int dhd_wl_ioctl_cmd(dhd_pub_t *dhd_pub, int cmd, void *arg, int len, uint8 set,
2247*4882a593Smuzhiyun int ifindex);
2248*4882a593Smuzhiyun extern int dhd_wl_ioctl_get_intiovar(dhd_pub_t *dhd_pub, char *name, uint *pval,
2249*4882a593Smuzhiyun int cmd, uint8 set, int ifidx);
2250*4882a593Smuzhiyun extern int dhd_wl_ioctl_set_intiovar(dhd_pub_t *dhd_pub, char *name, uint val,
2251*4882a593Smuzhiyun int cmd, uint8 set, int ifidx);
2252*4882a593Smuzhiyun extern void dhd_common_init(osl_t *osh);
2253*4882a593Smuzhiyun
2254*4882a593Smuzhiyun extern int dhd_do_driver_init(struct net_device *net);
2255*4882a593Smuzhiyun extern int dhd_event_ifadd(struct dhd_info *dhd, struct wl_event_data_if *ifevent,
2256*4882a593Smuzhiyun char *name, uint8 *mac);
2257*4882a593Smuzhiyun extern int dhd_event_ifdel(struct dhd_info *dhd, struct wl_event_data_if *ifevent,
2258*4882a593Smuzhiyun char *name, uint8 *mac);
2259*4882a593Smuzhiyun extern int dhd_event_ifchange(struct dhd_info *dhd, struct wl_event_data_if *ifevent,
2260*4882a593Smuzhiyun char *name, uint8 *mac);
2261*4882a593Smuzhiyun extern struct net_device* dhd_allocate_if(dhd_pub_t *dhdpub, int ifidx, const char *name,
2262*4882a593Smuzhiyun uint8 *mac, uint8 bssidx, bool need_rtnl_lock, const char *dngl_name);
2263*4882a593Smuzhiyun extern int dhd_remove_if(dhd_pub_t *dhdpub, int ifidx, bool need_rtnl_lock);
2264*4882a593Smuzhiyun #ifdef WL_STATIC_IF
2265*4882a593Smuzhiyun extern s32 dhd_update_iflist_info(dhd_pub_t *dhdp, struct net_device *ndev, int ifidx,
2266*4882a593Smuzhiyun uint8 *mac, uint8 bssidx, const char *dngl_name, int if_state);
2267*4882a593Smuzhiyun #endif /* WL_STATIC_IF */
2268*4882a593Smuzhiyun extern void dhd_vif_add(struct dhd_info *dhd, int ifidx, char * name);
2269*4882a593Smuzhiyun extern void dhd_vif_del(struct dhd_info *dhd, int ifidx);
2270*4882a593Smuzhiyun extern void dhd_event(struct dhd_info *dhd, char *evpkt, int evlen, int ifidx);
2271*4882a593Smuzhiyun extern void dhd_vif_sendup(struct dhd_info *dhd, int ifidx, uchar *cp, int len);
2272*4882a593Smuzhiyun
2273*4882a593Smuzhiyun #ifdef WL_NATOE
2274*4882a593Smuzhiyun extern int dhd_natoe_ct_event(dhd_pub_t *dhd, char *data);
2275*4882a593Smuzhiyun #endif /* WL_NATOE */
2276*4882a593Smuzhiyun
2277*4882a593Smuzhiyun /* Send packet to dongle via data channel */
2278*4882a593Smuzhiyun extern int dhd_sendpkt(dhd_pub_t *dhdp, int ifidx, void *pkt);
2279*4882a593Smuzhiyun
2280*4882a593Smuzhiyun /* send up locally generated event */
2281*4882a593Smuzhiyun extern void dhd_sendup_event_common(dhd_pub_t *dhdp, wl_event_msg_t *event, void *data);
2282*4882a593Smuzhiyun /* Send event to host */
2283*4882a593Smuzhiyun extern void dhd_sendup_event(dhd_pub_t *dhdp, wl_event_msg_t *event, void *data);
2284*4882a593Smuzhiyun #ifdef LOG_INTO_TCPDUMP
2285*4882a593Smuzhiyun extern void dhd_sendup_log(dhd_pub_t *dhdp, void *data, int len);
2286*4882a593Smuzhiyun #endif /* LOG_INTO_TCPDUMP */
2287*4882a593Smuzhiyun #ifdef SHOW_LOGTRACE
2288*4882a593Smuzhiyun void dhd_sendup_info_buf(dhd_pub_t *dhdp, uint8 *msg);
2289*4882a593Smuzhiyun #endif // endif
2290*4882a593Smuzhiyun extern int dhd_bus_devreset(dhd_pub_t *dhdp, uint8 flag);
2291*4882a593Smuzhiyun extern uint dhd_bus_status(dhd_pub_t *dhdp);
2292*4882a593Smuzhiyun extern int dhd_bus_start(dhd_pub_t *dhdp);
2293*4882a593Smuzhiyun extern int dhd_bus_suspend(dhd_pub_t *dhdpub);
2294*4882a593Smuzhiyun extern int dhd_bus_resume(dhd_pub_t *dhdpub, int stage);
2295*4882a593Smuzhiyun extern int dhd_bus_membytes(dhd_pub_t *dhdp, bool set, uint32 address, uint8 *data, uint size);
2296*4882a593Smuzhiyun extern void dhd_print_buf(void *pbuf, int len, int bytes_per_line);
2297*4882a593Smuzhiyun extern bool dhd_is_associated(dhd_pub_t *dhd, uint8 ifidx, int *retval);
2298*4882a593Smuzhiyun #if defined(BCMSDIO) || defined(BCMPCIE)
2299*4882a593Smuzhiyun extern uint dhd_bus_chip_id(dhd_pub_t *dhdp);
2300*4882a593Smuzhiyun extern uint dhd_bus_chiprev_id(dhd_pub_t *dhdp);
2301*4882a593Smuzhiyun extern uint dhd_bus_chippkg_id(dhd_pub_t *dhdp);
2302*4882a593Smuzhiyun #ifdef DHD_MAP_CHIP_FIRMWARE_PATH
2303*4882a593Smuzhiyun extern uint dhd_bus_chipmodule_id(dhd_pub_t *dhdp);
2304*4882a593Smuzhiyun #endif /* DHD_MAP_CHIP_FIRMWARE_PATH */
2305*4882a593Smuzhiyun #endif /* defined(BCMSDIO) || defined(BCMPCIE) */
2306*4882a593Smuzhiyun int dhd_bus_get_fw_mode(dhd_pub_t *dhdp);
2307*4882a593Smuzhiyun
2308*4882a593Smuzhiyun #if defined(KEEP_ALIVE)
2309*4882a593Smuzhiyun extern int dhd_keep_alive_onoff(dhd_pub_t *dhd);
2310*4882a593Smuzhiyun #endif /* KEEP_ALIVE */
2311*4882a593Smuzhiyun
2312*4882a593Smuzhiyun /* OS spin lock API */
2313*4882a593Smuzhiyun extern void *dhd_os_spin_lock_init(osl_t *osh);
2314*4882a593Smuzhiyun extern void dhd_os_spin_lock_deinit(osl_t *osh, void *lock);
2315*4882a593Smuzhiyun extern unsigned long dhd_os_spin_lock(void *lock);
2316*4882a593Smuzhiyun void dhd_os_spin_unlock(void *lock, unsigned long flags);
2317*4882a593Smuzhiyun
2318*4882a593Smuzhiyun /* linux is defined for DHD EFI builds also,
2319*4882a593Smuzhiyun * since its cross-compiled for EFI from linux.
2320*4882a593Smuzhiyun * dbgring_lock apis are meant only for linux
2321*4882a593Smuzhiyun * to use mutexes, other OSes will continue to
2322*4882a593Smuzhiyun * use dhd_os_spin_lock
2323*4882a593Smuzhiyun */
2324*4882a593Smuzhiyun void *dhd_os_dbgring_lock_init(osl_t *osh);
2325*4882a593Smuzhiyun void dhd_os_dbgring_lock_deinit(osl_t *osh, void *mtx);
2326*4882a593Smuzhiyun unsigned long dhd_os_dbgring_lock(void *lock);
2327*4882a593Smuzhiyun void dhd_os_dbgring_unlock(void *lock, unsigned long flags);
2328*4882a593Smuzhiyun
dhd_os_tput_test_wait(dhd_pub_t * pub,uint * condition,uint timeout_ms)2329*4882a593Smuzhiyun static INLINE int dhd_os_tput_test_wait(dhd_pub_t *pub, uint *condition,
2330*4882a593Smuzhiyun uint timeout_ms)
2331*4882a593Smuzhiyun { return 0; }
dhd_os_tput_test_wake(dhd_pub_t * pub)2332*4882a593Smuzhiyun static INLINE int dhd_os_tput_test_wake(dhd_pub_t * pub)
2333*4882a593Smuzhiyun { return 0; }
2334*4882a593Smuzhiyun
2335*4882a593Smuzhiyun extern int dhd_os_busbusy_wait_negation(dhd_pub_t * pub, uint * condition);
2336*4882a593Smuzhiyun extern int dhd_os_busbusy_wake(dhd_pub_t * pub);
2337*4882a593Smuzhiyun extern void dhd_os_tx_completion_wake(dhd_pub_t *dhd);
2338*4882a593Smuzhiyun extern int dhd_os_busbusy_wait_condition(dhd_pub_t *pub, uint *var, uint condition);
2339*4882a593Smuzhiyun int dhd_os_busbusy_wait_bitmask(dhd_pub_t *pub, uint *var,
2340*4882a593Smuzhiyun uint bitmask, uint condition);
2341*4882a593Smuzhiyun extern int dhd_os_d3ack_wait(dhd_pub_t * pub, uint * condition);
2342*4882a593Smuzhiyun extern int dhd_os_d3ack_wake(dhd_pub_t * pub);
2343*4882a593Smuzhiyun extern int dhd_os_dmaxfer_wait(dhd_pub_t *pub, uint *condition);
2344*4882a593Smuzhiyun extern int dhd_os_dmaxfer_wake(dhd_pub_t *pub);
2345*4882a593Smuzhiyun
2346*4882a593Smuzhiyun /*
2347*4882a593Smuzhiyun * Manage sta objects in an interface. Interface is identified by an ifindex and
2348*4882a593Smuzhiyun * sta(s) within an interfaces are managed using a MacAddress of the sta.
2349*4882a593Smuzhiyun */
2350*4882a593Smuzhiyun struct dhd_sta;
2351*4882a593Smuzhiyun extern bool dhd_sta_associated(dhd_pub_t *dhdp, uint32 bssidx, uint8 *mac);
2352*4882a593Smuzhiyun extern struct dhd_sta *dhd_find_sta(void *pub, int ifidx, void *ea);
2353*4882a593Smuzhiyun extern struct dhd_sta *dhd_findadd_sta(void *pub, int ifidx, void *ea);
2354*4882a593Smuzhiyun extern void dhd_del_all_sta(void *pub, int ifidx);
2355*4882a593Smuzhiyun extern void dhd_del_sta(void *pub, int ifidx, void *ea);
2356*4882a593Smuzhiyun extern int dhd_get_ap_isolate(dhd_pub_t *dhdp, uint32 idx);
2357*4882a593Smuzhiyun extern int dhd_set_ap_isolate(dhd_pub_t *dhdp, uint32 idx, int val);
2358*4882a593Smuzhiyun extern int dhd_bssidx2idx(dhd_pub_t *dhdp, uint32 bssidx);
2359*4882a593Smuzhiyun extern struct net_device *dhd_linux_get_primary_netdev(dhd_pub_t *dhdp);
2360*4882a593Smuzhiyun
2361*4882a593Smuzhiyun extern bool dhd_is_concurrent_mode(dhd_pub_t *dhd);
2362*4882a593Smuzhiyun int dhd_iovar(dhd_pub_t *pub, int ifidx, char *name, char *param_buf, uint param_len,
2363*4882a593Smuzhiyun char *res_buf, uint res_len, int set);
2364*4882a593Smuzhiyun extern int dhd_getiovar(dhd_pub_t *pub, int ifidx, char *name, char *cmd_buf,
2365*4882a593Smuzhiyun uint cmd_len, char **resptr, uint resp_len);
2366*4882a593Smuzhiyun
2367*4882a593Smuzhiyun #ifdef DHD_MCAST_REGEN
2368*4882a593Smuzhiyun extern int dhd_get_mcast_regen_bss_enable(dhd_pub_t *dhdp, uint32 idx);
2369*4882a593Smuzhiyun extern int dhd_set_mcast_regen_bss_enable(dhd_pub_t *dhdp, uint32 idx, int val);
2370*4882a593Smuzhiyun #endif // endif
2371*4882a593Smuzhiyun typedef enum cust_gpio_modes {
2372*4882a593Smuzhiyun WLAN_RESET_ON,
2373*4882a593Smuzhiyun WLAN_RESET_OFF,
2374*4882a593Smuzhiyun WLAN_POWER_ON,
2375*4882a593Smuzhiyun WLAN_POWER_OFF
2376*4882a593Smuzhiyun } cust_gpio_modes_t;
2377*4882a593Smuzhiyun
2378*4882a593Smuzhiyun typedef struct dmaxref_mem_map {
2379*4882a593Smuzhiyun dhd_dma_buf_t *srcmem;
2380*4882a593Smuzhiyun dhd_dma_buf_t *dstmem;
2381*4882a593Smuzhiyun } dmaxref_mem_map_t;
2382*4882a593Smuzhiyun
2383*4882a593Smuzhiyun #if defined(OEM_ANDROID)
2384*4882a593Smuzhiyun extern int wl_iw_iscan_set_scan_broadcast_prep(struct net_device *dev, uint flag);
2385*4882a593Smuzhiyun extern int wl_iw_send_priv_event(struct net_device *dev, char *flag);
2386*4882a593Smuzhiyun #endif /* defined(OEM_ANDROID) */
2387*4882a593Smuzhiyun
2388*4882a593Smuzhiyun #ifdef DHD_PCIE_NATIVE_RUNTIMEPM
2389*4882a593Smuzhiyun extern void dhd_flush_rx_tx_wq(dhd_pub_t *dhdp);
2390*4882a593Smuzhiyun #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
2391*4882a593Smuzhiyun
2392*4882a593Smuzhiyun /*
2393*4882a593Smuzhiyun * Insmod parameters for debug/test
2394*4882a593Smuzhiyun */
2395*4882a593Smuzhiyun
2396*4882a593Smuzhiyun /* Watchdog timer interval */
2397*4882a593Smuzhiyun extern uint dhd_watchdog_ms;
2398*4882a593Smuzhiyun #ifdef DHD_PCIE_RUNTIMEPM
2399*4882a593Smuzhiyun extern uint dhd_runtimepm_ms;
2400*4882a593Smuzhiyun #endif /* DHD_PCIE_RUNTIMEPM */
2401*4882a593Smuzhiyun
2402*4882a593Smuzhiyun /** Default console output poll interval */
2403*4882a593Smuzhiyun extern uint dhd_console_ms;
2404*4882a593Smuzhiyun
2405*4882a593Smuzhiyun #if defined(DHD_DEBUG)
2406*4882a593Smuzhiyun extern uint wl_msg_level;
2407*4882a593Smuzhiyun #endif /* defined(DHD_DEBUG) */
2408*4882a593Smuzhiyun
2409*4882a593Smuzhiyun extern uint dhd_slpauto;
2410*4882a593Smuzhiyun
2411*4882a593Smuzhiyun /* Use interrupts */
2412*4882a593Smuzhiyun extern uint dhd_intr;
2413*4882a593Smuzhiyun
2414*4882a593Smuzhiyun /* Use polling */
2415*4882a593Smuzhiyun extern uint dhd_poll;
2416*4882a593Smuzhiyun
2417*4882a593Smuzhiyun /* ARP offload agent mode */
2418*4882a593Smuzhiyun extern uint dhd_arp_mode;
2419*4882a593Smuzhiyun
2420*4882a593Smuzhiyun /* ARP offload enable */
2421*4882a593Smuzhiyun extern uint dhd_arp_enable;
2422*4882a593Smuzhiyun
2423*4882a593Smuzhiyun /* Pkt filte enable control */
2424*4882a593Smuzhiyun extern uint dhd_pkt_filter_enable;
2425*4882a593Smuzhiyun
2426*4882a593Smuzhiyun /* Pkt filter init setup */
2427*4882a593Smuzhiyun extern uint dhd_pkt_filter_init;
2428*4882a593Smuzhiyun
2429*4882a593Smuzhiyun /* Pkt filter mode control */
2430*4882a593Smuzhiyun extern uint dhd_master_mode;
2431*4882a593Smuzhiyun
2432*4882a593Smuzhiyun /* Roaming mode control */
2433*4882a593Smuzhiyun extern uint dhd_roam_disable;
2434*4882a593Smuzhiyun
2435*4882a593Smuzhiyun /* Roaming mode control */
2436*4882a593Smuzhiyun extern uint dhd_radio_up;
2437*4882a593Smuzhiyun
2438*4882a593Smuzhiyun /* TCM verification control */
2439*4882a593Smuzhiyun extern uint dhd_tcm_test_enable;
2440*4882a593Smuzhiyun
2441*4882a593Smuzhiyun /* Disable BUG_ON(1) */
2442*4882a593Smuzhiyun #ifdef DHD_FW_COREDUMP
2443*4882a593Smuzhiyun extern uint disable_bug_on;
2444*4882a593Smuzhiyun #endif /* DHD_FW_COREDUMP */
2445*4882a593Smuzhiyun
2446*4882a593Smuzhiyun /* Initial idletime ticks (may be -1 for immediate idle, 0 for no idle) */
2447*4882a593Smuzhiyun extern int dhd_idletime;
2448*4882a593Smuzhiyun #ifdef DHD_USE_IDLECOUNT
2449*4882a593Smuzhiyun #define DHD_IDLETIME_TICKS 5
2450*4882a593Smuzhiyun #else
2451*4882a593Smuzhiyun #define DHD_IDLETIME_TICKS 1
2452*4882a593Smuzhiyun #endif /* DHD_USE_IDLECOUNT */
2453*4882a593Smuzhiyun
2454*4882a593Smuzhiyun /* SDIO Drive Strength */
2455*4882a593Smuzhiyun extern uint dhd_sdiod_drive_strength;
2456*4882a593Smuzhiyun
2457*4882a593Smuzhiyun /* triggers bcm_bprintf to print to kernel log */
2458*4882a593Smuzhiyun extern bool bcm_bprintf_bypass;
2459*4882a593Smuzhiyun
2460*4882a593Smuzhiyun /* Override to force tx queueing all the time */
2461*4882a593Smuzhiyun extern uint dhd_force_tx_queueing;
2462*4882a593Smuzhiyun
2463*4882a593Smuzhiyun /* Default bcn_timeout value is 4 */
2464*4882a593Smuzhiyun #define DEFAULT_BCN_TIMEOUT_VALUE 4
2465*4882a593Smuzhiyun #ifndef CUSTOM_BCN_TIMEOUT_SETTING
2466*4882a593Smuzhiyun #define CUSTOM_BCN_TIMEOUT_SETTING DEFAULT_BCN_TIMEOUT_VALUE
2467*4882a593Smuzhiyun #endif // endif
2468*4882a593Smuzhiyun
2469*4882a593Smuzhiyun /* Default KEEP_ALIVE Period is 55 sec to prevent AP from sending Keep Alive probe frame */
2470*4882a593Smuzhiyun #define DEFAULT_KEEP_ALIVE_VALUE 55000 /* msec */
2471*4882a593Smuzhiyun #ifndef CUSTOM_KEEP_ALIVE_SETTING
2472*4882a593Smuzhiyun #define CUSTOM_KEEP_ALIVE_SETTING DEFAULT_KEEP_ALIVE_VALUE
2473*4882a593Smuzhiyun #endif /* DEFAULT_KEEP_ALIVE_VALUE */
2474*4882a593Smuzhiyun
2475*4882a593Smuzhiyun #define NULL_PKT_STR "null_pkt"
2476*4882a593Smuzhiyun
2477*4882a593Smuzhiyun /* hooks for custom glom setting option via Makefile */
2478*4882a593Smuzhiyun #define DEFAULT_GLOM_VALUE -1
2479*4882a593Smuzhiyun #ifndef CUSTOM_GLOM_SETTING
2480*4882a593Smuzhiyun #define CUSTOM_GLOM_SETTING DEFAULT_GLOM_VALUE
2481*4882a593Smuzhiyun #endif // endif
2482*4882a593Smuzhiyun #define WL_AUTO_ROAM_TRIGGER -75
2483*4882a593Smuzhiyun /* hooks for custom Roaming Trigger setting via Makefile */
2484*4882a593Smuzhiyun #define DEFAULT_ROAM_TRIGGER_VALUE -75 /* dBm default roam trigger all band */
2485*4882a593Smuzhiyun #define DEFAULT_ROAM_TRIGGER_SETTING -1
2486*4882a593Smuzhiyun #ifndef CUSTOM_ROAM_TRIGGER_SETTING
2487*4882a593Smuzhiyun #define CUSTOM_ROAM_TRIGGER_SETTING DEFAULT_ROAM_TRIGGER_VALUE
2488*4882a593Smuzhiyun #endif // endif
2489*4882a593Smuzhiyun
2490*4882a593Smuzhiyun /* hooks for custom Roaming Romaing setting via Makefile */
2491*4882a593Smuzhiyun #define DEFAULT_ROAM_DELTA_VALUE 10 /* dBm default roam delta all band */
2492*4882a593Smuzhiyun #define DEFAULT_ROAM_DELTA_SETTING -1
2493*4882a593Smuzhiyun #ifndef CUSTOM_ROAM_DELTA_SETTING
2494*4882a593Smuzhiyun #define CUSTOM_ROAM_DELTA_SETTING DEFAULT_ROAM_DELTA_VALUE
2495*4882a593Smuzhiyun #endif // endif
2496*4882a593Smuzhiyun
2497*4882a593Smuzhiyun /* hooks for custom PNO Event wake lock to guarantee enough time
2498*4882a593Smuzhiyun for the Platform to detect Event before system suspended
2499*4882a593Smuzhiyun */
2500*4882a593Smuzhiyun #define DEFAULT_PNO_EVENT_LOCK_xTIME 2 /* multiplay of DHD_PACKET_TIMEOUT_MS */
2501*4882a593Smuzhiyun #ifndef CUSTOM_PNO_EVENT_LOCK_xTIME
2502*4882a593Smuzhiyun #define CUSTOM_PNO_EVENT_LOCK_xTIME DEFAULT_PNO_EVENT_LOCK_xTIME
2503*4882a593Smuzhiyun #endif // endif
2504*4882a593Smuzhiyun /* hooks for custom dhd_dpc_prio setting option via Makefile */
2505*4882a593Smuzhiyun #define DEFAULT_DHP_DPC_PRIO 1
2506*4882a593Smuzhiyun #ifndef CUSTOM_DPC_PRIO_SETTING
2507*4882a593Smuzhiyun #define CUSTOM_DPC_PRIO_SETTING DEFAULT_DHP_DPC_PRIO
2508*4882a593Smuzhiyun #endif // endif
2509*4882a593Smuzhiyun
2510*4882a593Smuzhiyun #ifndef CUSTOM_LISTEN_INTERVAL
2511*4882a593Smuzhiyun #define CUSTOM_LISTEN_INTERVAL LISTEN_INTERVAL
2512*4882a593Smuzhiyun #endif /* CUSTOM_LISTEN_INTERVAL */
2513*4882a593Smuzhiyun
2514*4882a593Smuzhiyun #define DEFAULT_SUSPEND_BCN_LI_DTIM 3
2515*4882a593Smuzhiyun #ifndef CUSTOM_SUSPEND_BCN_LI_DTIM
2516*4882a593Smuzhiyun #define CUSTOM_SUSPEND_BCN_LI_DTIM DEFAULT_SUSPEND_BCN_LI_DTIM
2517*4882a593Smuzhiyun #endif // endif
2518*4882a593Smuzhiyun
2519*4882a593Smuzhiyun #ifdef OEM_ANDROID
2520*4882a593Smuzhiyun #ifndef BCN_TIMEOUT_IN_SUSPEND
2521*4882a593Smuzhiyun #define BCN_TIMEOUT_IN_SUSPEND 6 /* bcn timeout value in suspend mode */
2522*4882a593Smuzhiyun #endif // endif
2523*4882a593Smuzhiyun #endif /* OEM_ANDROID */
2524*4882a593Smuzhiyun
2525*4882a593Smuzhiyun #ifndef CUSTOM_RXF_PRIO_SETTING
2526*4882a593Smuzhiyun #define CUSTOM_RXF_PRIO_SETTING MAX((CUSTOM_DPC_PRIO_SETTING - 1), 1)
2527*4882a593Smuzhiyun #endif // endif
2528*4882a593Smuzhiyun
2529*4882a593Smuzhiyun #define DEFAULT_WIFI_TURNOFF_DELAY 0
2530*4882a593Smuzhiyun #ifndef WIFI_TURNOFF_DELAY
2531*4882a593Smuzhiyun #define WIFI_TURNOFF_DELAY DEFAULT_WIFI_TURNOFF_DELAY
2532*4882a593Smuzhiyun #endif /* WIFI_TURNOFF_DELAY */
2533*4882a593Smuzhiyun
2534*4882a593Smuzhiyun #define DEFAULT_WIFI_TURNON_DELAY 200
2535*4882a593Smuzhiyun #ifndef WIFI_TURNON_DELAY
2536*4882a593Smuzhiyun #define WIFI_TURNON_DELAY DEFAULT_WIFI_TURNON_DELAY
2537*4882a593Smuzhiyun #endif /* WIFI_TURNON_DELAY */
2538*4882a593Smuzhiyun
2539*4882a593Smuzhiyun #define DEFAULT_DHD_WATCHDOG_INTERVAL_MS 10 /* msec */
2540*4882a593Smuzhiyun #ifndef CUSTOM_DHD_WATCHDOG_MS
2541*4882a593Smuzhiyun #define CUSTOM_DHD_WATCHDOG_MS DEFAULT_DHD_WATCHDOG_INTERVAL_MS
2542*4882a593Smuzhiyun #endif /* DEFAULT_DHD_WATCHDOG_INTERVAL_MS */
2543*4882a593Smuzhiyun
2544*4882a593Smuzhiyun #define DEFAULT_ASSOC_RETRY_MAX 3
2545*4882a593Smuzhiyun #ifndef CUSTOM_ASSOC_RETRY_MAX
2546*4882a593Smuzhiyun #define CUSTOM_ASSOC_RETRY_MAX DEFAULT_ASSOC_RETRY_MAX
2547*4882a593Smuzhiyun #endif /* DEFAULT_ASSOC_RETRY_MAX */
2548*4882a593Smuzhiyun
2549*4882a593Smuzhiyun #if defined(BCMSDIO) || defined(DISABLE_FRAMEBURST)
2550*4882a593Smuzhiyun #define DEFAULT_FRAMEBURST_SET 0
2551*4882a593Smuzhiyun #else
2552*4882a593Smuzhiyun #define DEFAULT_FRAMEBURST_SET 1
2553*4882a593Smuzhiyun #endif /* BCMSDIO */
2554*4882a593Smuzhiyun
2555*4882a593Smuzhiyun #ifndef CUSTOM_FRAMEBURST_SET
2556*4882a593Smuzhiyun #define CUSTOM_FRAMEBURST_SET DEFAULT_FRAMEBURST_SET
2557*4882a593Smuzhiyun #endif /* CUSTOM_FRAMEBURST_SET */
2558*4882a593Smuzhiyun
2559*4882a593Smuzhiyun #ifdef WLTDLS
2560*4882a593Smuzhiyun #ifndef CUSTOM_TDLS_IDLE_MODE_SETTING
2561*4882a593Smuzhiyun #define CUSTOM_TDLS_IDLE_MODE_SETTING 60000 /* 60sec to tear down TDLS of not active */
2562*4882a593Smuzhiyun #endif // endif
2563*4882a593Smuzhiyun #ifndef CUSTOM_TDLS_RSSI_THRESHOLD_HIGH
2564*4882a593Smuzhiyun #define CUSTOM_TDLS_RSSI_THRESHOLD_HIGH -70 /* rssi threshold for establishing TDLS link */
2565*4882a593Smuzhiyun #endif // endif
2566*4882a593Smuzhiyun #ifndef CUSTOM_TDLS_RSSI_THRESHOLD_LOW
2567*4882a593Smuzhiyun #define CUSTOM_TDLS_RSSI_THRESHOLD_LOW -80 /* rssi threshold for tearing down TDLS link */
2568*4882a593Smuzhiyun #endif // endif
2569*4882a593Smuzhiyun #ifndef CUSTOM_TDLS_PCKTCNT_THRESHOLD_HIGH
2570*4882a593Smuzhiyun #define CUSTOM_TDLS_PCKTCNT_THRESHOLD_HIGH 100 /* pkt/sec threshold for establishing TDLS link */
2571*4882a593Smuzhiyun #endif // endif
2572*4882a593Smuzhiyun #ifndef CUSTOM_TDLS_PCKTCNT_THRESHOLD_LOW
2573*4882a593Smuzhiyun #define CUSTOM_TDLS_PCKTCNT_THRESHOLD_LOW 10 /* pkt/sec threshold for tearing down TDLS link */
2574*4882a593Smuzhiyun #endif // endif
2575*4882a593Smuzhiyun #endif /* WLTDLS */
2576*4882a593Smuzhiyun
2577*4882a593Smuzhiyun #if defined(VSDB) || defined(ROAM_ENABLE)
2578*4882a593Smuzhiyun #define DEFAULT_BCN_TIMEOUT 8
2579*4882a593Smuzhiyun #else
2580*4882a593Smuzhiyun #define DEFAULT_BCN_TIMEOUT 4
2581*4882a593Smuzhiyun #endif // endif
2582*4882a593Smuzhiyun
2583*4882a593Smuzhiyun #ifndef CUSTOM_BCN_TIMEOUT
2584*4882a593Smuzhiyun #define CUSTOM_BCN_TIMEOUT DEFAULT_BCN_TIMEOUT
2585*4882a593Smuzhiyun #endif // endif
2586*4882a593Smuzhiyun
2587*4882a593Smuzhiyun #define MAX_DTIM_SKIP_BEACON_INTERVAL 100 /* max allowed associated AP beacon for DTIM skip */
2588*4882a593Smuzhiyun #ifndef MAX_DTIM_ALLOWED_INTERVAL
2589*4882a593Smuzhiyun #define MAX_DTIM_ALLOWED_INTERVAL 600 /* max allowed total beacon interval for DTIM skip */
2590*4882a593Smuzhiyun #endif // endif
2591*4882a593Smuzhiyun
2592*4882a593Smuzhiyun #ifdef OEM_ANDROID
2593*4882a593Smuzhiyun #ifndef MIN_DTIM_FOR_ROAM_THRES_EXTEND
2594*4882a593Smuzhiyun #define MIN_DTIM_FOR_ROAM_THRES_EXTEND 600 /* minimum dtim interval to extend roam threshold */
2595*4882a593Smuzhiyun #endif // endif
2596*4882a593Smuzhiyun #endif /* OEM_ANDROID */
2597*4882a593Smuzhiyun
2598*4882a593Smuzhiyun #define NO_DTIM_SKIP 1
2599*4882a593Smuzhiyun #ifdef SDTEST
2600*4882a593Smuzhiyun /* Echo packet generator (SDIO), pkts/s */
2601*4882a593Smuzhiyun extern uint dhd_pktgen;
2602*4882a593Smuzhiyun
2603*4882a593Smuzhiyun /* Echo packet len (0 => sawtooth, max 1800) */
2604*4882a593Smuzhiyun extern uint dhd_pktgen_len;
2605*4882a593Smuzhiyun #define MAX_PKTGEN_LEN 1800
2606*4882a593Smuzhiyun #endif // endif
2607*4882a593Smuzhiyun
2608*4882a593Smuzhiyun /* optionally set by a module_param_string() */
2609*4882a593Smuzhiyun #define MOD_PARAM_PATHLEN 2048
2610*4882a593Smuzhiyun #define MOD_PARAM_INFOLEN 512
2611*4882a593Smuzhiyun #define MOD_PARAM_SRLEN 64
2612*4882a593Smuzhiyun
2613*4882a593Smuzhiyun #ifdef SOFTAP
2614*4882a593Smuzhiyun extern char fw_path2[MOD_PARAM_PATHLEN];
2615*4882a593Smuzhiyun #endif // endif
2616*4882a593Smuzhiyun
2617*4882a593Smuzhiyun #if defined(ANDROID_PLATFORM_VERSION)
2618*4882a593Smuzhiyun #if (ANDROID_PLATFORM_VERSION < 7)
2619*4882a593Smuzhiyun #define DHD_LEGACY_FILE_PATH
2620*4882a593Smuzhiyun #define VENDOR_PATH "/system"
2621*4882a593Smuzhiyun #elif (ANDROID_PLATFORM_VERSION == 7)
2622*4882a593Smuzhiyun #define VENDOR_PATH "/system"
2623*4882a593Smuzhiyun #elif (ANDROID_PLATFORM_VERSION >= 8)
2624*4882a593Smuzhiyun #define VENDOR_PATH "/vendor"
2625*4882a593Smuzhiyun #endif /* ANDROID_PLATFORM_VERSION < 7 */
2626*4882a593Smuzhiyun #else
2627*4882a593Smuzhiyun #define VENDOR_PATH ""
2628*4882a593Smuzhiyun #endif /* ANDROID_PLATFORM_VERSION */
2629*4882a593Smuzhiyun
2630*4882a593Smuzhiyun #if defined(ANDROID_PLATFORM_VERSION)
2631*4882a593Smuzhiyun #if (ANDROID_PLATFORM_VERSION < 9)
2632*4882a593Smuzhiyun #ifdef WL_STATIC_IF
2633*4882a593Smuzhiyun #undef WL_STATIC_IF
2634*4882a593Smuzhiyun #endif /* WL_STATIC_IF */
2635*4882a593Smuzhiyun #ifdef WL_STATIC_IFNAME_PREFIX
2636*4882a593Smuzhiyun #undef WL_STATIC_IFNAME_PREFIX
2637*4882a593Smuzhiyun #endif /* WL_STATIC_IFNAME_PREFIX */
2638*4882a593Smuzhiyun #endif /* ANDROID_PLATFORM_VERSION < 9 */
2639*4882a593Smuzhiyun #endif /* ANDROID_PLATFORM_VERSION */
2640*4882a593Smuzhiyun
2641*4882a593Smuzhiyun #if defined(DHD_LEGACY_FILE_PATH)
2642*4882a593Smuzhiyun #define PLATFORM_PATH "/data/"
2643*4882a593Smuzhiyun #elif defined(PLATFORM_SLP)
2644*4882a593Smuzhiyun #define PLATFORM_PATH "/opt/etc/"
2645*4882a593Smuzhiyun #else
2646*4882a593Smuzhiyun #if defined(ANDROID_PLATFORM_VERSION)
2647*4882a593Smuzhiyun #if (ANDROID_PLATFORM_VERSION >= 9)
2648*4882a593Smuzhiyun #define PLATFORM_PATH "/data/vendor/conn/"
2649*4882a593Smuzhiyun #define DHD_MAC_ADDR_EXPORT
2650*4882a593Smuzhiyun #define DHD_ADPS_BAM_EXPORT
2651*4882a593Smuzhiyun #define DHD_EXPORT_CNTL_FILE
2652*4882a593Smuzhiyun #define DHD_SOFTAP_DUAL_IF_INFO
2653*4882a593Smuzhiyun #define DHD_SEND_HANG_PRIVCMD_ERRORS
2654*4882a593Smuzhiyun #else
2655*4882a593Smuzhiyun #define PLATFORM_PATH "/data/misc/conn/"
2656*4882a593Smuzhiyun #endif /* ANDROID_PLATFORM_VERSION >= 9 */
2657*4882a593Smuzhiyun #else
2658*4882a593Smuzhiyun #define PLATFORM_PATH "/data/misc/conn/"
2659*4882a593Smuzhiyun #endif /* ANDROID_PLATFORM_VERSION */
2660*4882a593Smuzhiyun #endif /* DHD_LEGACY_FILE_PATH */
2661*4882a593Smuzhiyun
2662*4882a593Smuzhiyun #ifdef DHD_MAC_ADDR_EXPORT
2663*4882a593Smuzhiyun extern struct ether_addr sysfs_mac_addr;
2664*4882a593Smuzhiyun #endif /* DHD_MAC_ADDR_EXPORT */
2665*4882a593Smuzhiyun
2666*4882a593Smuzhiyun /* Flag to indicate if we should download firmware on driver load */
2667*4882a593Smuzhiyun extern uint dhd_download_fw_on_driverload;
2668*4882a593Smuzhiyun extern int allow_delay_fwdl;
2669*4882a593Smuzhiyun
2670*4882a593Smuzhiyun extern int dhd_process_cid_mac(dhd_pub_t *dhdp, bool prepost);
2671*4882a593Smuzhiyun extern int dhd_write_file(const char *filepath, char *buf, int buf_len);
2672*4882a593Smuzhiyun extern int dhd_read_file(const char *filepath, char *buf, int buf_len);
2673*4882a593Smuzhiyun extern int dhd_write_file_and_check(const char *filepath, char *buf, int buf_len);
2674*4882a593Smuzhiyun extern int dhd_file_delete(char *path);
2675*4882a593Smuzhiyun
2676*4882a593Smuzhiyun #ifdef READ_MACADDR
2677*4882a593Smuzhiyun extern int dhd_set_macaddr_from_file(dhd_pub_t *dhdp);
2678*4882a593Smuzhiyun #else
dhd_set_macaddr_from_file(dhd_pub_t * dhdp)2679*4882a593Smuzhiyun static INLINE int dhd_set_macaddr_from_file(dhd_pub_t *dhdp) { return 0; }
2680*4882a593Smuzhiyun #endif /* READ_MACADDR */
2681*4882a593Smuzhiyun #ifdef WRITE_MACADDR
2682*4882a593Smuzhiyun extern int dhd_write_macaddr(struct ether_addr *mac);
2683*4882a593Smuzhiyun #else
dhd_write_macaddr(struct ether_addr * mac)2684*4882a593Smuzhiyun static INLINE int dhd_write_macaddr(struct ether_addr *mac) { return 0; }
2685*4882a593Smuzhiyun #endif /* WRITE_MACADDR */
2686*4882a593Smuzhiyun #ifdef USE_CID_CHECK
2687*4882a593Smuzhiyun #define MAX_VNAME_LEN 64
2688*4882a593Smuzhiyun #ifdef DHD_EXPORT_CNTL_FILE
2689*4882a593Smuzhiyun extern char cidinfostr[MAX_VNAME_LEN];
2690*4882a593Smuzhiyun #endif /* DHD_EXPORT_CNTL_FILE */
2691*4882a593Smuzhiyun extern int dhd_check_module_cid(dhd_pub_t *dhdp);
2692*4882a593Smuzhiyun extern char *dhd_get_cid_info(unsigned char *vid, int vid_length);
2693*4882a593Smuzhiyun #else
dhd_check_module_cid(dhd_pub_t * dhdp)2694*4882a593Smuzhiyun static INLINE int dhd_check_module_cid(dhd_pub_t *dhdp) { return 0; }
2695*4882a593Smuzhiyun #endif /* USE_CID_CHECK */
2696*4882a593Smuzhiyun #ifdef GET_MAC_FROM_OTP
2697*4882a593Smuzhiyun extern int dhd_check_module_mac(dhd_pub_t *dhdp);
2698*4882a593Smuzhiyun #else
dhd_check_module_mac(dhd_pub_t * dhdp)2699*4882a593Smuzhiyun static INLINE int dhd_check_module_mac(dhd_pub_t *dhdp) { return 0; }
2700*4882a593Smuzhiyun #endif /* GET_MAC_FROM_OTP */
2701*4882a593Smuzhiyun
2702*4882a593Smuzhiyun #if defined(READ_MACADDR) || defined(WRITE_MACADDR) || defined(USE_CID_CHECK) || \
2703*4882a593Smuzhiyun defined(GET_MAC_FROM_OTP)
2704*4882a593Smuzhiyun #define DHD_USE_CISINFO
2705*4882a593Smuzhiyun #endif /* READ_MACADDR || WRITE_MACADDR || USE_CID_CHECK || GET_MAC_FROM_OTP */
2706*4882a593Smuzhiyun
2707*4882a593Smuzhiyun #ifdef DHD_USE_CISINFO
2708*4882a593Smuzhiyun int dhd_read_cis(dhd_pub_t *dhdp);
2709*4882a593Smuzhiyun void dhd_clear_cis(dhd_pub_t *dhdp);
2710*4882a593Smuzhiyun #if defined(SUPPORT_MULTIPLE_MODULE_CIS) && defined(USE_CID_CHECK)
2711*4882a593Smuzhiyun extern int dhd_check_module_b85a(void);
2712*4882a593Smuzhiyun extern int dhd_check_module_b90(void);
2713*4882a593Smuzhiyun #define BCM4359_MODULE_TYPE_B90B 1
2714*4882a593Smuzhiyun #define BCM4359_MODULE_TYPE_B90S 2
2715*4882a593Smuzhiyun #endif /* defined(SUPPORT_MULTIPLE_MODULE_CIS) && defined(USE_CID_CHECK) */
2716*4882a593Smuzhiyun #if defined(USE_CID_CHECK)
2717*4882a593Smuzhiyun extern int dhd_check_module_bcm(char *module_type, int index, bool *is_murata_fem);
2718*4882a593Smuzhiyun #endif /* defined(USE_CID_CHECK) */
2719*4882a593Smuzhiyun #else
dhd_read_cis(dhd_pub_t * dhdp)2720*4882a593Smuzhiyun static INLINE int dhd_read_cis(dhd_pub_t *dhdp) { return 0; }
dhd_clear_cis(dhd_pub_t * dhdp)2721*4882a593Smuzhiyun static INLINE void dhd_clear_cis(dhd_pub_t *dhdp) { }
2722*4882a593Smuzhiyun #endif /* DHD_USE_CISINFO */
2723*4882a593Smuzhiyun
2724*4882a593Smuzhiyun #if defined(WL_CFG80211) && defined(SUPPORT_DEEP_SLEEP)
2725*4882a593Smuzhiyun /* Flags to indicate if we distingish power off policy when
2726*4882a593Smuzhiyun * user set the memu "Keep Wi-Fi on during sleep" to "Never"
2727*4882a593Smuzhiyun */
2728*4882a593Smuzhiyun extern int trigger_deep_sleep;
2729*4882a593Smuzhiyun int dhd_deepsleep(struct net_device *dev, int flag);
2730*4882a593Smuzhiyun #endif /* WL_CFG80211 && SUPPORT_DEEP_SLEEP */
2731*4882a593Smuzhiyun
2732*4882a593Smuzhiyun extern void dhd_wait_for_event(dhd_pub_t *dhd, bool *lockvar);
2733*4882a593Smuzhiyun extern void dhd_wait_event_wakeup(dhd_pub_t*dhd);
2734*4882a593Smuzhiyun
2735*4882a593Smuzhiyun #define IFLOCK_INIT(lock) *lock = 0
2736*4882a593Smuzhiyun #define IFLOCK(lock) while (InterlockedCompareExchange((lock), 1, 0)) \
2737*4882a593Smuzhiyun NdisStallExecution(1);
2738*4882a593Smuzhiyun #define IFUNLOCK(lock) InterlockedExchange((lock), 0)
2739*4882a593Smuzhiyun #define IFLOCK_FREE(lock)
2740*4882a593Smuzhiyun #define FW_SUPPORTED(dhd, capa) ((strstr(dhd->fw_capabilities, " " #capa " ") != NULL))
2741*4882a593Smuzhiyun #ifdef ARP_OFFLOAD_SUPPORT
2742*4882a593Smuzhiyun #define MAX_IPV4_ENTRIES 8
2743*4882a593Smuzhiyun void dhd_arp_offload_set(dhd_pub_t * dhd, int arp_mode);
2744*4882a593Smuzhiyun void dhd_arp_offload_enable(dhd_pub_t * dhd, int arp_enable);
2745*4882a593Smuzhiyun
2746*4882a593Smuzhiyun /* dhd_commn arp offload wrapers */
2747*4882a593Smuzhiyun void dhd_aoe_hostip_clr(dhd_pub_t *dhd, int idx);
2748*4882a593Smuzhiyun void dhd_aoe_arp_clr(dhd_pub_t *dhd, int idx);
2749*4882a593Smuzhiyun int dhd_arp_get_arp_hostip_table(dhd_pub_t *dhd, void *buf, int buflen, int idx);
2750*4882a593Smuzhiyun void dhd_arp_offload_add_ip(dhd_pub_t *dhd, uint32 ipaddr, int idx);
2751*4882a593Smuzhiyun #endif /* ARP_OFFLOAD_SUPPORT */
2752*4882a593Smuzhiyun #ifdef WLTDLS
2753*4882a593Smuzhiyun int dhd_tdls_enable(struct net_device *dev, bool tdls_on, bool auto_on, struct ether_addr *mac);
2754*4882a593Smuzhiyun int dhd_tdls_set_mode(dhd_pub_t *dhd, bool wfd_mode);
2755*4882a593Smuzhiyun #ifdef PCIE_FULL_DONGLE
2756*4882a593Smuzhiyun int dhd_tdls_update_peer_info(dhd_pub_t *dhdp, wl_event_msg_t *event);
2757*4882a593Smuzhiyun int dhd_tdls_event_handler(dhd_pub_t *dhd_pub, wl_event_msg_t *event);
2758*4882a593Smuzhiyun int dhd_free_tdls_peer_list(dhd_pub_t *dhd_pub);
2759*4882a593Smuzhiyun #endif /* PCIE_FULL_DONGLE */
2760*4882a593Smuzhiyun #endif /* WLTDLS */
2761*4882a593Smuzhiyun
2762*4882a593Smuzhiyun /* Neighbor Discovery Offload Support */
2763*4882a593Smuzhiyun extern int dhd_ndo_enable(dhd_pub_t * dhd, int ndo_enable);
2764*4882a593Smuzhiyun int dhd_ndo_add_ip(dhd_pub_t *dhd, char* ipaddr, int idx);
2765*4882a593Smuzhiyun int dhd_ndo_remove_ip(dhd_pub_t *dhd, int idx);
2766*4882a593Smuzhiyun
2767*4882a593Smuzhiyun /* Enhanced ND offload support */
2768*4882a593Smuzhiyun uint16 dhd_ndo_get_version(dhd_pub_t *dhdp);
2769*4882a593Smuzhiyun int dhd_ndo_add_ip_with_type(dhd_pub_t *dhdp, char *ipv6addr, uint8 type, int idx);
2770*4882a593Smuzhiyun int dhd_ndo_remove_ip_by_addr(dhd_pub_t *dhdp, char *ipv6addr, int idx);
2771*4882a593Smuzhiyun int dhd_ndo_remove_ip_by_type(dhd_pub_t *dhdp, uint8 type, int idx);
2772*4882a593Smuzhiyun int dhd_ndo_unsolicited_na_filter_enable(dhd_pub_t *dhdp, int enable);
2773*4882a593Smuzhiyun
2774*4882a593Smuzhiyun /* ioctl processing for nl80211 */
2775*4882a593Smuzhiyun int dhd_ioctl_process(dhd_pub_t *pub, int ifidx, struct dhd_ioctl *ioc, void *data_buf);
2776*4882a593Smuzhiyun
2777*4882a593Smuzhiyun #if defined(SUPPORT_MULTIPLE_REVISION)
2778*4882a593Smuzhiyun extern int
2779*4882a593Smuzhiyun concate_revision(struct dhd_bus *bus, char *fwpath, char *nvpath);
2780*4882a593Smuzhiyun #endif /* SUPPORT_MULTIPLE_REVISION */
2781*4882a593Smuzhiyun void dhd_bus_update_fw_nv_path(struct dhd_bus *bus, char *pfw_path, char *pnv_path);
2782*4882a593Smuzhiyun void dhd_set_bus_state(void *bus, uint32 state);
2783*4882a593Smuzhiyun
2784*4882a593Smuzhiyun /* Remove proper pkts(either one no-frag pkt or whole fragmented pkts) */
2785*4882a593Smuzhiyun typedef int (*f_droppkt_t)(dhd_pub_t *dhdp, int prec, void* p, bool bPktInQ);
2786*4882a593Smuzhiyun extern bool dhd_prec_drop_pkts(dhd_pub_t *dhdp, struct pktq *pq, int prec, f_droppkt_t fn);
2787*4882a593Smuzhiyun
2788*4882a593Smuzhiyun #ifdef PROP_TXSTATUS
2789*4882a593Smuzhiyun int dhd_os_wlfc_block(dhd_pub_t *pub);
2790*4882a593Smuzhiyun int dhd_os_wlfc_unblock(dhd_pub_t *pub);
2791*4882a593Smuzhiyun extern const uint8 prio2fifo[];
2792*4882a593Smuzhiyun #endif /* PROP_TXSTATUS */
2793*4882a593Smuzhiyun
2794*4882a593Smuzhiyun int dhd_os_socram_dump(struct net_device *dev, uint32 *dump_size);
2795*4882a593Smuzhiyun int dhd_os_get_socram_dump(struct net_device *dev, char **buf, uint32 *size);
2796*4882a593Smuzhiyun int dhd_common_socram_dump(dhd_pub_t *dhdp);
2797*4882a593Smuzhiyun
2798*4882a593Smuzhiyun int dhd_dump(dhd_pub_t *dhdp, char *buf, int buflen);
2799*4882a593Smuzhiyun
2800*4882a593Smuzhiyun int dhd_os_get_version(struct net_device *dev, bool dhd_ver, char **buf, uint32 size);
2801*4882a593Smuzhiyun void dhd_get_memdump_filename(struct net_device *ndev, char *memdump_path, int len, char *fname);
2802*4882a593Smuzhiyun uint8* dhd_os_prealloc(dhd_pub_t *dhdpub, int section, uint size, bool kmalloc_if_fail);
2803*4882a593Smuzhiyun void dhd_os_prefree(dhd_pub_t *dhdpub, void *addr, uint size);
2804*4882a593Smuzhiyun
2805*4882a593Smuzhiyun #if defined(CONFIG_DHD_USE_STATIC_BUF)
2806*4882a593Smuzhiyun #define DHD_OS_PREALLOC(dhdpub, section, size) dhd_os_prealloc(dhdpub, section, size, FALSE)
2807*4882a593Smuzhiyun #define DHD_OS_PREFREE(dhdpub, addr, size) dhd_os_prefree(dhdpub, addr, size)
2808*4882a593Smuzhiyun #else
2809*4882a593Smuzhiyun #define DHD_OS_PREALLOC(dhdpub, section, size) MALLOC(dhdpub->osh, size)
2810*4882a593Smuzhiyun #define DHD_OS_PREFREE(dhdpub, addr, size) MFREE(dhdpub->osh, addr, size)
2811*4882a593Smuzhiyun #endif /* defined(CONFIG_DHD_USE_STATIC_BUF) */
2812*4882a593Smuzhiyun
2813*4882a593Smuzhiyun #ifdef USE_WFA_CERT_CONF
2814*4882a593Smuzhiyun enum {
2815*4882a593Smuzhiyun SET_PARAM_BUS_TXGLOM_MODE,
2816*4882a593Smuzhiyun SET_PARAM_ROAMOFF,
2817*4882a593Smuzhiyun #ifdef USE_WL_FRAMEBURST
2818*4882a593Smuzhiyun SET_PARAM_FRAMEBURST,
2819*4882a593Smuzhiyun #endif /* USE_WL_FRAMEBURST */
2820*4882a593Smuzhiyun #ifdef USE_WL_TXBF
2821*4882a593Smuzhiyun SET_PARAM_TXBF,
2822*4882a593Smuzhiyun #endif /* USE_WL_TXBF */
2823*4882a593Smuzhiyun #ifdef PROP_TXSTATUS
2824*4882a593Smuzhiyun SET_PARAM_PROPTX,
2825*4882a593Smuzhiyun SET_PARAM_PROPTXMODE,
2826*4882a593Smuzhiyun #endif /* PROP_TXSTATUS */
2827*4882a593Smuzhiyun PARAM_LAST_VALUE
2828*4882a593Smuzhiyun };
2829*4882a593Smuzhiyun extern int sec_get_param_wfa_cert(dhd_pub_t *dhd, int mode, uint* read_val);
2830*4882a593Smuzhiyun #ifdef DHD_EXPORT_CNTL_FILE
2831*4882a593Smuzhiyun #define VALUENOTSET 0xFFFFFFFFu
2832*4882a593Smuzhiyun extern uint32 bus_txglom;
2833*4882a593Smuzhiyun extern uint32 roam_off;
2834*4882a593Smuzhiyun #ifdef USE_WL_FRAMEBURST
2835*4882a593Smuzhiyun extern uint32 frameburst;
2836*4882a593Smuzhiyun #endif /* USE_WL_FRAMEBURST */
2837*4882a593Smuzhiyun #ifdef USE_WL_TXBF
2838*4882a593Smuzhiyun extern uint32 txbf;
2839*4882a593Smuzhiyun #endif /* USE_WL_TXBF */
2840*4882a593Smuzhiyun #ifdef PROP_TXSTATUS
2841*4882a593Smuzhiyun extern uint32 proptx;
2842*4882a593Smuzhiyun #endif /* PROP_TXSTATUS */
2843*4882a593Smuzhiyun #endif /* DHD_EXPORT_CNTL_FILE */
2844*4882a593Smuzhiyun #endif /* USE_WFA_CERT_CONF */
2845*4882a593Smuzhiyun
2846*4882a593Smuzhiyun #define dhd_add_flowid(pub, ifidx, ac_prio, ea, flowid) do {} while (0)
2847*4882a593Smuzhiyun #define dhd_del_flowid(pub, ifidx, flowid) do {} while (0)
2848*4882a593Smuzhiyun bool dhd_wet_chainable(dhd_pub_t *dhdp);
2849*4882a593Smuzhiyun
2850*4882a593Smuzhiyun extern unsigned long dhd_os_general_spin_lock(dhd_pub_t *pub);
2851*4882a593Smuzhiyun extern void dhd_os_general_spin_unlock(dhd_pub_t *pub, unsigned long flags);
2852*4882a593Smuzhiyun
2853*4882a593Smuzhiyun /** Miscellaenous DHD Spin Locks */
2854*4882a593Smuzhiyun
2855*4882a593Smuzhiyun /* Disable router 3GMAC bypass path perimeter lock */
2856*4882a593Smuzhiyun #define DHD_PERIM_LOCK(dhdp) do {} while (0)
2857*4882a593Smuzhiyun #define DHD_PERIM_UNLOCK(dhdp) do {} while (0)
2858*4882a593Smuzhiyun #define DHD_PERIM_LOCK_ALL(processor_id) do {} while (0)
2859*4882a593Smuzhiyun #define DHD_PERIM_UNLOCK_ALL(processor_id) do {} while (0)
2860*4882a593Smuzhiyun
2861*4882a593Smuzhiyun /* Enable DHD general spin lock/unlock */
2862*4882a593Smuzhiyun #define DHD_GENERAL_LOCK(dhdp, flags) \
2863*4882a593Smuzhiyun (flags) = dhd_os_general_spin_lock(dhdp)
2864*4882a593Smuzhiyun #define DHD_GENERAL_UNLOCK(dhdp, flags) \
2865*4882a593Smuzhiyun dhd_os_general_spin_unlock((dhdp), (flags))
2866*4882a593Smuzhiyun
2867*4882a593Smuzhiyun /* Enable DHD timer spin lock/unlock */
2868*4882a593Smuzhiyun #define DHD_TIMER_LOCK(lock, flags) (flags) = dhd_os_spin_lock(lock)
2869*4882a593Smuzhiyun #define DHD_TIMER_UNLOCK(lock, flags) dhd_os_spin_unlock(lock, (flags))
2870*4882a593Smuzhiyun
2871*4882a593Smuzhiyun /* Enable DHD flowring spin lock/unlock */
2872*4882a593Smuzhiyun #define DHD_FLOWRING_LOCK(lock, flags) (flags) = dhd_os_spin_lock(lock)
2873*4882a593Smuzhiyun #define DHD_FLOWRING_UNLOCK(lock, flags) dhd_os_spin_unlock((lock), (flags))
2874*4882a593Smuzhiyun
2875*4882a593Smuzhiyun /* Enable DHD common flowring info spin lock/unlock */
2876*4882a593Smuzhiyun #define DHD_FLOWID_LOCK(lock, flags) (flags) = dhd_os_spin_lock(lock)
2877*4882a593Smuzhiyun #define DHD_FLOWID_UNLOCK(lock, flags) dhd_os_spin_unlock((lock), (flags))
2878*4882a593Smuzhiyun
2879*4882a593Smuzhiyun /* Enable DHD common flowring list spin lock/unlock */
2880*4882a593Smuzhiyun #define DHD_FLOWRING_LIST_LOCK(lock, flags) (flags) = dhd_os_spin_lock(lock)
2881*4882a593Smuzhiyun #define DHD_FLOWRING_LIST_UNLOCK(lock, flags) dhd_os_spin_unlock((lock), (flags))
2882*4882a593Smuzhiyun
2883*4882a593Smuzhiyun #define DHD_SPIN_LOCK(lock, flags) (flags) = dhd_os_spin_lock(lock)
2884*4882a593Smuzhiyun #define DHD_SPIN_UNLOCK(lock, flags) dhd_os_spin_unlock((lock), (flags))
2885*4882a593Smuzhiyun
2886*4882a593Smuzhiyun #define DHD_RING_LOCK(lock, flags) (flags) = dhd_os_spin_lock(lock)
2887*4882a593Smuzhiyun #define DHD_RING_UNLOCK(lock, flags) dhd_os_spin_unlock((lock), (flags))
2888*4882a593Smuzhiyun
2889*4882a593Smuzhiyun #define DHD_BUS_LOCK(lock, flags) (flags) = dhd_os_spin_lock(lock)
2890*4882a593Smuzhiyun #define DHD_BUS_UNLOCK(lock, flags) dhd_os_spin_unlock((lock), (flags))
2891*4882a593Smuzhiyun
2892*4882a593Smuzhiyun /* Enable DHD backplane spin lock/unlock */
2893*4882a593Smuzhiyun #define DHD_BACKPLANE_ACCESS_LOCK(lock, flags) (flags) = dhd_os_spin_lock(lock)
2894*4882a593Smuzhiyun #define DHD_BACKPLANE_ACCESS_UNLOCK(lock, flags) dhd_os_spin_unlock((lock), (flags))
2895*4882a593Smuzhiyun
2896*4882a593Smuzhiyun #define DHD_BUS_INB_DW_LOCK(lock, flags) (flags) = dhd_os_spin_lock(lock)
2897*4882a593Smuzhiyun #define DHD_BUS_INB_DW_UNLOCK(lock, flags) dhd_os_spin_unlock((lock), (flags))
2898*4882a593Smuzhiyun
2899*4882a593Smuzhiyun /* Enable DHD TDLS peer list spin lock/unlock */
2900*4882a593Smuzhiyun #ifdef WLTDLS
2901*4882a593Smuzhiyun #define DHD_TDLS_LOCK(lock, flags) (flags) = dhd_os_spin_lock(lock)
2902*4882a593Smuzhiyun #define DHD_TDLS_UNLOCK(lock, flags) dhd_os_spin_unlock((lock), (flags))
2903*4882a593Smuzhiyun #endif /* WLTDLS */
2904*4882a593Smuzhiyun
2905*4882a593Smuzhiyun #define DHD_BUS_INB_DW_LOCK(lock, flags) (flags) = dhd_os_spin_lock(lock)
2906*4882a593Smuzhiyun #define DHD_BUS_INB_DW_UNLOCK(lock, flags) dhd_os_spin_unlock((lock), (flags))
2907*4882a593Smuzhiyun
2908*4882a593Smuzhiyun #ifdef DBG_PKT_MON
2909*4882a593Smuzhiyun /* Enable DHD PKT MON spin lock/unlock */
2910*4882a593Smuzhiyun #define DHD_PKT_MON_LOCK(lock, flags) (flags) = dhd_os_spin_lock(lock)
2911*4882a593Smuzhiyun #define DHD_PKT_MON_UNLOCK(lock, flags) dhd_os_spin_unlock(lock, (flags))
2912*4882a593Smuzhiyun #endif /* DBG_PKT_MON */
2913*4882a593Smuzhiyun
2914*4882a593Smuzhiyun #define DHD_LINUX_GENERAL_LOCK(dhdp, flags) DHD_GENERAL_LOCK(dhdp, flags)
2915*4882a593Smuzhiyun #define DHD_LINUX_GENERAL_UNLOCK(dhdp, flags) DHD_GENERAL_UNLOCK(dhdp, flags)
2916*4882a593Smuzhiyun
2917*4882a593Smuzhiyun /* linux is defined for DHD EFI builds also,
2918*4882a593Smuzhiyun * since its cross-compiled for EFI from linux
2919*4882a593Smuzhiyun */
2920*4882a593Smuzhiyun #define DHD_DBG_RING_LOCK_INIT(osh) dhd_os_dbgring_lock_init(osh)
2921*4882a593Smuzhiyun #define DHD_DBG_RING_LOCK_DEINIT(osh, lock) dhd_os_dbgring_lock_deinit(osh, (lock))
2922*4882a593Smuzhiyun #define DHD_DBG_RING_LOCK(lock, flags) (flags) = dhd_os_dbgring_lock(lock)
2923*4882a593Smuzhiyun #define DHD_DBG_RING_UNLOCK(lock, flags) dhd_os_dbgring_unlock((lock), flags)
2924*4882a593Smuzhiyun
2925*4882a593Smuzhiyun extern void dhd_dump_to_kernelog(dhd_pub_t *dhdp);
2926*4882a593Smuzhiyun
2927*4882a593Smuzhiyun extern void dhd_print_tasklet_status(dhd_pub_t *dhd);
2928*4882a593Smuzhiyun
2929*4882a593Smuzhiyun #ifdef DHD_L2_FILTER
2930*4882a593Smuzhiyun extern int dhd_get_parp_status(dhd_pub_t *dhdp, uint32 idx);
2931*4882a593Smuzhiyun extern int dhd_set_parp_status(dhd_pub_t *dhdp, uint32 idx, int val);
2932*4882a593Smuzhiyun extern int dhd_get_dhcp_unicast_status(dhd_pub_t *dhdp, uint32 idx);
2933*4882a593Smuzhiyun extern int dhd_set_dhcp_unicast_status(dhd_pub_t *dhdp, uint32 idx, int val);
2934*4882a593Smuzhiyun extern int dhd_get_block_ping_status(dhd_pub_t *dhdp, uint32 idx);
2935*4882a593Smuzhiyun extern int dhd_set_block_ping_status(dhd_pub_t *dhdp, uint32 idx, int val);
2936*4882a593Smuzhiyun extern int dhd_get_grat_arp_status(dhd_pub_t *dhdp, uint32 idx);
2937*4882a593Smuzhiyun extern int dhd_set_grat_arp_status(dhd_pub_t *dhdp, uint32 idx, int val);
2938*4882a593Smuzhiyun extern int dhd_get_block_tdls_status(dhd_pub_t *dhdp, uint32 idx);
2939*4882a593Smuzhiyun extern int dhd_set_block_tdls_status(dhd_pub_t *dhdp, uint32 idx, int val);
2940*4882a593Smuzhiyun #endif /* DHD_L2_FILTER */
2941*4882a593Smuzhiyun
2942*4882a593Smuzhiyun typedef struct wl_io_pport {
2943*4882a593Smuzhiyun dhd_pub_t *dhd_pub;
2944*4882a593Smuzhiyun uint ifidx;
2945*4882a593Smuzhiyun } wl_io_pport_t;
2946*4882a593Smuzhiyun
2947*4882a593Smuzhiyun typedef struct wl_evt_pport {
2948*4882a593Smuzhiyun dhd_pub_t *dhd_pub;
2949*4882a593Smuzhiyun int *ifidx;
2950*4882a593Smuzhiyun void *pktdata;
2951*4882a593Smuzhiyun uint data_len;
2952*4882a593Smuzhiyun void **data_ptr;
2953*4882a593Smuzhiyun void *raw_event;
2954*4882a593Smuzhiyun } wl_evt_pport_t;
2955*4882a593Smuzhiyun
2956*4882a593Smuzhiyun extern void *dhd_pub_shim(dhd_pub_t *dhd_pub);
2957*4882a593Smuzhiyun #ifdef DHD_FW_COREDUMP
2958*4882a593Smuzhiyun void* dhd_get_fwdump_buf(dhd_pub_t *dhd_pub, uint32 length);
2959*4882a593Smuzhiyun #endif /* DHD_FW_COREDUMP */
2960*4882a593Smuzhiyun
2961*4882a593Smuzhiyun #if defined(SET_RPS_CPUS)
2962*4882a593Smuzhiyun int dhd_rps_cpus_enable(struct net_device *net, int enable);
2963*4882a593Smuzhiyun int custom_rps_map_set(struct netdev_rx_queue *queue, char *buf, size_t len);
2964*4882a593Smuzhiyun void custom_rps_map_clear(struct netdev_rx_queue *queue);
2965*4882a593Smuzhiyun #define PRIMARY_INF 0
2966*4882a593Smuzhiyun #define VIRTUAL_INF 1
2967*4882a593Smuzhiyun #if defined(CONFIG_MACH_UNIVERSAL5433) || defined(CONFIG_MACH_UNIVERSAL7420) || \
2968*4882a593Smuzhiyun defined(CONFIG_SOC_EXYNOS8890)
2969*4882a593Smuzhiyun #define RPS_CPUS_MASK "10"
2970*4882a593Smuzhiyun #define RPS_CPUS_MASK_P2P "10"
2971*4882a593Smuzhiyun #define RPS_CPUS_MASK_IBSS "10"
2972*4882a593Smuzhiyun #define RPS_CPUS_WLAN_CORE_ID 4
2973*4882a593Smuzhiyun #else
2974*4882a593Smuzhiyun #define RPS_CPUS_MASK "6"
2975*4882a593Smuzhiyun #define RPS_CPUS_MASK_P2P "6"
2976*4882a593Smuzhiyun #define RPS_CPUS_MASK_IBSS "6"
2977*4882a593Smuzhiyun #endif /* CONFIG_MACH_UNIVERSAL5433 || CONFIG_MACH_UNIVERSAL7420 || CONFIG_SOC_EXYNOS8890 */
2978*4882a593Smuzhiyun #endif // endif
2979*4882a593Smuzhiyun
2980*4882a593Smuzhiyun int dhd_get_download_buffer(dhd_pub_t *dhd, char *file_path, download_type_t component,
2981*4882a593Smuzhiyun char ** buffer, int *length);
2982*4882a593Smuzhiyun
2983*4882a593Smuzhiyun void dhd_free_download_buffer(dhd_pub_t *dhd, void *buffer, int length);
2984*4882a593Smuzhiyun
2985*4882a593Smuzhiyun int dhd_download_blob(dhd_pub_t *dhd, unsigned char *buf,
2986*4882a593Smuzhiyun uint32 len, char *iovar);
2987*4882a593Smuzhiyun
2988*4882a593Smuzhiyun int dhd_download_blob_cached(dhd_pub_t *dhd, char *file_path,
2989*4882a593Smuzhiyun uint32 len, char *iovar);
2990*4882a593Smuzhiyun
2991*4882a593Smuzhiyun int dhd_apply_default_txcap(dhd_pub_t *dhd, char *txcap_path);
2992*4882a593Smuzhiyun int dhd_apply_default_clm(dhd_pub_t *dhd, char *clm_path);
2993*4882a593Smuzhiyun
2994*4882a593Smuzhiyun #ifdef SHOW_LOGTRACE
2995*4882a593Smuzhiyun int dhd_parse_logstrs_file(osl_t *osh, char *raw_fmts, int logstrs_size,
2996*4882a593Smuzhiyun dhd_event_log_t *event_log);
2997*4882a593Smuzhiyun int dhd_parse_map_file(osl_t *osh, void *file, uint32 *ramstart,
2998*4882a593Smuzhiyun uint32 *rodata_start, uint32 *rodata_end);
2999*4882a593Smuzhiyun #ifdef PCIE_FULL_DONGLE
3000*4882a593Smuzhiyun int dhd_event_logtrace_infobuf_pkt_process(dhd_pub_t *dhdp, void *pktbuf,
3001*4882a593Smuzhiyun dhd_event_log_t *event_data);
3002*4882a593Smuzhiyun #endif /* PCIE_FULL_DONGLE */
3003*4882a593Smuzhiyun #endif /* SHOW_LOGTRACE */
3004*4882a593Smuzhiyun
3005*4882a593Smuzhiyun #define dhd_is_device_removed(x) FALSE
3006*4882a593Smuzhiyun #define dhd_os_ind_firmware_stall(x)
3007*4882a593Smuzhiyun
3008*4882a593Smuzhiyun #if defined(DHD_FW_COREDUMP)
3009*4882a593Smuzhiyun extern void dhd_get_memdump_info(dhd_pub_t *dhd);
3010*4882a593Smuzhiyun #endif /* defined(DHD_FW_COREDUMP) */
3011*4882a593Smuzhiyun #ifdef BCMASSERT_LOG
3012*4882a593Smuzhiyun extern void dhd_get_assert_info(dhd_pub_t *dhd);
3013*4882a593Smuzhiyun #else
dhd_get_assert_info(dhd_pub_t * dhd)3014*4882a593Smuzhiyun static INLINE void dhd_get_assert_info(dhd_pub_t *dhd) { }
3015*4882a593Smuzhiyun #endif /* BCMASSERT_LOG */
3016*4882a593Smuzhiyun
3017*4882a593Smuzhiyun #define DMAXFER_FREE(dhdp, dmap) dhd_schedule_dmaxfer_free(dhdp, dmap);
3018*4882a593Smuzhiyun
3019*4882a593Smuzhiyun #if defined(PCIE_FULL_DONGLE)
3020*4882a593Smuzhiyun extern void dmaxfer_free_prev_dmaaddr(dhd_pub_t *dhdp, dmaxref_mem_map_t *dmmap);
3021*4882a593Smuzhiyun void dhd_schedule_dmaxfer_free(dhd_pub_t *dhdp, dmaxref_mem_map_t *dmmap);
3022*4882a593Smuzhiyun #endif /* PCIE_FULL_DONGLE */
3023*4882a593Smuzhiyun
3024*4882a593Smuzhiyun #define DHD_LB_STATS_NOOP do { /* noop */ } while (0)
3025*4882a593Smuzhiyun #if defined(DHD_LB_STATS)
3026*4882a593Smuzhiyun #include <bcmutils.h>
3027*4882a593Smuzhiyun extern void dhd_lb_stats_init(dhd_pub_t *dhd);
3028*4882a593Smuzhiyun extern void dhd_lb_stats_deinit(dhd_pub_t *dhd);
3029*4882a593Smuzhiyun extern void dhd_lb_stats_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf);
3030*4882a593Smuzhiyun extern void dhd_lb_stats_update_napi_histo(dhd_pub_t *dhdp, uint32 count);
3031*4882a593Smuzhiyun extern void dhd_lb_stats_update_txc_histo(dhd_pub_t *dhdp, uint32 count);
3032*4882a593Smuzhiyun extern void dhd_lb_stats_update_rxc_histo(dhd_pub_t *dhdp, uint32 count);
3033*4882a593Smuzhiyun extern void dhd_lb_stats_txc_percpu_cnt_incr(dhd_pub_t *dhdp);
3034*4882a593Smuzhiyun extern void dhd_lb_stats_rxc_percpu_cnt_incr(dhd_pub_t *dhdp);
3035*4882a593Smuzhiyun #define DHD_LB_STATS_INIT(dhdp) dhd_lb_stats_init(dhdp)
3036*4882a593Smuzhiyun #define DHD_LB_STATS_DEINIT(dhdp) dhd_lb_stats_deinit(dhdp)
3037*4882a593Smuzhiyun /* Reset is called from common layer so it takes dhd_pub_t as argument */
3038*4882a593Smuzhiyun #define DHD_LB_STATS_RESET(dhdp) dhd_lb_stats_init(dhdp)
3039*4882a593Smuzhiyun #define DHD_LB_STATS_CLR(x) (x) = 0U
3040*4882a593Smuzhiyun #define DHD_LB_STATS_INCR(x) (x) = (x) + 1
3041*4882a593Smuzhiyun #define DHD_LB_STATS_ADD(x, c) (x) = (x) + (c)
3042*4882a593Smuzhiyun #define DHD_LB_STATS_PERCPU_ARR_INCR(x) \
3043*4882a593Smuzhiyun { \
3044*4882a593Smuzhiyun int cpu = get_cpu(); put_cpu(); \
3045*4882a593Smuzhiyun DHD_LB_STATS_INCR(x[cpu]); \
3046*4882a593Smuzhiyun }
3047*4882a593Smuzhiyun #define DHD_LB_STATS_UPDATE_NAPI_HISTO(dhdp, x) dhd_lb_stats_update_napi_histo(dhdp, x)
3048*4882a593Smuzhiyun #define DHD_LB_STATS_UPDATE_TXC_HISTO(dhdp, x) dhd_lb_stats_update_txc_histo(dhdp, x)
3049*4882a593Smuzhiyun #define DHD_LB_STATS_UPDATE_RXC_HISTO(dhdp, x) dhd_lb_stats_update_rxc_histo(dhdp, x)
3050*4882a593Smuzhiyun #define DHD_LB_STATS_TXC_PERCPU_CNT_INCR(dhdp) dhd_lb_stats_txc_percpu_cnt_incr(dhdp)
3051*4882a593Smuzhiyun #define DHD_LB_STATS_RXC_PERCPU_CNT_INCR(dhdp) dhd_lb_stats_rxc_percpu_cnt_incr(dhdp)
3052*4882a593Smuzhiyun #else /* !DHD_LB_STATS */
3053*4882a593Smuzhiyun #define DHD_LB_STATS_INIT(dhdp) DHD_LB_STATS_NOOP
3054*4882a593Smuzhiyun #define DHD_LB_STATS_DEINIT(dhdp) DHD_LB_STATS_NOOP
3055*4882a593Smuzhiyun #define DHD_LB_STATS_RESET(dhdp) DHD_LB_STATS_NOOP
3056*4882a593Smuzhiyun #define DHD_LB_STATS_CLR(x) DHD_LB_STATS_NOOP
3057*4882a593Smuzhiyun #define DHD_LB_STATS_INCR(x) DHD_LB_STATS_NOOP
3058*4882a593Smuzhiyun #define DHD_LB_STATS_ADD(x, c) DHD_LB_STATS_NOOP
3059*4882a593Smuzhiyun #define DHD_LB_STATS_PERCPU_ARR_INCR(x) DHD_LB_STATS_NOOP
3060*4882a593Smuzhiyun #define DHD_LB_STATS_UPDATE_NAPI_HISTO(dhd, x) DHD_LB_STATS_NOOP
3061*4882a593Smuzhiyun #define DHD_LB_STATS_UPDATE_TXC_HISTO(dhd, x) DHD_LB_STATS_NOOP
3062*4882a593Smuzhiyun #define DHD_LB_STATS_UPDATE_RXC_HISTO(dhd, x) DHD_LB_STATS_NOOP
3063*4882a593Smuzhiyun #define DHD_LB_STATS_TXC_PERCPU_CNT_INCR(dhdp) DHD_LB_STATS_NOOP
3064*4882a593Smuzhiyun #define DHD_LB_STATS_RXC_PERCPU_CNT_INCR(dhdp) DHD_LB_STATS_NOOP
3065*4882a593Smuzhiyun #endif /* !DHD_LB_STATS */
3066*4882a593Smuzhiyun
3067*4882a593Smuzhiyun #ifdef DHD_SSSR_DUMP
3068*4882a593Smuzhiyun #define DHD_SSSR_MEMPOOL_SIZE (2 * 1024 * 1024) /* 2MB size */
3069*4882a593Smuzhiyun
3070*4882a593Smuzhiyun /* used in sssr_dump_mode */
3071*4882a593Smuzhiyun #define SSSR_DUMP_MODE_SSSR 0 /* dump both *before* and *after* files */
3072*4882a593Smuzhiyun #define SSSR_DUMP_MODE_FIS 1 /* dump *after* files only */
3073*4882a593Smuzhiyun
3074*4882a593Smuzhiyun extern int dhd_sssr_mempool_init(dhd_pub_t *dhd);
3075*4882a593Smuzhiyun extern void dhd_sssr_mempool_deinit(dhd_pub_t *dhd);
3076*4882a593Smuzhiyun extern int dhd_sssr_dump_init(dhd_pub_t *dhd);
3077*4882a593Smuzhiyun extern void dhd_sssr_dump_deinit(dhd_pub_t *dhd);
3078*4882a593Smuzhiyun extern int dhdpcie_sssr_dump(dhd_pub_t *dhd);
3079*4882a593Smuzhiyun extern void dhd_sssr_print_filepath(dhd_pub_t *dhd, char *path);
3080*4882a593Smuzhiyun
3081*4882a593Smuzhiyun #define DHD_SSSR_MEMPOOL_INIT(dhdp) dhd_sssr_mempool_init(dhdp)
3082*4882a593Smuzhiyun #define DHD_SSSR_MEMPOOL_DEINIT(dhdp) dhd_sssr_mempool_deinit(dhdp)
3083*4882a593Smuzhiyun #define DHD_SSSR_DUMP_INIT(dhdp) dhd_sssr_dump_init(dhdp)
3084*4882a593Smuzhiyun #define DHD_SSSR_DUMP_DEINIT(dhdp) dhd_sssr_dump_deinit(dhdp)
3085*4882a593Smuzhiyun #define DHD_SSSR_PRINT_FILEPATH(dhdp, path) dhd_sssr_print_filepath(dhdp, path)
3086*4882a593Smuzhiyun #else
3087*4882a593Smuzhiyun #define DHD_SSSR_MEMPOOL_INIT(dhdp) do { /* noop */ } while (0)
3088*4882a593Smuzhiyun #define DHD_SSSR_MEMPOOL_DEINIT(dhdp) do { /* noop */ } while (0)
3089*4882a593Smuzhiyun #define DHD_SSSR_DUMP_INIT(dhdp) do { /* noop */ } while (0)
3090*4882a593Smuzhiyun #define DHD_SSSR_DUMP_DEINIT(dhdp) do { /* noop */ } while (0)
3091*4882a593Smuzhiyun #define DHD_SSSR_PRINT_FILEPATH(dhdp, path) do { /* noop */ } while (0)
3092*4882a593Smuzhiyun #endif /* DHD_SSSR_DUMP */
3093*4882a593Smuzhiyun
3094*4882a593Smuzhiyun #ifdef BCMPCIE
3095*4882a593Smuzhiyun extern int dhd_prot_debug_info_print(dhd_pub_t *dhd);
3096*4882a593Smuzhiyun extern bool dhd_bus_skip_clm(dhd_pub_t *dhdp);
3097*4882a593Smuzhiyun extern void dhd_pcie_dump_rc_conf_space_cap(dhd_pub_t *dhd);
3098*4882a593Smuzhiyun extern bool dhd_pcie_dump_int_regs(dhd_pub_t *dhd);
3099*4882a593Smuzhiyun #else
3100*4882a593Smuzhiyun #define dhd_prot_debug_info_print(x)
dhd_bus_skip_clm(dhd_pub_t * dhd_pub)3101*4882a593Smuzhiyun static INLINE bool dhd_bus_skip_clm(dhd_pub_t *dhd_pub)
3102*4882a593Smuzhiyun { return 0; }
3103*4882a593Smuzhiyun #endif /* BCMPCIE */
3104*4882a593Smuzhiyun
3105*4882a593Smuzhiyun fw_download_status_t dhd_fw_download_status(dhd_pub_t * dhd_pub);
3106*4882a593Smuzhiyun void dhd_show_kirqstats(dhd_pub_t *dhd);
3107*4882a593Smuzhiyun
3108*4882a593Smuzhiyun /* Bitmask used for Join Timeout */
3109*4882a593Smuzhiyun #define WLC_SSID_MASK 0x01
3110*4882a593Smuzhiyun #define WLC_WPA_MASK 0x02
3111*4882a593Smuzhiyun
3112*4882a593Smuzhiyun extern int dhd_start_join_timer(dhd_pub_t *pub);
3113*4882a593Smuzhiyun extern int dhd_stop_join_timer(dhd_pub_t *pub);
3114*4882a593Smuzhiyun extern int dhd_start_scan_timer(dhd_pub_t *pub, bool is_escan);
3115*4882a593Smuzhiyun extern int dhd_stop_scan_timer(dhd_pub_t *pub, bool is_escan, uint16 sync_id);
3116*4882a593Smuzhiyun extern int dhd_start_cmd_timer(dhd_pub_t *pub);
3117*4882a593Smuzhiyun extern int dhd_stop_cmd_timer(dhd_pub_t *pub);
3118*4882a593Smuzhiyun extern int dhd_start_bus_timer(dhd_pub_t *pub);
3119*4882a593Smuzhiyun extern int dhd_stop_bus_timer(dhd_pub_t *pub);
3120*4882a593Smuzhiyun extern uint16 dhd_get_request_id(dhd_pub_t *pub);
3121*4882a593Smuzhiyun extern int dhd_set_request_id(dhd_pub_t *pub, uint16 id, uint32 cmd);
3122*4882a593Smuzhiyun extern void dhd_set_join_error(dhd_pub_t *pub, uint32 mask);
3123*4882a593Smuzhiyun extern void dhd_clear_join_error(dhd_pub_t *pub, uint32 mask);
3124*4882a593Smuzhiyun extern void dhd_get_scan_to_val(dhd_pub_t *pub, uint32 *to_val);
3125*4882a593Smuzhiyun extern void dhd_set_scan_to_val(dhd_pub_t *pub, uint32 to_val);
3126*4882a593Smuzhiyun extern void dhd_get_join_to_val(dhd_pub_t *pub, uint32 *to_val);
3127*4882a593Smuzhiyun extern void dhd_set_join_to_val(dhd_pub_t *pub, uint32 to_val);
3128*4882a593Smuzhiyun extern void dhd_get_cmd_to_val(dhd_pub_t *pub, uint32 *to_val);
3129*4882a593Smuzhiyun extern void dhd_set_cmd_to_val(dhd_pub_t *pub, uint32 to_val);
3130*4882a593Smuzhiyun extern void dhd_get_bus_to_val(dhd_pub_t *pub, uint32 *to_val);
3131*4882a593Smuzhiyun extern void dhd_set_bus_to_val(dhd_pub_t *pub, uint32 to_val);
3132*4882a593Smuzhiyun extern int dhd_start_timesync_timer(dhd_pub_t *pub);
3133*4882a593Smuzhiyun extern int dhd_stop_timesync_timer(dhd_pub_t *pub);
3134*4882a593Smuzhiyun
3135*4882a593Smuzhiyun #ifdef DHD_PKTID_AUDIT_ENABLED
3136*4882a593Smuzhiyun void dhd_pktid_error_handler(dhd_pub_t *dhdp);
3137*4882a593Smuzhiyun #endif /* DHD_PKTID_AUDIT_ENABLED */
3138*4882a593Smuzhiyun
3139*4882a593Smuzhiyun #ifdef DHD_MAP_PKTID_LOGGING
3140*4882a593Smuzhiyun extern void dhd_pktid_logging_dump(dhd_pub_t *dhdp);
3141*4882a593Smuzhiyun #endif /* DHD_MAP_PKTID_LOGGING */
3142*4882a593Smuzhiyun
3143*4882a593Smuzhiyun #ifdef DHD_PCIE_RUNTIMEPM
3144*4882a593Smuzhiyun extern bool dhd_runtimepm_state(dhd_pub_t *dhd);
3145*4882a593Smuzhiyun extern bool dhd_runtime_bus_wake(struct dhd_bus *bus, bool wait, void *func_addr);
3146*4882a593Smuzhiyun extern bool dhdpcie_runtime_bus_wake(dhd_pub_t *dhdp, bool wait, void *func_addr);
3147*4882a593Smuzhiyun extern void dhdpcie_block_runtime_pm(dhd_pub_t *dhdp);
3148*4882a593Smuzhiyun extern bool dhdpcie_is_resume_done(dhd_pub_t *dhdp);
3149*4882a593Smuzhiyun extern void dhd_runtime_pm_disable(dhd_pub_t *dhdp);
3150*4882a593Smuzhiyun extern void dhd_runtime_pm_enable(dhd_pub_t *dhdp);
3151*4882a593Smuzhiyun /* Disable the Runtime PM and wake up if the bus is already in suspend */
3152*4882a593Smuzhiyun #define DHD_DISABLE_RUNTIME_PM(dhdp) \
3153*4882a593Smuzhiyun do { \
3154*4882a593Smuzhiyun dhd_runtime_pm_disable(dhdp); \
3155*4882a593Smuzhiyun } while (0);
3156*4882a593Smuzhiyun
3157*4882a593Smuzhiyun /* Enable the Runtime PM */
3158*4882a593Smuzhiyun #define DHD_ENABLE_RUNTIME_PM(dhdp) \
3159*4882a593Smuzhiyun do { \
3160*4882a593Smuzhiyun dhd_runtime_pm_enable(dhdp); \
3161*4882a593Smuzhiyun } while (0);
3162*4882a593Smuzhiyun #else
3163*4882a593Smuzhiyun #define DHD_DISABLE_RUNTIME_PM(dhdp)
3164*4882a593Smuzhiyun #define DHD_ENABLE_RUNTIME_PM(dhdp)
3165*4882a593Smuzhiyun #endif /* DHD_PCIE_RUNTIMEPM */
3166*4882a593Smuzhiyun
3167*4882a593Smuzhiyun #ifdef REVERSE_AIFSN
3168*4882a593Smuzhiyun extern int check_reverse_aifsn_condition(dhd_pub_t *dhdp, struct net_device *ndev);
3169*4882a593Smuzhiyun
3170*4882a593Smuzhiyun #define DHD_REVERSE_AIFSN(dhdp, ndev) \
3171*4882a593Smuzhiyun do { \
3172*4882a593Smuzhiyun check_reverse_aifsn_condition(dhdp, ndev); \
3173*4882a593Smuzhiyun } while (0);
3174*4882a593Smuzhiyun #else
3175*4882a593Smuzhiyun #define DHD_REVERSE_AIFSN(dhdp, ndev)
3176*4882a593Smuzhiyun #endif /* AIFSN_REVERSE */
3177*4882a593Smuzhiyun
3178*4882a593Smuzhiyun extern bool dhd_prot_is_cmpl_ring_empty(dhd_pub_t *dhd, void *prot_info);
3179*4882a593Smuzhiyun extern void dhd_prot_dump_ring_ptrs(void *prot_info);
3180*4882a593Smuzhiyun
3181*4882a593Smuzhiyun #if defined(DHD_TRACE_WAKE_LOCK)
3182*4882a593Smuzhiyun void dhd_wk_lock_stats_dump(dhd_pub_t *dhdp);
3183*4882a593Smuzhiyun #endif // endif
3184*4882a593Smuzhiyun
3185*4882a593Smuzhiyun extern bool dhd_query_bus_erros(dhd_pub_t *dhdp);
3186*4882a593Smuzhiyun void dhd_clear_bus_errors(dhd_pub_t *dhdp);
3187*4882a593Smuzhiyun
3188*4882a593Smuzhiyun #if defined(CONFIG_64BIT)
3189*4882a593Smuzhiyun #define DHD_SUPPORT_64BIT
3190*4882a593Smuzhiyun #endif /* (linux || LINUX) && CONFIG_64BIT */
3191*4882a593Smuzhiyun
3192*4882a593Smuzhiyun #if defined(DHD_ERPOM)
3193*4882a593Smuzhiyun extern void dhd_schedule_reset(dhd_pub_t *dhdp);
3194*4882a593Smuzhiyun #else
dhd_schedule_reset(dhd_pub_t * dhdp)3195*4882a593Smuzhiyun static INLINE void dhd_schedule_reset(dhd_pub_t *dhdp) {;}
3196*4882a593Smuzhiyun #endif // endif
3197*4882a593Smuzhiyun
3198*4882a593Smuzhiyun extern void init_dhd_timeouts(dhd_pub_t *pub);
3199*4882a593Smuzhiyun extern void deinit_dhd_timeouts(dhd_pub_t *pub);
3200*4882a593Smuzhiyun
3201*4882a593Smuzhiyun typedef enum timeout_resons {
3202*4882a593Smuzhiyun DHD_REASON_COMMAND_TO,
3203*4882a593Smuzhiyun DHD_REASON_JOIN_TO,
3204*4882a593Smuzhiyun DHD_REASON_SCAN_TO,
3205*4882a593Smuzhiyun DHD_REASON_OQS_TO
3206*4882a593Smuzhiyun } timeout_reasons_t;
3207*4882a593Smuzhiyun
3208*4882a593Smuzhiyun extern void dhd_prhex(const char *msg, volatile uchar *buf, uint nbytes, uint8 dbg_level);
3209*4882a593Smuzhiyun int dhd_tput_test(dhd_pub_t *dhd, tput_test_t *tput_data);
3210*4882a593Smuzhiyun void dhd_tput_test_rx(dhd_pub_t *dhd, void *pkt);
dhd_get_max_txbufs(dhd_pub_t * dhdp)3211*4882a593Smuzhiyun static INLINE int dhd_get_max_txbufs(dhd_pub_t *dhdp)
3212*4882a593Smuzhiyun { return -1; }
3213*4882a593Smuzhiyun
3214*4882a593Smuzhiyun #ifdef FILTER_IE
3215*4882a593Smuzhiyun int dhd_read_from_file(dhd_pub_t *dhd);
3216*4882a593Smuzhiyun int dhd_parse_filter_ie(dhd_pub_t *dhd, uint8 *buf);
3217*4882a593Smuzhiyun int dhd_get_filter_ie_count(dhd_pub_t *dhd, uint8 *buf);
3218*4882a593Smuzhiyun int dhd_parse_oui(dhd_pub_t *dhd, uint8 *inbuf, uint8 *oui, int len);
3219*4882a593Smuzhiyun int dhd_check_valid_ie(dhd_pub_t *dhdp, uint8 *buf, int len);
3220*4882a593Smuzhiyun #endif /* FILTER_IE */
3221*4882a593Smuzhiyun
3222*4882a593Smuzhiyun uint16 dhd_prot_get_ioctl_trans_id(dhd_pub_t *dhdp);
3223*4882a593Smuzhiyun
3224*4882a593Smuzhiyun #ifdef SET_PCIE_IRQ_CPU_CORE
3225*4882a593Smuzhiyun enum {
3226*4882a593Smuzhiyun PCIE_IRQ_AFFINITY_OFF = 0,
3227*4882a593Smuzhiyun PCIE_IRQ_AFFINITY_BIG_CORE_ANY,
3228*4882a593Smuzhiyun PCIE_IRQ_AFFINITY_BIG_CORE_EXYNOS,
3229*4882a593Smuzhiyun PCIE_IRQ_AFFINITY_LAST
3230*4882a593Smuzhiyun };
3231*4882a593Smuzhiyun extern void dhd_set_irq_cpucore(dhd_pub_t *dhdp, int affinity_cmd);
3232*4882a593Smuzhiyun #endif /* SET_PCIE_IRQ_CPU_CORE */
3233*4882a593Smuzhiyun
3234*4882a593Smuzhiyun #if defined(DHD_HANG_SEND_UP_TEST)
3235*4882a593Smuzhiyun extern void dhd_make_hang_with_reason(struct net_device *dev, const char *string_num);
3236*4882a593Smuzhiyun #endif /* DHD_HANG_SEND_UP_TEST */
3237*4882a593Smuzhiyun
3238*4882a593Smuzhiyun #ifdef DHD_RND_DEBUG
3239*4882a593Smuzhiyun int dhd_dump_rnd_info(dhd_pub_t *dhd, uint8 *rnd_buf, uint32 rnd_len);
3240*4882a593Smuzhiyun int dhd_get_rnd_info(dhd_pub_t *dhd);
3241*4882a593Smuzhiyun #endif /* DHD_RND_DEBUG */
3242*4882a593Smuzhiyun
3243*4882a593Smuzhiyun #ifdef DHD_WAKE_STATUS
3244*4882a593Smuzhiyun wake_counts_t* dhd_get_wakecount(dhd_pub_t *dhdp);
3245*4882a593Smuzhiyun #endif /* DHD_WAKE_STATUS */
3246*4882a593Smuzhiyun extern int dhd_get_random_bytes(uint8 *buf, uint len);
3247*4882a593Smuzhiyun #if defined(DHD_BLOB_EXISTENCE_CHECK)
3248*4882a593Smuzhiyun extern void dhd_set_blob_support(dhd_pub_t *dhdp, char *fw_path);
3249*4882a593Smuzhiyun #endif /* DHD_BLOB_EXISTENCE_CHECK */
3250*4882a593Smuzhiyun
3251*4882a593Smuzhiyun /* configuration of ecounters. API's tp start/stop. currently supported only for linux */
3252*4882a593Smuzhiyun extern int dhd_ecounter_configure(dhd_pub_t *dhd, bool enable);
3253*4882a593Smuzhiyun extern int dhd_start_ecounters(dhd_pub_t *dhd);
3254*4882a593Smuzhiyun extern int dhd_stop_ecounters(dhd_pub_t *dhd);
3255*4882a593Smuzhiyun extern int dhd_start_event_ecounters(dhd_pub_t *dhd);
3256*4882a593Smuzhiyun extern int dhd_stop_event_ecounters(dhd_pub_t *dhd);
3257*4882a593Smuzhiyun
3258*4882a593Smuzhiyun int dhd_get_preserve_log_numbers(dhd_pub_t *dhd, uint32 *logset_mask);
3259*4882a593Smuzhiyun
3260*4882a593Smuzhiyun #ifdef DHD_LOG_DUMP
3261*4882a593Smuzhiyun void dhd_schedule_log_dump(dhd_pub_t *dhdp, void *type);
3262*4882a593Smuzhiyun void dhd_log_dump_trigger(dhd_pub_t *dhdp, int subcmd);
3263*4882a593Smuzhiyun int dhd_log_dump_ring_to_file(dhd_pub_t *dhdp, void *ring_ptr, void *file,
3264*4882a593Smuzhiyun unsigned long *file_posn, log_dump_section_hdr_t *sec_hdr, char *text_hdr,
3265*4882a593Smuzhiyun uint32 sec_type);
3266*4882a593Smuzhiyun int dhd_dump_debug_ring(dhd_pub_t *dhdp, void *ring_ptr, const void *user_buf,
3267*4882a593Smuzhiyun log_dump_section_hdr_t *sec_hdr, char *text_hdr, int buflen, uint32 sec_type);
3268*4882a593Smuzhiyun int dhd_log_dump_cookie_to_file(dhd_pub_t *dhdp, void *fp,
3269*4882a593Smuzhiyun const void *user_buf, unsigned long *f_pos);
3270*4882a593Smuzhiyun int dhd_log_dump_cookie(dhd_pub_t *dhdp, const void *user_buf);
3271*4882a593Smuzhiyun uint32 dhd_log_dump_cookie_len(dhd_pub_t *dhdp);
3272*4882a593Smuzhiyun int dhd_logdump_cookie_init(dhd_pub_t *dhdp, uint8 *buf, uint32 buf_size);
3273*4882a593Smuzhiyun void dhd_logdump_cookie_deinit(dhd_pub_t *dhdp);
3274*4882a593Smuzhiyun void dhd_logdump_cookie_save(dhd_pub_t *dhdp, char *cookie, char *type);
3275*4882a593Smuzhiyun int dhd_logdump_cookie_get(dhd_pub_t *dhdp, char *ret_cookie, uint32 buf_size);
3276*4882a593Smuzhiyun int dhd_logdump_cookie_count(dhd_pub_t *dhdp);
3277*4882a593Smuzhiyun int dhd_get_dld_log_dump(void *dev, dhd_pub_t *dhdp, const void *user_buf, void *fp,
3278*4882a593Smuzhiyun uint32 len, int type, void *pos);
3279*4882a593Smuzhiyun int dhd_print_ext_trap_data(void *dev, dhd_pub_t *dhdp, const void *user_buf,
3280*4882a593Smuzhiyun void *fp, uint32 len, void *pos);
3281*4882a593Smuzhiyun int dhd_print_dump_data(void *dev, dhd_pub_t *dhdp, const void *user_buf,
3282*4882a593Smuzhiyun void *fp, uint32 len, void *pos);
3283*4882a593Smuzhiyun int dhd_print_cookie_data(void *dev, dhd_pub_t *dhdp, const void *user_buf,
3284*4882a593Smuzhiyun void *fp, uint32 len, void *pos);
3285*4882a593Smuzhiyun int dhd_print_health_chk_data(void *dev, dhd_pub_t *dhdp, const void *user_buf,
3286*4882a593Smuzhiyun void *fp, uint32 len, void *pos);
3287*4882a593Smuzhiyun int dhd_print_time_str(const void *user_buf, void *fp, uint32 len, void *pos);
3288*4882a593Smuzhiyun #ifdef DHD_DUMP_PCIE_RINGS
3289*4882a593Smuzhiyun int dhd_print_flowring_data(void *dev, dhd_pub_t *dhdp, const void *user_buf,
3290*4882a593Smuzhiyun void *fp, uint32 len, void *pos);
3291*4882a593Smuzhiyun uint32 dhd_get_flowring_len(void *ndev, dhd_pub_t *dhdp);
3292*4882a593Smuzhiyun #endif /* DHD_DUMP_PCIE_RINGS */
3293*4882a593Smuzhiyun #ifdef DHD_STATUS_LOGGING
3294*4882a593Smuzhiyun extern int dhd_print_status_log_data(void *dev, dhd_pub_t *dhdp,
3295*4882a593Smuzhiyun const void *user_buf, void *fp, uint32 len, void *pos);
3296*4882a593Smuzhiyun extern uint32 dhd_get_status_log_len(void *ndev, dhd_pub_t *dhdp);
3297*4882a593Smuzhiyun #endif /* DHD_STATUS_LOGGING */
3298*4882a593Smuzhiyun int dhd_print_ecntrs_data(void *dev, dhd_pub_t *dhdp, const void *user_buf,
3299*4882a593Smuzhiyun void *fp, uint32 len, void *pos);
3300*4882a593Smuzhiyun int dhd_print_rtt_data(void *dev, dhd_pub_t *dhdp, const void *user_buf,
3301*4882a593Smuzhiyun void *fp, uint32 len, void *pos);
3302*4882a593Smuzhiyun int dhd_get_debug_dump_file_name(void *dev, dhd_pub_t *dhdp,
3303*4882a593Smuzhiyun char *dump_path, int size);
3304*4882a593Smuzhiyun uint32 dhd_get_ext_trap_len(void *ndev, dhd_pub_t *dhdp);
3305*4882a593Smuzhiyun uint32 dhd_get_time_str_len(void);
3306*4882a593Smuzhiyun uint32 dhd_get_health_chk_len(void *ndev, dhd_pub_t *dhdp);
3307*4882a593Smuzhiyun uint32 dhd_get_dhd_dump_len(void *ndev, dhd_pub_t *dhdp);
3308*4882a593Smuzhiyun uint32 dhd_get_cookie_log_len(void *ndev, dhd_pub_t *dhdp);
3309*4882a593Smuzhiyun uint32 dhd_get_ecntrs_len(void *ndev, dhd_pub_t *dhdp);
3310*4882a593Smuzhiyun uint32 dhd_get_rtt_len(void *ndev, dhd_pub_t *dhdp);
3311*4882a593Smuzhiyun uint32 dhd_get_dld_len(int log_type);
3312*4882a593Smuzhiyun void dhd_init_sec_hdr(log_dump_section_hdr_t *sec_hdr);
3313*4882a593Smuzhiyun extern char *dhd_log_dump_get_timestamp(void);
3314*4882a593Smuzhiyun bool dhd_log_dump_ecntr_enabled(void);
3315*4882a593Smuzhiyun bool dhd_log_dump_rtt_enabled(void);
3316*4882a593Smuzhiyun void dhd_nla_put_sssr_dump_len(void *ndev, uint32 *arr_len);
3317*4882a593Smuzhiyun int dhd_get_debug_dump(void *dev, const void *user_buf, uint32 len, int type);
3318*4882a593Smuzhiyun int
3319*4882a593Smuzhiyun dhd_sssr_dump_d11_buf_before(void *dev, const void *user_buf, uint32 len, int core);
3320*4882a593Smuzhiyun int
3321*4882a593Smuzhiyun dhd_sssr_dump_d11_buf_after(void *dev, const void *user_buf, uint32 len, int core);
3322*4882a593Smuzhiyun int
3323*4882a593Smuzhiyun dhd_sssr_dump_dig_buf_before(void *dev, const void *user_buf, uint32 len);
3324*4882a593Smuzhiyun int
3325*4882a593Smuzhiyun dhd_sssr_dump_dig_buf_after(void *dev, const void *user_buf, uint32 len);
3326*4882a593Smuzhiyun #ifdef DHD_PKT_LOGGING
3327*4882a593Smuzhiyun extern int dhd_os_get_pktlog_dump(void *dev, const void *user_buf, uint32 len);
3328*4882a593Smuzhiyun extern uint32 dhd_os_get_pktlog_dump_size(struct net_device *dev);
3329*4882a593Smuzhiyun extern void dhd_os_get_pktlogdump_filename(struct net_device *dev, char *dump_path, int len);
3330*4882a593Smuzhiyun #endif /* DHD_PKT_LOGGING */
3331*4882a593Smuzhiyun
3332*4882a593Smuzhiyun #ifdef DNGL_AXI_ERROR_LOGGING
3333*4882a593Smuzhiyun extern int dhd_os_get_axi_error_dump(void *dev, const void *user_buf, uint32 len);
3334*4882a593Smuzhiyun extern int dhd_os_get_axi_error_dump_size(struct net_device *dev);
3335*4882a593Smuzhiyun extern void dhd_os_get_axi_error_filename(struct net_device *dev, char *dump_path, int len);
3336*4882a593Smuzhiyun #endif /* DNGL_AXI_ERROR_LOGGING */
3337*4882a593Smuzhiyun
3338*4882a593Smuzhiyun #endif /* DHD_LOG_DUMP */
3339*4882a593Smuzhiyun int dhd_export_debug_data(void *mem_buf, void *fp, const void *user_buf, int buf_len, void *pos);
3340*4882a593Smuzhiyun #define DHD_PCIE_CONFIG_SAVE(bus) pci_save_state(bus->dev)
3341*4882a593Smuzhiyun #define DHD_PCIE_CONFIG_RESTORE(bus) pci_restore_state(bus->dev)
3342*4882a593Smuzhiyun
3343*4882a593Smuzhiyun #ifdef BIGDATA_SOFTAP
3344*4882a593Smuzhiyun void dhd_schedule_gather_ap_stadata(void *bcm_cfg, void *ndev, const wl_event_msg_t *e);
3345*4882a593Smuzhiyun #endif /* BIGDATA_SOFTAP */
3346*4882a593Smuzhiyun
3347*4882a593Smuzhiyun typedef struct dhd_pkt_parse {
3348*4882a593Smuzhiyun uint32 proto; /* Network layer protocol */
3349*4882a593Smuzhiyun uint32 t1; /* n-tuple */
3350*4882a593Smuzhiyun uint32 t2;
3351*4882a593Smuzhiyun } dhd_pkt_parse_t;
3352*4882a593Smuzhiyun
3353*4882a593Smuzhiyun /* ========= RING API functions : exposed to others ============= */
3354*4882a593Smuzhiyun #define DHD_RING_TYPE_FIXED 1
3355*4882a593Smuzhiyun #define DHD_RING_TYPE_SINGLE_IDX 2
3356*4882a593Smuzhiyun uint32 dhd_ring_get_hdr_size(void);
3357*4882a593Smuzhiyun void *dhd_ring_init(dhd_pub_t *dhdp, uint8 *buf, uint32 buf_size, uint32 elem_size,
3358*4882a593Smuzhiyun uint32 elem_cnt, uint32 type);
3359*4882a593Smuzhiyun void dhd_ring_deinit(dhd_pub_t *dhdp, void *_ring);
3360*4882a593Smuzhiyun void *dhd_ring_get_first(void *_ring);
3361*4882a593Smuzhiyun void dhd_ring_free_first(void *_ring);
3362*4882a593Smuzhiyun void dhd_ring_set_read_idx(void *_ring, uint32 read_idx);
3363*4882a593Smuzhiyun void dhd_ring_set_write_idx(void *_ring, uint32 write_idx);
3364*4882a593Smuzhiyun uint32 dhd_ring_get_read_idx(void *_ring);
3365*4882a593Smuzhiyun uint32 dhd_ring_get_write_idx(void *_ring);
3366*4882a593Smuzhiyun void *dhd_ring_get_last(void *_ring);
3367*4882a593Smuzhiyun void *dhd_ring_get_next(void *_ring, void *cur);
3368*4882a593Smuzhiyun void *dhd_ring_get_prev(void *_ring, void *cur);
3369*4882a593Smuzhiyun void *dhd_ring_get_empty(void *_ring);
3370*4882a593Smuzhiyun int dhd_ring_get_cur_size(void *_ring);
3371*4882a593Smuzhiyun void dhd_ring_lock(void *ring, void *fist_ptr, void *last_ptr);
3372*4882a593Smuzhiyun void dhd_ring_lock_free(void *ring);
3373*4882a593Smuzhiyun void *dhd_ring_lock_get_first(void *_ring);
3374*4882a593Smuzhiyun void *dhd_ring_lock_get_last(void *_ring);
3375*4882a593Smuzhiyun int dhd_ring_lock_get_count(void *_ring);
3376*4882a593Smuzhiyun void dhd_ring_lock_free_first(void *ring);
3377*4882a593Smuzhiyun void dhd_ring_whole_lock(void *ring);
3378*4882a593Smuzhiyun void dhd_ring_whole_unlock(void *ring);
3379*4882a593Smuzhiyun
3380*4882a593Smuzhiyun #define DHD_DUMP_TYPE_NAME_SIZE 32
3381*4882a593Smuzhiyun #define DHD_DUMP_FILE_PATH_SIZE 256
3382*4882a593Smuzhiyun #define DHD_DUMP_FILE_COUNT_MAX 5
3383*4882a593Smuzhiyun #define DHD_DUMP_TYPE_COUNT_MAX 10
3384*4882a593Smuzhiyun
3385*4882a593Smuzhiyun #ifdef DHD_DUMP_MNGR
3386*4882a593Smuzhiyun typedef struct _DFM_elem {
3387*4882a593Smuzhiyun char type_name[DHD_DUMP_TYPE_NAME_SIZE];
3388*4882a593Smuzhiyun char file_path[DHD_DUMP_FILE_COUNT_MAX][DHD_DUMP_FILE_PATH_SIZE];
3389*4882a593Smuzhiyun int file_idx;
3390*4882a593Smuzhiyun } DFM_elem_t;
3391*4882a593Smuzhiyun
3392*4882a593Smuzhiyun typedef struct _dhd_dump_file_manage {
3393*4882a593Smuzhiyun DFM_elem_t elems[DHD_DUMP_TYPE_COUNT_MAX];
3394*4882a593Smuzhiyun } dhd_dump_file_manage_t;
3395*4882a593Smuzhiyun
3396*4882a593Smuzhiyun extern void dhd_dump_file_manage_enqueue(dhd_pub_t *dhd, char *dump_path, char *fname);
3397*4882a593Smuzhiyun #endif /* DHD_DUMP_MNGR */
3398*4882a593Smuzhiyun
3399*4882a593Smuzhiyun #ifdef PKT_FILTER_SUPPORT
3400*4882a593Smuzhiyun extern void dhd_pktfilter_offload_set(dhd_pub_t * dhd, char *arg);
3401*4882a593Smuzhiyun extern void dhd_pktfilter_offload_enable(dhd_pub_t * dhd, char *arg, int enable, int master_mode);
3402*4882a593Smuzhiyun extern void dhd_pktfilter_offload_delete(dhd_pub_t *dhd, int id);
3403*4882a593Smuzhiyun #endif // endif
3404*4882a593Smuzhiyun
3405*4882a593Smuzhiyun #ifdef DHD_DUMP_PCIE_RINGS
3406*4882a593Smuzhiyun extern int dhd_d2h_h2d_ring_dump(dhd_pub_t *dhd, void *file, const void *user_buf,
3407*4882a593Smuzhiyun unsigned long *file_posn, bool file_write);
3408*4882a593Smuzhiyun #endif /* DHD_DUMP_PCIE_RINGS */
3409*4882a593Smuzhiyun
3410*4882a593Smuzhiyun #ifdef EWP_EDL
3411*4882a593Smuzhiyun #define DHD_EDL_RING_SIZE (D2HRING_EDL_MAX_ITEM * D2HRING_EDL_ITEMSIZE)
3412*4882a593Smuzhiyun int dhd_event_logtrace_process_edl(dhd_pub_t *dhdp, uint8 *data,
3413*4882a593Smuzhiyun void *evt_decode_data);
3414*4882a593Smuzhiyun int dhd_edl_mem_init(dhd_pub_t *dhd);
3415*4882a593Smuzhiyun void dhd_edl_mem_deinit(dhd_pub_t *dhd);
3416*4882a593Smuzhiyun void dhd_prot_edl_ring_tcm_rd_update(dhd_pub_t *dhd);
3417*4882a593Smuzhiyun #define DHD_EDL_MEM_INIT(dhdp) dhd_edl_mem_init(dhdp)
3418*4882a593Smuzhiyun #define DHD_EDL_MEM_DEINIT(dhdp) dhd_edl_mem_deinit(dhdp)
3419*4882a593Smuzhiyun #define DHD_EDL_RING_TCM_RD_UPDATE(dhdp) \
3420*4882a593Smuzhiyun dhd_prot_edl_ring_tcm_rd_update(dhdp)
3421*4882a593Smuzhiyun #else
3422*4882a593Smuzhiyun #define DHD_EDL_MEM_INIT(dhdp) do { /* noop */ } while (0)
3423*4882a593Smuzhiyun #define DHD_EDL_MEM_DEINIT(dhdp) do { /* noop */ } while (0)
3424*4882a593Smuzhiyun #define DHD_EDL_RING_TCM_RD_UPDATE(dhdp) do { /* noop */ } while (0)
3425*4882a593Smuzhiyun #endif /* EWP_EDL */
3426*4882a593Smuzhiyun
3427*4882a593Smuzhiyun void dhd_schedule_logtrace(void *dhd_info);
3428*4882a593Smuzhiyun int dhd_print_fw_ver_from_file(dhd_pub_t *dhdp, char *fwpath);
3429*4882a593Smuzhiyun
3430*4882a593Smuzhiyun #define HD_PREFIX_SIZE 2 /* hexadecimal prefix size */
3431*4882a593Smuzhiyun #define HD_BYTE_SIZE 2 /* hexadecimal byte size */
3432*4882a593Smuzhiyun
3433*4882a593Smuzhiyun #if defined(DHD_H2D_LOG_TIME_SYNC)
3434*4882a593Smuzhiyun void dhd_h2d_log_time_sync_deferred_wq_schedule(dhd_pub_t *dhdp);
3435*4882a593Smuzhiyun void dhd_h2d_log_time_sync(dhd_pub_t *dhdp);
3436*4882a593Smuzhiyun #endif /* DHD_H2D_LOG_TIME_SYNC */
3437*4882a593Smuzhiyun extern void dhd_cleanup_if(struct net_device *net);
3438*4882a593Smuzhiyun
3439*4882a593Smuzhiyun #ifdef DNGL_AXI_ERROR_LOGGING
3440*4882a593Smuzhiyun extern void dhd_axi_error(dhd_pub_t *dhd);
3441*4882a593Smuzhiyun #ifdef DHD_USE_WQ_FOR_DNGL_AXI_ERROR
3442*4882a593Smuzhiyun extern void dhd_axi_error_dispatch(dhd_pub_t *dhdp);
3443*4882a593Smuzhiyun #endif /* DHD_USE_WQ_FOR_DNGL_AXI_ERROR */
3444*4882a593Smuzhiyun #endif /* DNGL_AXI_ERROR_LOGGING */
3445*4882a593Smuzhiyun
3446*4882a593Smuzhiyun #ifdef DHD_HP2P
3447*4882a593Smuzhiyun extern unsigned long dhd_os_hp2plock(dhd_pub_t *pub);
3448*4882a593Smuzhiyun extern void dhd_os_hp2punlock(dhd_pub_t *pub, unsigned long flags);
3449*4882a593Smuzhiyun #endif /* DHD_HP2P */
3450*4882a593Smuzhiyun extern struct dhd_if * dhd_get_ifp(dhd_pub_t *dhdp, uint32 ifidx);
3451*4882a593Smuzhiyun
3452*4882a593Smuzhiyun #ifdef DHD_STATUS_LOGGING
3453*4882a593Smuzhiyun #include <dhd_statlog.h>
3454*4882a593Smuzhiyun #else
3455*4882a593Smuzhiyun #define ST(x) 0
3456*4882a593Smuzhiyun #define STDIR(x) 0
3457*4882a593Smuzhiyun #define DHD_STATLOG_CTRL(dhdp, stat, ifidx, reason) \
3458*4882a593Smuzhiyun do { /* noop */ } while (0)
3459*4882a593Smuzhiyun #define DHD_STATLOG_DATA(dhdp, stat, ifidx, dir, cond) \
3460*4882a593Smuzhiyun do { BCM_REFERENCE(cond); } while (0)
3461*4882a593Smuzhiyun #define DHD_STATLOG_DATA_RSN(dhdp, stat, ifidx, dir, reason) \
3462*4882a593Smuzhiyun do { /* noop */ } while (0)
3463*4882a593Smuzhiyun #endif /* DHD_STATUS_LOGGING */
3464*4882a593Smuzhiyun
3465*4882a593Smuzhiyun #ifdef CONFIG_SILENT_ROAM
3466*4882a593Smuzhiyun extern int dhd_sroam_set_mon(dhd_pub_t *dhd, bool set);
3467*4882a593Smuzhiyun typedef wlc_sroam_info_v1_t wlc_sroam_info_t;
3468*4882a593Smuzhiyun #endif /* CONFIG_SILENT_ROAM */
3469*4882a593Smuzhiyun
3470*4882a593Smuzhiyun #ifdef SUPPORT_SET_TID
3471*4882a593Smuzhiyun enum dhd_set_tid_mode {
3472*4882a593Smuzhiyun /* Disalbe changing TID */
3473*4882a593Smuzhiyun SET_TID_OFF = 0,
3474*4882a593Smuzhiyun /* Change TID for all UDP frames */
3475*4882a593Smuzhiyun SET_TID_ALL_UDP,
3476*4882a593Smuzhiyun /* Change TID for UDP frames based on UID */
3477*4882a593Smuzhiyun SET_TID_BASED_ON_UID
3478*4882a593Smuzhiyun };
3479*4882a593Smuzhiyun extern void dhd_set_tid_based_on_uid(dhd_pub_t *dhdp, void *pkt);
3480*4882a593Smuzhiyun #endif /* SUPPORT_SET_TID */
3481*4882a593Smuzhiyun
3482*4882a593Smuzhiyun #ifdef DHD_DUMP_FILE_WRITE_FROM_KERNEL
3483*4882a593Smuzhiyun #define FILE_NAME_HAL_TAG ""
3484*4882a593Smuzhiyun #else
3485*4882a593Smuzhiyun #define FILE_NAME_HAL_TAG "_hal" /* The tag name concatenated by HAL */
3486*4882a593Smuzhiyun #endif /* DHD_DUMP_FILE_WRITE_FROM_KERNEL */
3487*4882a593Smuzhiyun
3488*4882a593Smuzhiyun #if defined(DISABLE_HE_ENAB) || defined(CUSTOM_CONTROL_HE_ENAB)
3489*4882a593Smuzhiyun extern int dhd_control_he_enab(dhd_pub_t * dhd, uint8 he_enab);
3490*4882a593Smuzhiyun extern uint8 control_he_enab;
3491*4882a593Smuzhiyun #endif /* DISABLE_HE_ENAB || CUSTOM_CONTROL_HE_ENAB */
3492*4882a593Smuzhiyun
3493*4882a593Smuzhiyun #if defined(BCMSDIO)
3494*4882a593Smuzhiyun void dhd_set_role(dhd_pub_t *dhdp, int role, int bssidx);
3495*4882a593Smuzhiyun #endif /* BCMSDIO */
3496*4882a593Smuzhiyun #endif /* _dhd_h_ */
3497