1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Rockchip PCIe Apis For WIFI
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2022, Rockchip Electronics Co., Ltd.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #ifndef __RK_DHD_PCIE_LINUX_H__
9*4882a593Smuzhiyun #define __RK_DHD_PCIE_LINUX_H__
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <typedefs.h>
12*4882a593Smuzhiyun #include <sbchipc.h>
13*4882a593Smuzhiyun #include <pcie_core.h>
14*4882a593Smuzhiyun #include <dhd_pcie.h>
15*4882a593Smuzhiyun #include <linux/aspm_ext.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun static inline void
rk_dhd_bus_l1ss_enable_rc_ep(dhd_bus_t * bus,bool enable)18*4882a593Smuzhiyun rk_dhd_bus_l1ss_enable_rc_ep(dhd_bus_t *bus, bool enable)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun if (!bus->rc_ep_aspm_cap || !bus->rc_ep_l1ss_cap) {
21*4882a593Smuzhiyun pr_err("%s: NOT L1SS CAPABLE rc_ep_aspm_cap: %d rc_ep_l1ss_cap: %d\n",
22*4882a593Smuzhiyun __func__, bus->rc_ep_aspm_cap, bus->rc_ep_l1ss_cap);
23*4882a593Smuzhiyun return;
24*4882a593Smuzhiyun }
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* Disable ASPM of RC and EP */
27*4882a593Smuzhiyun pcie_aspm_ext_l1ss_enable(bus->dev, bus->rc_dev, enable);
28*4882a593Smuzhiyun }
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun static inline bool
rk_dhd_bus_is_rc_ep_l1ss_capable(dhd_bus_t * bus)31*4882a593Smuzhiyun rk_dhd_bus_is_rc_ep_l1ss_capable(dhd_bus_t *bus)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun return pcie_aspm_ext_is_rc_ep_l1ss_capable(bus->dev, bus->rc_dev);
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #endif /* __RK_DHD_PCIE_LINUX_H__ */
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