1 /* 2 * Misc utility routines for accessing the SOC Interconnects 3 * of Broadcom HNBU chips. 4 * 5 * Copyright (C) 2020, Broadcom. 6 * 7 * Unless you and Broadcom execute a separate written software license 8 * agreement governing use of this software, this software is licensed to you 9 * under the terms of the GNU General Public License version 2 (the "GPL"), 10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 11 * following added to such license: 12 * 13 * As a special exception, the copyright holders of this software give you 14 * permission to link this software with independent modules, and to copy and 15 * distribute the resulting executable under terms of your choice, provided that 16 * you also meet, for each linked independent module, the terms and conditions of 17 * the license of that module. An independent module is a module which is not 18 * derived from this software. The special exception does not apply to any 19 * modifications of the software. 20 * 21 * 22 * <<Broadcom-WL-IPTag/Dual:>> 23 */ 24 25 #ifndef _siutils_h_ 26 #define _siutils_h_ 27 28 #include <osl_decl.h> 29 30 /* Make the d11 core(s) selectable by the user config... */ 31 #ifndef D11_CORE_UNIT_MASK 32 /* By default we allow all d11 cores to be used */ 33 #define D11_CORE_UNIT_MASK 0xFFFFFFFFu 34 #endif 35 36 /* Generic interrupt bit mask definitions */ 37 enum bcm_int_reg_idx { 38 BCM_INT_REG_IDX_0 = 0, 39 BCM_INT_REG_IDX_1 = 1, 40 /* temp work around to avoid > 50K invalidation on 4388a0-roml */ 41 #ifndef ROM_COMPAT_INT_REG_IDX 42 BCM_INT_REG_IDX_2 = 2, 43 #endif /* ROM_COMPAT_INT_REG_IDX */ 44 BCM_INT_REGS_NUM 45 }; 46 47 typedef struct bcm_int_bitmask { 48 uint32 bits[BCM_INT_REGS_NUM]; 49 } bcm_int_bitmask_t; 50 51 #ifndef ROM_COMPAT_INT_REG_IDX 52 53 #define BCM_INT_BITMASK_IS_EQUAL(b, cmp) (\ 54 (b)->bits[BCM_INT_REG_IDX_0] == (cmp)->bits[BCM_INT_REG_IDX_0] && \ 55 (b)->bits[BCM_INT_REG_IDX_1] == (cmp)->bits[BCM_INT_REG_IDX_1] && \ 56 (b)->bits[BCM_INT_REG_IDX_2] == (cmp)->bits[BCM_INT_REG_IDX_2]) 57 58 #define BCM_INT_BITMASK_IS_ZERO(b) (\ 59 (b)->bits[BCM_INT_REG_IDX_0] == 0 && \ 60 (b)->bits[BCM_INT_REG_IDX_1] == 0 && \ 61 (b)->bits[BCM_INT_REG_IDX_2] == 0) 62 63 #define BCM_INT_BITMASK_SET(to, from) do { \ 64 (to)->bits[BCM_INT_REG_IDX_0] = (from)->bits[BCM_INT_REG_IDX_0]; \ 65 (to)->bits[BCM_INT_REG_IDX_1] = (from)->bits[BCM_INT_REG_IDX_1]; \ 66 (to)->bits[BCM_INT_REG_IDX_2] = (from)->bits[BCM_INT_REG_IDX_2]; \ 67 } while (0) 68 #define BCM_INT_BITMASK_OR(to, from) do { \ 69 (to)->bits[BCM_INT_REG_IDX_0] |= (from)->bits[BCM_INT_REG_IDX_0]; \ 70 (to)->bits[BCM_INT_REG_IDX_1] |= (from)->bits[BCM_INT_REG_IDX_1]; \ 71 (to)->bits[BCM_INT_REG_IDX_2] |= (from)->bits[BCM_INT_REG_IDX_2]; \ 72 } while (0) 73 74 #define BCM_INT_BITMASK_AND(to, mask) do { \ 75 (to)->bits[BCM_INT_REG_IDX_0] &= (mask)->bits[BCM_INT_REG_IDX_0]; \ 76 (to)->bits[BCM_INT_REG_IDX_1] &= (mask)->bits[BCM_INT_REG_IDX_1]; \ 77 (to)->bits[BCM_INT_REG_IDX_2] &= (mask)->bits[BCM_INT_REG_IDX_2]; \ 78 } while (0) 79 80 #else 81 82 #define BCM_INT_BITMASK_IS_EQUAL(b, cmp) (\ 83 (b)->bits[BCM_INT_REG_IDX_0] == (cmp)->bits[BCM_INT_REG_IDX_0] && \ 84 (b)->bits[BCM_INT_REG_IDX_1] == (cmp)->bits[BCM_INT_REG_IDX_1]) \ 85 86 #define BCM_INT_BITMASK_IS_ZERO(b) (\ 87 (b)->bits[BCM_INT_REG_IDX_0] == 0 && \ 88 (b)->bits[BCM_INT_REG_IDX_1] == 0) 89 90 #define BCM_INT_BITMASK_SET(to, from) do { \ 91 (to)->bits[BCM_INT_REG_IDX_0] = (from)->bits[BCM_INT_REG_IDX_0]; \ 92 (to)->bits[BCM_INT_REG_IDX_1] = (from)->bits[BCM_INT_REG_IDX_1]; \ 93 } while (0) 94 95 #define BCM_INT_BITMASK_OR(to, from) do { \ 96 (to)->bits[BCM_INT_REG_IDX_0] |= (from)->bits[BCM_INT_REG_IDX_0]; \ 97 (to)->bits[BCM_INT_REG_IDX_1] |= (from)->bits[BCM_INT_REG_IDX_1]; \ 98 } while (0) 99 100 #define BCM_INT_BITMASK_AND(to, mask) do { \ 101 (to)->bits[BCM_INT_REG_IDX_0] &= (mask)->bits[BCM_INT_REG_IDX_0]; \ 102 (to)->bits[BCM_INT_REG_IDX_1] &= (mask)->bits[BCM_INT_REG_IDX_1]; \ 103 } while (0) 104 105 #endif /* ROM_COMPAT_INT_REG_IDX */ 106 107 #define WARM_BOOT 0xA0B0C0D0 108 109 typedef struct si_axi_error_info si_axi_error_info_t; 110 111 #ifdef AXI_TIMEOUTS_NIC 112 #define SI_MAX_ERRLOG_SIZE 4 113 typedef struct si_axi_error 114 { 115 uint32 error; 116 uint32 coreid; 117 uint32 errlog_lo; 118 uint32 errlog_hi; 119 uint32 errlog_id; 120 uint32 errlog_flags; 121 uint32 errlog_status; 122 } si_axi_error_t; 123 124 struct si_axi_error_info 125 { 126 uint32 count; 127 si_axi_error_t axi_error[SI_MAX_ERRLOG_SIZE]; 128 }; 129 #endif /* AXI_TIMEOUTS_NIC */ 130 131 /** 132 * Data structure to export all chip specific common variables 133 * public (read-only) portion of siutils handle returned by si_attach()/si_kattach() 134 */ 135 struct si_pub { 136 bool issim; /**< chip is in simulation or emulation */ 137 138 uint16 socitype; /**< SOCI_SB, SOCI_AI */ 139 int16 socirev; /**< SOC interconnect rev */ 140 141 uint16 bustype; /**< SI_BUS, PCI_BUS */ 142 uint16 buscoretype; /**< PCI_CORE_ID, PCIE_CORE_ID */ 143 int16 buscorerev; /**< buscore rev */ 144 uint16 buscoreidx; /**< buscore index */ 145 146 int16 ccrev; /**< chip common core rev */ 147 uint32 cccaps; /**< chip common capabilities */ 148 uint32 cccaps_ext; /**< chip common capabilities extension */ 149 int16 pmurev; /**< pmu core rev */ 150 uint32 pmucaps; /**< pmu capabilities */ 151 152 uint32 boardtype; /**< board type */ 153 uint32 boardrev; /* board rev */ 154 uint32 boardvendor; /**< board vendor */ 155 uint32 boardflags; /**< board flags */ 156 uint32 boardflags2; /**< board flags2 */ 157 uint32 boardflags4; /**< board flags4 */ 158 159 uint32 chip; /**< chip number */ 160 uint16 chiprev; /**< chip revision */ 161 uint16 chippkg; /**< chip package option */ 162 uint32 chipst; /**< chip status */ 163 164 int16 gcirev; /**< gci core rev */ 165 int16 lhlrev; /**< gci core rev */ 166 167 uint32 lpflags; /**< low power flags */ 168 uint32 enum_base; /**< backplane address where the chipcommon core resides */ 169 bool _multibp_enable; 170 bool rffe_debug_mode; 171 bool rffe_elnabyp_mode; 172 173 si_axi_error_info_t * err_info; 174 }; 175 176 /* for HIGH_ONLY driver, the si_t must be writable to allow states sync from BMAC to HIGH driver 177 * for monolithic driver, it is readonly to prevent accident change 178 */ 179 typedef struct si_pub si_t; 180 181 /* 182 * Many of the routines below take an 'sih' handle as their first arg. 183 * Allocate this by calling si_attach(). Free it by calling si_detach(). 184 * At any one time, the sih is logically focused on one particular si core 185 * (the "current core"). 186 * Use si_setcore() or si_setcoreidx() to change the association to another core. 187 */ 188 #define SI_OSH NULL /**< Use for si_kattach when no osh is available */ 189 190 #ifndef SOCI_NCI_BUS 191 #define BADIDX (SI_MAXCORES + 1) 192 #else 193 #define BADIDX (0xffffu) /* MAXCORES will be dynamically calculated for NCI. */ 194 #endif /* SOCI_NCI_BUS */ 195 196 /* clkctl xtal what flags */ 197 #define XTAL 0x1 /**< primary crystal oscillator (2050) */ 198 #define PLL 0x2 /**< main chip pll */ 199 200 /* clkctl clk mode */ 201 #define CLK_FAST 0 /**< force fast (pll) clock */ 202 #define CLK_DYNAMIC 2 /**< enable dynamic clock control */ 203 204 /* GPIO usage priorities */ 205 #define GPIO_DRV_PRIORITY 0 /**< Driver */ 206 #define GPIO_APP_PRIORITY 1 /**< Application */ 207 #define GPIO_HI_PRIORITY 2 /**< Highest priority. Ignore GPIO reservation */ 208 209 /* GPIO pull up/down */ 210 #define GPIO_PULLUP 0 211 #define GPIO_PULLDN 1 212 213 /* GPIO event regtype */ 214 #define GPIO_REGEVT 0 /**< GPIO register event */ 215 #define GPIO_REGEVT_INTMSK 1 /**< GPIO register event int mask */ 216 #define GPIO_REGEVT_INTPOL 2 /**< GPIO register event int polarity */ 217 218 /* device path */ 219 #define SI_DEVPATH_BUFSZ 16 /**< min buffer size in bytes */ 220 221 /* SI routine enumeration: to be used by update function with multiple hooks */ 222 #define SI_DOATTACH 1 223 #define SI_PCIDOWN 2 /**< wireless interface is down */ 224 #define SI_PCIUP 3 /**< wireless interface is up */ 225 226 #ifdef SR_DEBUG 227 #define PMU_RES 31 228 #endif /* SR_DEBUG */ 229 230 /* "access" param defines for si_seci_access() below */ 231 #define SECI_ACCESS_STATUSMASK_SET 0 232 #define SECI_ACCESS_INTRS 1 233 #define SECI_ACCESS_UART_CTS 2 234 #define SECI_ACCESS_UART_RTS 3 235 #define SECI_ACCESS_UART_RXEMPTY 4 236 #define SECI_ACCESS_UART_GETC 5 237 #define SECI_ACCESS_UART_TXFULL 6 238 #define SECI_ACCESS_UART_PUTC 7 239 #define SECI_ACCESS_STATUSMASK_GET 8 240 241 #if defined(BCMQT) 242 #define ISSIM_ENAB(sih) TRUE 243 #else /* !defined(BCMQT) */ 244 #define ISSIM_ENAB(sih) FALSE 245 #endif /* defined(BCMQT) */ 246 247 #if defined(ATE_BUILD) 248 #define ATE_BLD_ENAB(sih) TRUE 249 #else 250 #define ATE_BLD_ENAB(sih) FALSE 251 #endif 252 253 #define INVALID_ADDR (0xFFFFFFFFu) 254 255 /* PMU clock/power control */ 256 #if defined(BCMPMUCTL) 257 #define PMUCTL_ENAB(sih) (BCMPMUCTL) 258 #else 259 #define PMUCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PMU) 260 #endif 261 262 #if defined(BCMAOBENAB) 263 #define AOB_ENAB(sih) (BCMAOBENAB) 264 #else 265 #define AOB_ENAB(sih) ((sih)->ccrev >= 35 ? \ 266 ((sih)->cccaps_ext & CC_CAP_EXT_AOB_PRESENT) : 0) 267 #endif /* BCMAOBENAB */ 268 269 /* chipcommon clock/power control (exclusive with PMU's) */ 270 #if defined(BCMPMUCTL) && BCMPMUCTL 271 #define CCCTL_ENAB(sih) (0) 272 #define CCPLL_ENAB(sih) (0) 273 #else 274 #define CCCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PWR_CTL) 275 #define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK) 276 #endif 277 278 typedef void (*gci_gpio_handler_t)(uint32 stat, void *arg); 279 280 typedef void (*wci2_handler_t)(void *ctx, char *buf, int len); 281 282 /* External BT Coex enable mask */ 283 #define CC_BTCOEX_EN_MASK 0x01 284 /* External PA enable mask */ 285 #define GPIO_CTRL_EPA_EN_MASK 0x40 286 /* WL/BT control enable mask */ 287 #define GPIO_CTRL_5_6_EN_MASK 0x60 288 #define GPIO_CTRL_7_6_EN_MASK 0xC0 289 #define GPIO_OUT_7_EN_MASK 0x80 290 291 #define UCODE_WAKE_STATUS_BIT 1 292 293 #if defined(BCMDONGLEHOST) 294 295 /* CR4 specific defines used by the host driver */ 296 #define SI_CR4_CAP (0x04) 297 #define SI_CR4_BANKIDX (0x40) 298 #define SI_CR4_BANKINFO (0x44) 299 #define SI_CR4_BANKPDA (0x4C) 300 301 #define ARMCR4_TCBBNB_MASK 0xf0 302 #define ARMCR4_TCBBNB_SHIFT 4 303 #define ARMCR4_TCBANB_MASK 0xf 304 #define ARMCR4_TCBANB_SHIFT 0 305 306 #define SICF_CPUHALT (0x0020) 307 #define ARMCR4_BSZ_MASK 0x7f 308 #define ARMCR4_BUNITSZ_MASK 0x200 309 #define ARMCR4_BSZ_8K 8192 310 #define ARMCR4_BSZ_1K 1024 311 #endif /* BCMDONGLEHOST */ 312 #define SI_BPIND_1BYTE 0x1 313 #define SI_BPIND_2BYTE 0x3 314 #define SI_BPIND_4BYTE 0xF 315 316 #define GET_GCI_OFFSET(sih, gci_reg) \ 317 (AOB_ENAB(sih)? OFFSETOF(gciregs_t, gci_reg) : OFFSETOF(chipcregs_t, gci_reg)) 318 319 #define GET_GCI_CORE(sih) \ 320 (AOB_ENAB(sih)? si_findcoreidx(sih, GCI_CORE_ID, 0) : SI_CC_IDX) 321 322 #define VARBUF_PRIO_INVALID 0u 323 #define VARBUF_PRIO_NVRAM 1u 324 #define VARBUF_PRIO_SROM 2u 325 #define VARBUF_PRIO_OTP 3u 326 #define VARBUF_PRIO_SH_SFLASH 4u 327 328 #define BT_IN_RESET_BIT_SHIFT 19u 329 #define BT_IN_PDS_BIT_SHIFT 10u 330 331 /* === exported functions === */ 332 extern si_t *si_attach(uint pcidev, osl_t *osh, volatile void *regs, uint bustype, 333 void *sdh, char **vars, uint *varsz); 334 extern si_t *si_kattach(osl_t *osh); 335 extern void si_detach(si_t *sih); 336 extern volatile void *si_d11_switch_addrbase(si_t *sih, uint coreunit); 337 extern uint si_corelist(const si_t *sih, uint coreid[]); 338 extern uint si_coreid(const si_t *sih); 339 extern uint si_flag(si_t *sih); 340 extern uint si_flag_alt(const si_t *sih); 341 extern uint si_intflag(si_t *sih); 342 extern uint si_coreidx(const si_t *sih); 343 extern uint si_get_num_cores(const si_t *sih); 344 extern uint si_coreunit(const si_t *sih); 345 extern uint si_corevendor(const si_t *sih); 346 extern uint si_corerev(const si_t *sih); 347 extern uint si_corerev_minor(const si_t *sih); 348 extern void *si_osh(si_t *sih); 349 extern void si_setosh(si_t *sih, osl_t *osh); 350 extern int si_backplane_access(si_t *sih, uint addr, uint size, uint *val, bool read); 351 352 /* precommit failed when this is removed */ 353 /* BLAZAR_BRANCH_101_10_DHD_002/build/dhd/linux-fc30/brix-brcm */ 354 /* TBD: Revisit later */ 355 #ifdef BCMINTERNAL 356 extern int si_backplane_access_64(si_t *sih, uint addr, uint size, 357 uint64 *val, bool read); 358 #endif /* BCMINTERNAL */ 359 360 extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val); 361 extern uint si_corereg_writeonly(si_t *sih, uint coreidx, uint regoff, uint mask, uint val); 362 extern uint si_pmu_corereg(si_t *sih, uint32 idx, uint regoff, uint mask, uint val); 363 extern volatile uint32 *si_corereg_addr(si_t *sih, uint coreidx, uint regoff); 364 extern volatile void *si_coreregs(const si_t *sih); 365 extern uint si_wrapperreg(const si_t *sih, uint32 offset, uint32 mask, uint32 val); 366 extern uint si_core_wrapperreg(si_t *sih, uint32 coreidx, uint32 offset, uint32 mask, uint32 val); 367 extern void *si_wrapperregs(const si_t *sih); 368 extern uint32 si_core_cflags(const si_t *sih, uint32 mask, uint32 val); 369 extern void si_core_cflags_wo(const si_t *sih, uint32 mask, uint32 val); 370 extern uint32 si_core_sflags(const si_t *sih, uint32 mask, uint32 val); 371 extern void si_commit(si_t *sih); 372 extern bool si_iscoreup(const si_t *sih); 373 extern uint si_numcoreunits(const si_t *sih, uint coreid); 374 extern uint si_numd11coreunits(const si_t *sih); 375 extern uint si_findcoreidx(const si_t *sih, uint coreid, uint coreunit); 376 extern uint si_findcoreid(const si_t *sih, uint coreidx); 377 extern volatile void *si_setcoreidx(si_t *sih, uint coreidx); 378 extern volatile void *si_setcore(si_t *sih, uint coreid, uint coreunit); 379 extern uint32 si_oobr_baseaddr(const si_t *sih, bool second); 380 #if !defined(BCMDONGLEHOST) 381 extern uint si_corereg_ifup(si_t *sih, uint core_id, uint regoff, uint mask, uint val); 382 extern void si_lowpwr_opt(si_t *sih); 383 #endif /* !defined(BCMDONGLEHOST */ 384 extern volatile void *si_switch_core(si_t *sih, uint coreid, uint *origidx, 385 bcm_int_bitmask_t *intr_val); 386 extern void si_restore_core(si_t *sih, uint coreid, bcm_int_bitmask_t *intr_val); 387 #ifdef USE_NEW_COREREV_API 388 extern uint si_corerev_ext(si_t *sih, uint coreid, uint coreunit); 389 #else 390 uint si_get_corerev(si_t *sih, uint core_id); 391 #endif 392 extern int si_numaddrspaces(const si_t *sih); 393 extern uint32 si_addrspace(const si_t *sih, uint spidx, uint baidx); 394 extern uint32 si_addrspacesize(const si_t *sih, uint spidx, uint baidx); 395 extern void si_coreaddrspaceX(const si_t *sih, uint asidx, uint32 *addr, uint32 *size); 396 extern int si_corebist(const si_t *sih); 397 extern void si_core_reset(si_t *sih, uint32 bits, uint32 resetbits); 398 extern void si_core_disable(const si_t *sih, uint32 bits); 399 extern uint32 si_clock_rate(uint32 pll_type, uint32 n, uint32 m); 400 extern uint si_chip_hostif(const si_t *sih); 401 extern uint32 si_clock(si_t *sih); 402 extern uint32 si_alp_clock(si_t *sih); /* returns [Hz] units */ 403 extern uint32 si_ilp_clock(si_t *sih); /* returns [Hz] units */ 404 extern void si_pci_setup(si_t *sih, uint coremask); 405 extern int si_pcie_setup(si_t *sih, uint coreidx); 406 extern void si_setint(const si_t *sih, int siflag); 407 extern bool si_backplane64(const si_t *sih); 408 extern void si_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn, 409 void *intrsenabled_fn, void *intr_arg); 410 extern void si_deregister_intr_callback(si_t *sih); 411 extern void si_clkctl_init(si_t *sih); 412 extern uint16 si_clkctl_fast_pwrup_delay(si_t *sih); 413 extern bool si_clkctl_cc(si_t *sih, uint mode); 414 extern int si_clkctl_xtal(si_t *sih, uint what, bool on); 415 extern void si_btcgpiowar(si_t *sih); 416 extern bool si_deviceremoved(const si_t *sih); 417 extern void si_set_device_removed(si_t *sih, bool status); 418 extern uint32 si_sysmem_size(si_t *sih); 419 extern uint32 si_socram_size(si_t *sih); 420 extern uint32 si_socram_srmem_size(si_t *sih); 421 extern void si_socram_set_bankpda(si_t *sih, uint32 bankidx, uint32 bankpda); 422 extern bool si_is_bus_mpu_present(si_t *sih); 423 424 extern void si_watchdog(si_t *sih, uint ticks); 425 extern void si_watchdog_ms(si_t *sih, uint32 ms); 426 extern uint32 si_watchdog_msticks(void); 427 extern volatile void *si_gpiosetcore(si_t *sih); 428 extern uint32 si_gpiocontrol(si_t *sih, uint32 mask, uint32 val, uint8 priority); 429 extern uint32 si_gpioouten(si_t *sih, uint32 mask, uint32 val, uint8 priority); 430 extern uint32 si_gpioout(si_t *sih, uint32 mask, uint32 val, uint8 priority); 431 extern uint32 si_gpioin(si_t *sih); 432 extern uint32 si_gpiointpolarity(si_t *sih, uint32 mask, uint32 val, uint8 priority); 433 extern uint32 si_gpiointmask(si_t *sih, uint32 mask, uint32 val, uint8 priority); 434 extern uint32 si_gpioeventintmask(si_t *sih, uint32 mask, uint32 val, uint8 priority); 435 extern uint32 si_gpioled(si_t *sih, uint32 mask, uint32 val); 436 extern uint32 si_gpioreserve(const si_t *sih, uint32 gpio_num, uint8 priority); 437 extern uint32 si_gpiorelease(const si_t *sih, uint32 gpio_num, uint8 priority); 438 extern uint32 si_gpiopull(si_t *sih, bool updown, uint32 mask, uint32 val); 439 extern uint32 si_gpioevent(si_t *sih, uint regtype, uint32 mask, uint32 val); 440 extern uint32 si_gpio_int_enable(si_t *sih, bool enable); 441 extern void si_gci_uart_init(si_t *sih, osl_t *osh, uint8 seci_mode); 442 extern void si_gci_enable_gpio(si_t *sih, uint8 gpio, uint32 mask, uint32 value); 443 extern uint8 si_gci_host_wake_gpio_init(si_t *sih); 444 extern uint8 si_gci_time_sync_gpio_init(si_t *sih); 445 extern void si_gci_host_wake_gpio_enable(si_t *sih, uint8 gpio, bool state); 446 extern void si_gci_time_sync_gpio_enable(si_t *sih, uint8 gpio, bool state); 447 extern void si_gci_host_wake_gpio_tristate(si_t *sih, uint8 gpio, bool state); 448 extern int si_gpio_enable(si_t *sih, uint32 mask); 449 450 extern void si_invalidate_second_bar0win(si_t *sih); 451 452 extern void si_gci_shif_config_wake_pin(si_t *sih, uint8 gpio_n, 453 uint8 wake_events, bool gci_gpio); 454 extern void si_shif_int_enable(si_t *sih, uint8 gpio_n, uint8 wake_events, bool enable); 455 456 /* GCI interrupt handlers */ 457 extern void si_gci_handler_process(si_t *sih); 458 459 extern void si_enable_gpio_wake(si_t *sih, uint8 *wake_mask, uint8 *cur_status, uint8 gci_gpio, 460 uint32 pmu_cc2_mask, uint32 pmu_cc2_value); 461 462 /* GCI GPIO event handlers */ 463 extern void *si_gci_gpioint_handler_register(si_t *sih, uint8 gpio, uint8 sts, 464 gci_gpio_handler_t cb, void *arg); 465 extern void si_gci_gpioint_handler_unregister(si_t *sih, void* gci_i); 466 467 extern void si_gci_gpio_chipcontrol_ex(si_t *si, uint8 gpoi, uint8 opt); 468 extern uint8 si_gci_gpio_status(si_t *sih, uint8 gci_gpio, uint8 mask, uint8 value); 469 extern void si_gci_config_wake_pin(si_t *sih, uint8 gpio_n, uint8 wake_events, 470 bool gci_gpio); 471 extern void si_gci_free_wake_pin(si_t *sih, uint8 gpio_n); 472 #if !defined(BCMDONGLEHOST) 473 extern uint8 si_gci_gpio_wakemask(si_t *sih, uint8 gpio, uint8 mask, uint8 value); 474 extern uint8 si_gci_gpio_intmask(si_t *sih, uint8 gpio, uint8 mask, uint8 value); 475 #endif /* !defined(BCMDONGLEHOST) */ 476 477 /* Wake-on-wireless-LAN (WOWL) */ 478 extern bool si_pci_pmestat(const si_t *sih); 479 extern void si_pci_pmeclr(const si_t *sih); 480 extern void si_pci_pmeen(const si_t *sih); 481 extern void si_pci_pmestatclr(const si_t *sih); 482 extern uint si_pcie_readreg(void *sih, uint addrtype, uint offset); 483 extern uint si_pcie_writereg(void *sih, uint addrtype, uint offset, uint val); 484 485 #ifdef BCMSDIO 486 extern void si_sdio_init(si_t *sih); 487 #endif 488 489 extern uint16 si_d11_devid(si_t *sih); 490 extern int si_corepciid(si_t *sih, uint func, uint16 *pcivendor, uint16 *pcidevice, 491 uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif, uint8 *pciheader); 492 493 extern uint32 si_seci_access(si_t *sih, uint32 val, int access); 494 extern volatile void* si_seci_init(si_t *sih, uint8 seci_mode); 495 extern void si_seci_clk_force(si_t *sih, bool val); 496 extern bool si_seci_clk_force_status(si_t *sih); 497 498 #if (defined(BCMECICOEX) && !defined(BCMDONGLEHOST)) 499 extern bool si_eci(const si_t *sih); 500 extern int si_eci_init(si_t *sih); 501 extern void si_eci_notify_bt(si_t *sih, uint32 mask, uint32 val, bool interrupt); 502 extern bool si_seci(const si_t *sih); 503 extern void* si_gci_init(si_t *sih); 504 extern void si_seci_down(si_t *sih); 505 extern void si_seci_upd(si_t *sih, bool enable); 506 extern bool si_gci(const si_t *sih); 507 extern bool si_sraon(const si_t *sih); 508 #else 509 #define si_eci(sih) 0 510 #define si_eci_init(sih) 0 511 #define si_eci_notify_bt(sih, type, val) (0) 512 #define si_seci(sih) 0 513 #define si_seci_upd(sih, a) do {} while (0) 514 #define si_gci_init(sih) NULL 515 #define si_seci_down(sih) do {} while (0) 516 #define si_gci(sih) 0 517 #define si_sraon(sih) 0 518 #endif /* BCMECICOEX */ 519 520 /* OTP status */ 521 extern bool si_is_otp_disabled(const si_t *sih); 522 extern bool si_is_otp_powered(si_t *sih); 523 extern void si_otp_power(si_t *sih, bool on, uint32* min_res_mask); 524 525 /* SPROM availability */ 526 extern bool si_is_sprom_available(si_t *sih); 527 #ifdef SI_SPROM_PROBE 528 extern void si_sprom_init(si_t *sih); 529 #endif /* SI_SPROM_PROBE */ 530 531 /* SFlash availability */ 532 bool si_is_sflash_available(const si_t *sih); 533 534 /* OTP/SROM CIS stuff */ 535 extern int si_cis_source(const si_t *sih); 536 #define CIS_DEFAULT 0 537 #define CIS_SROM 1 538 #define CIS_OTP 2 539 540 /* Fab-id information */ 541 #define DEFAULT_FAB 0x0 /**< Original/first fab used for this chip */ 542 #define CSM_FAB7 0x1 /**< CSM Fab7 chip */ 543 #define TSMC_FAB12 0x2 /**< TSMC Fab12/Fab14 chip */ 544 #define SMIC_FAB4 0x3 /**< SMIC Fab4 chip */ 545 546 /* bp_ind_access default timeout */ 547 #define BP_ACCESS_TO (500u * 1000u) 548 549 extern uint16 BCMATTACHFN(si_fabid)(si_t *sih); 550 extern uint16 BCMINITFN(si_chipid)(const si_t *sih); 551 552 /* 553 * Build device path. Path size must be >= SI_DEVPATH_BUFSZ. 554 * The returned path is NULL terminated and has trailing '/'. 555 * Return 0 on success, nonzero otherwise. 556 */ 557 extern int si_devpath(const si_t *sih, char *path, int size); 558 extern int si_devpath_pcie(const si_t *sih, char *path, int size); 559 /* Read variable with prepending the devpath to the name */ 560 extern char *si_getdevpathvar(const si_t *sih, const char *name); 561 extern int si_getdevpathintvar(const si_t *sih, const char *name); 562 extern char *si_coded_devpathvar(const si_t *sih, char *varname, int var_len, const char *name); 563 564 /* === HW PR WARs === */ 565 extern uint8 si_pcieclkreq(const si_t *sih, uint32 mask, uint32 val); 566 extern uint32 si_pcielcreg(const si_t *sih, uint32 mask, uint32 val); 567 extern uint8 si_pcieltrenable(const si_t *sih, uint32 mask, uint32 val); 568 extern uint8 si_pcieobffenable(const si_t *sih, uint32 mask, uint32 val); 569 extern uint32 si_pcieltr_reg(const si_t *sih, uint32 reg, uint32 mask, uint32 val); 570 extern uint32 si_pcieltrspacing_reg(const si_t *sih, uint32 mask, uint32 val); 571 extern uint32 si_pcieltrhysteresiscnt_reg(const si_t *sih, uint32 mask, uint32 val); 572 extern void si_pcie_set_error_injection(const si_t *sih, uint32 mode); 573 extern void si_pcie_set_L1substate(const si_t *sih, uint32 substate); 574 #ifndef BCM_BOOTLOADER 575 extern uint32 si_pcie_get_L1substate(const si_t *sih); 576 #endif /* BCM_BOOTLOADER */ 577 extern void si_pci_down(const si_t *sih); 578 extern void si_pci_up(const si_t *sih); 579 extern void si_pci_sleep(const si_t *sih); 580 extern void si_pcie_war_ovr_update(const si_t *sih, uint8 aspm); 581 extern void si_pcie_power_save_enable(const si_t *sih, bool enable); 582 extern int si_pci_fixcfg(si_t *sih); 583 extern bool si_is_warmboot(void); 584 585 extern void si_chipcontrl_restore(si_t *sih, uint32 val); 586 extern uint32 si_chipcontrl_read(si_t *sih); 587 extern void si_chipcontrl_srom4360(si_t *sih, bool on); 588 extern void si_srom_clk_set(si_t *sih); /**< for chips with fast BP clock */ 589 extern void si_btc_enable_chipcontrol(si_t *sih); 590 extern void si_pmu_avb_clk_set(si_t *sih, osl_t *osh, bool set_flag); 591 /* === debug routines === */ 592 593 extern bool si_taclear(si_t *sih, bool details); 594 595 #ifdef BCMDBG 596 extern void si_view(si_t *sih, bool verbose); 597 extern void si_viewall(si_t *sih, bool verbose); 598 #endif /* BCMDBG */ 599 #if defined(BCMDBG) || defined(BCMDBG_DUMP) || defined(BCMDBG_PHYDUMP) || \ 600 defined(WLTEST) 601 struct bcmstrbuf; 602 extern int si_dump_pcieinfo(const si_t *sih, struct bcmstrbuf *b); 603 extern void si_dump_pmuregs(si_t *sih, struct bcmstrbuf *b); 604 extern int si_dump_pcieregs(const si_t *sih, struct bcmstrbuf *b); 605 #endif /* BCMDBG || BCMDBG_DUMP || WLTEST */ 606 607 #if defined(BCMDBG) || defined(BCMDBG_DUMP) || defined(BCMDBG_PHYDUMP) 608 extern void si_dump(const si_t *sih, struct bcmstrbuf *b); 609 extern void si_ccreg_dump(si_t *sih, struct bcmstrbuf *b); 610 extern void si_clkctl_dump(si_t *sih, struct bcmstrbuf *b); 611 extern int si_gpiodump(si_t *sih, struct bcmstrbuf *b); 612 613 extern void si_dumpregs(si_t *sih, struct bcmstrbuf *b); 614 #endif /* BCMDBG || BCMDBG_DUMP || BCMDBG_PHYDUMP */ 615 616 extern uint32 si_ccreg(si_t *sih, uint32 offset, uint32 mask, uint32 val); 617 extern uint32 si_pciereg(const si_t *sih, uint32 offset, uint32 mask, uint32 val, uint type); 618 extern int si_bpind_access(si_t *sih, uint32 addr_high, uint32 addr_low, 619 int32* data, bool read, uint32 us_timeout); 620 extern void sih_write_sraon(si_t *sih, int offset, int len, const uint32* data); 621 #ifdef SR_DEBUG 622 extern void si_dump_pmu(si_t *sih, void *pmu_var); 623 extern void si_pmu_keep_on(const si_t *sih, int32 int_val); 624 extern uint32 si_pmu_keep_on_get(const si_t *sih); 625 extern uint32 si_power_island_set(si_t *sih, uint32 int_val); 626 extern uint32 si_power_island_get(si_t *sih); 627 #endif /* SR_DEBUG */ 628 629 extern uint32 si_pcieserdesreg(const si_t *sih, uint32 mdioslave, uint32 offset, 630 uint32 mask, uint32 val); 631 extern void si_pcie_set_request_size(const si_t *sih, uint16 size); 632 extern uint16 si_pcie_get_request_size(const si_t *sih); 633 extern void si_pcie_set_maxpayload_size(const si_t *sih, uint16 size); 634 extern uint16 si_pcie_get_maxpayload_size(const si_t *sih); 635 extern uint16 si_pcie_get_ssid(const si_t *sih); 636 extern uint32 si_pcie_get_bar0(const si_t *sih); 637 extern int si_pcie_configspace_cache(const si_t *sih); 638 extern int si_pcie_configspace_restore(const si_t *sih); 639 extern int si_pcie_configspace_get(const si_t *sih, uint8 *buf, uint size); 640 641 #ifndef BCMDONGLEHOST 642 extern void si_muxenab(si_t *sih, uint32 w); 643 extern uint32 si_clear_backplane_to(si_t *sih); 644 extern void si_slave_wrapper_add(si_t *sih); 645 646 #ifdef AXI_TIMEOUTS_NIC 647 extern uint32 si_clear_backplane_to_fast(void *sih, void *addr); 648 #endif /* AXI_TIMEOUTS_NIC */ 649 650 #if defined(AXI_TIMEOUTS) || defined(AXI_TIMEOUTS_NIC) 651 extern uint32 si_clear_backplane_to_per_core(si_t *sih, uint coreid, uint coreunit, void *wrap); 652 #endif /* AXI_TIMEOUTS || AXI_TIMEOUTS_NIC */ 653 #endif /* !BCMDONGLEHOST */ 654 655 extern uint32 si_findcoreidx_by_axiid(const si_t *sih, uint32 axiid); 656 extern void si_wrapper_get_last_error(const si_t *sih, uint32 *error_status, uint32 *core, 657 uint32 *lo, uint32 *hi, uint32 *id); 658 extern uint32 si_get_axi_timeout_reg(const si_t *sih); 659 660 #ifdef AXI_TIMEOUTS_NIC 661 extern const si_axi_error_info_t * si_get_axi_errlog_info(const si_t *sih); 662 extern void si_reset_axi_errlog_info(const si_t * sih); 663 #endif /* AXI_TIMEOUTS_NIC */ 664 665 extern void si_update_backplane_timeouts(const si_t *sih, bool enable, uint32 timeout, uint32 cid); 666 667 #if defined(BCMDONGLEHOST) 668 extern uint32 si_tcm_size(si_t *sih); 669 extern bool si_has_flops(si_t *sih); 670 #endif /* BCMDONGLEHOST */ 671 672 extern int si_set_sromctl(si_t *sih, uint32 value); 673 extern uint32 si_get_sromctl(si_t *sih); 674 675 extern uint32 si_gci_direct(si_t *sih, uint offset, uint32 mask, uint32 val); 676 extern uint32 si_gci_indirect(si_t *sih, uint regidx, uint offset, uint32 mask, uint32 val); 677 extern uint32 si_gci_output(si_t *sih, uint reg, uint32 mask, uint32 val); 678 extern uint32 si_gci_input(si_t *sih, uint reg); 679 extern uint32 si_gci_int_enable(si_t *sih, bool enable); 680 extern void si_gci_reset(si_t *sih); 681 #ifdef BCMLTECOEX 682 extern void si_ercx_init(si_t *sih, uint32 ltecx_mux, uint32 ltecx_padnum, 683 uint32 ltecx_fnsel, uint32 ltecx_gcigpio); 684 #endif /* BCMLTECOEX */ 685 #if defined(BCMLTECOEX) && !defined(WLTEST) 686 extern int si_wci2_rxfifo_handler_register(si_t *sih, wci2_handler_t rx_cb, void *ctx); 687 extern void si_wci2_rxfifo_handler_unregister(si_t *sih); 688 #endif /* BCMLTECOEX && !WLTEST */ 689 extern void si_gci_seci_init(si_t *sih); 690 extern void si_wci2_init(si_t *sih, uint8 baudrate, uint32 ltecx_mux, uint32 ltecx_padnum, 691 uint32 ltecx_fnsel, uint32 ltecx_gcigpio, uint32 xtalfreq); 692 693 extern bool si_btcx_wci2_init(si_t *sih); 694 695 extern void si_gci_set_functionsel(si_t *sih, uint32 pin, uint8 fnsel); 696 extern uint32 si_gci_get_functionsel(si_t *sih, uint32 pin); 697 extern void si_gci_clear_functionsel(si_t *sih, uint8 fnsel); 698 extern uint8 si_gci_get_chipctrlreg_idx(uint32 pin, uint32 *regidx, uint32 *pos); 699 extern uint32 si_gci_chipcontrol(si_t *sih, uint reg, uint32 mask, uint32 val); 700 extern uint32 si_gci_chipstatus(si_t *sih, uint reg); 701 extern uint8 si_enable_device_wake(si_t *sih, uint8 *wake_status, uint8 *cur_status); 702 extern uint8 si_get_device_wake_opt(si_t *sih); 703 extern void si_swdenable(si_t *sih, uint32 swdflag); 704 extern uint8 si_enable_perst_wake(si_t *sih, uint8 *perst_wake_mask, uint8 *perst_cur_status); 705 706 extern uint32 si_get_pmu_reg_addr(si_t *sih, uint32 offset); 707 #define CHIPCTRLREG1 0x1 708 #define CHIPCTRLREG2 0x2 709 #define CHIPCTRLREG3 0x3 710 #define CHIPCTRLREG4 0x4 711 #define CHIPCTRLREG5 0x5 712 #define MINRESMASKREG 0x618 713 #define MAXRESMASKREG 0x61c 714 #define CHIPCTRLADDR 0x650 715 #define CHIPCTRLDATA 0x654 716 #define RSRCTABLEADDR 0x620 717 #define RSRCUPDWNTIME 0x628 718 #define PMUREG_RESREQ_MASK 0x68c 719 720 void si_update_masks(si_t *sih); 721 void si_force_islanding(si_t *sih, bool enable); 722 extern uint32 si_pmu_res_req_timer_clr(si_t *sih); 723 extern void si_pmu_rfldo(si_t *sih, bool on); 724 extern void si_pcie_ltr_war(const si_t *sih); 725 extern void si_pcie_hw_LTR_war(const si_t *sih); 726 extern void si_pcie_hw_L1SS_war(const si_t *sih); 727 extern void si_pciedev_crwlpciegen2(const si_t *sih); 728 extern void si_pcie_prep_D3(const si_t *sih, bool enter_D3); 729 extern void si_pciedev_reg_pm_clk_period(const si_t *sih); 730 extern void si_pcie_disable_oobselltr(const si_t *sih); 731 extern uint32 si_raw_reg(const si_t *sih, uint32 reg, uint32 val, uint32 wrire_req); 732 733 /* Macro to enable clock gating changes in different cores */ 734 #define MEM_CLK_GATE_BIT 5 735 #define GCI_CLK_GATE_BIT 18 736 737 #define USBAPP_CLK_BIT 0 738 #define PCIE_CLK_BIT 3 739 #define ARMCR4_DBG_CLK_BIT 4 740 #define SAMPLE_SYNC_CLK_BIT 17 741 #define PCIE_TL_CLK_BIT 18 742 #define HQ_REQ_BIT 24 743 #define PLL_DIV2_BIT_START 9 744 #define PLL_DIV2_MASK (0x37 << PLL_DIV2_BIT_START) 745 #define PLL_DIV2_DIS_OP (0x37 << PLL_DIV2_BIT_START) 746 747 #define pmu_corereg(si, cc_idx, member, mask, val) \ 748 (AOB_ENAB(si) ? \ 749 si_pmu_corereg(si, si_findcoreidx(si, PMU_CORE_ID, 0), \ 750 OFFSETOF(pmuregs_t, member), mask, val): \ 751 si_pmu_corereg(si, cc_idx, OFFSETOF(chipcregs_t, member), mask, val)) 752 753 #define PMU_REG(si, member, mask, val) \ 754 (AOB_ENAB(si) ? \ 755 si_corereg(si, si_findcoreidx(si, PMU_CORE_ID, 0), \ 756 OFFSETOF(pmuregs_t, member), mask, val): \ 757 si_corereg(si, SI_CC_IDX, OFFSETOF(chipcregs_t, member), mask, val)) 758 759 /* Used only for the regs present in the pmu core and not present in the old cc core */ 760 #define PMU_REG_NEW(si, member, mask, val) \ 761 si_corereg(si, si_findcoreidx(si, PMU_CORE_ID, 0), \ 762 OFFSETOF(pmuregs_t, member), mask, val) 763 764 #define GCI_REG(si, offset, mask, val) \ 765 (AOB_ENAB(si) ? \ 766 si_corereg(si, si_findcoreidx(si, GCI_CORE_ID, 0), \ 767 offset, mask, val): \ 768 si_corereg(si, SI_CC_IDX, offset, mask, val)) 769 770 /* Used only for the regs present in the gci core and not present in the old cc core */ 771 #define GCI_REG_NEW(si, member, mask, val) \ 772 si_corereg(si, si_findcoreidx(si, GCI_CORE_ID, 0), \ 773 OFFSETOF(gciregs_t, member), mask, val) 774 775 #define LHL_REG(si, member, mask, val) \ 776 si_corereg(si, si_findcoreidx(si, GCI_CORE_ID, 0), \ 777 OFFSETOF(gciregs_t, member), mask, val) 778 779 #define CHIPC_REG(si, member, mask, val) \ 780 si_corereg(si, SI_CC_IDX, OFFSETOF(chipcregs_t, member), mask, val) 781 782 /* GCI Macros */ 783 #define ALLONES_32 0xFFFFFFFF 784 #define GCI_CCTL_SECIRST_OFFSET 0 /**< SeciReset */ 785 #define GCI_CCTL_RSTSL_OFFSET 1 /**< ResetSeciLogic */ 786 #define GCI_CCTL_SECIEN_OFFSET 2 /**< EnableSeci */ 787 #define GCI_CCTL_FSL_OFFSET 3 /**< ForceSeciOutLow */ 788 #define GCI_CCTL_SMODE_OFFSET 4 /**< SeciOpMode, 6:4 */ 789 #define GCI_CCTL_US_OFFSET 7 /**< UpdateSeci */ 790 #define GCI_CCTL_BRKONSLP_OFFSET 8 /**< BreakOnSleep */ 791 #define GCI_CCTL_SILOWTOUT_OFFSET 9 /**< SeciInLowTimeout, 10:9 */ 792 #define GCI_CCTL_RSTOCC_OFFSET 11 /**< ResetOffChipCoex */ 793 #define GCI_CCTL_ARESEND_OFFSET 12 /**< AutoBTSigResend */ 794 #define GCI_CCTL_FGCR_OFFSET 16 /**< ForceGciClkReq */ 795 #define GCI_CCTL_FHCRO_OFFSET 17 /**< ForceHWClockReqOff */ 796 #define GCI_CCTL_FREGCLK_OFFSET 18 /**< ForceRegClk */ 797 #define GCI_CCTL_FSECICLK_OFFSET 19 /**< ForceSeciClk */ 798 #define GCI_CCTL_FGCA_OFFSET 20 /**< ForceGciClkAvail */ 799 #define GCI_CCTL_FGCAV_OFFSET 21 /**< ForceGciClkAvailValue */ 800 #define GCI_CCTL_SCS_OFFSET 24 /**< SeciClkStretch, 31:24 */ 801 #define GCI_CCTL_SCS 25 /* SeciClkStretch */ 802 803 #define GCI_MODE_UART 0x0 804 #define GCI_MODE_SECI 0x1 805 #define GCI_MODE_BTSIG 0x2 806 #define GCI_MODE_GPIO 0x3 807 #define GCI_MODE_MASK 0x7 808 809 #define GCI_CCTL_LOWTOUT_DIS 0x0 810 #define GCI_CCTL_LOWTOUT_10BIT 0x1 811 #define GCI_CCTL_LOWTOUT_20BIT 0x2 812 #define GCI_CCTL_LOWTOUT_30BIT 0x3 813 #define GCI_CCTL_LOWTOUT_MASK 0x3 814 815 #define GCI_CCTL_SCS_DEF 0x19 816 #define GCI_CCTL_SCS_MASK 0xFF 817 818 #define GCI_SECIIN_MODE_OFFSET 0 819 #define GCI_SECIIN_GCIGPIO_OFFSET 4 820 #define GCI_SECIIN_RXID2IP_OFFSET 8 821 822 #define GCI_SECIIN_MODE_MASK 0x7 823 #define GCI_SECIIN_GCIGPIO_MASK 0xF 824 825 #define GCI_SECIOUT_MODE_OFFSET 0 826 #define GCI_SECIOUT_GCIGPIO_OFFSET 4 827 #define GCI_SECIOUT_LOOPBACK_OFFSET 8 828 #define GCI_SECIOUT_SECIINRELATED_OFFSET 16 829 830 #define GCI_SECIOUT_MODE_MASK 0x7 831 #define GCI_SECIOUT_GCIGPIO_MASK 0xF 832 #define GCI_SECIOUT_SECIINRELATED_MASK 0x1 833 834 #define GCI_SECIOUT_SECIINRELATED 0x1 835 836 #define GCI_SECIAUX_RXENABLE_OFFSET 0 837 #define GCI_SECIFIFO_RXENABLE_OFFSET 16 838 839 #define GCI_SECITX_ENABLE_OFFSET 0 840 841 #define GCI_GPIOCTL_INEN_OFFSET 0 842 #define GCI_GPIOCTL_OUTEN_OFFSET 1 843 #define GCI_GPIOCTL_PDN_OFFSET 4 844 845 #define GCI_GPIOIDX_OFFSET 16 846 847 #define GCI_LTECX_SECI_ID 0 /**< SECI port for LTECX */ 848 #define GCI_LTECX_TXCONF_EN_OFFSET 2 849 #define GCI_LTECX_PRISEL_EN_OFFSET 3 850 851 /* To access per GCI bit registers */ 852 #define GCI_REG_WIDTH 32 853 854 /* number of event summary bits */ 855 #define GCI_EVENT_NUM_BITS 32 856 857 /* gci event bits per core */ 858 #define GCI_EVENT_BITS_PER_CORE 4 859 #define GCI_EVENT_HWBIT_1 1 860 #define GCI_EVENT_HWBIT_2 2 861 #define GCI_EVENT_SWBIT_1 3 862 #define GCI_EVENT_SWBIT_2 4 863 864 #define GCI_MBDATA_TOWLAN_POS 96 865 #define GCI_MBACK_TOWLAN_POS 104 866 #define GCI_WAKE_TOWLAN_PO 112 867 #define GCI_SWREADY_POS 120 868 869 /* GCI bit positions */ 870 /* GCI [127:000] = WLAN [127:0] */ 871 #define GCI_WLAN_IP_ID 0 872 #define GCI_WLAN_BEGIN 0 873 #define GCI_WLAN_PRIO_POS (GCI_WLAN_BEGIN + 4) 874 #define GCI_WLAN_PERST_POS (GCI_WLAN_BEGIN + 15) 875 876 /* GCI [255:128] = BT [127:0] */ 877 #define GCI_BT_IP_ID 1 878 #define GCI_BT_BEGIN 128 879 #define GCI_BT_MBDATA_TOWLAN_POS (GCI_BT_BEGIN + GCI_MBDATA_TOWLAN_POS) 880 #define GCI_BT_MBACK_TOWLAN_POS (GCI_BT_BEGIN + GCI_MBACK_TOWLAN_POS) 881 #define GCI_BT_WAKE_TOWLAN_POS (GCI_BT_BEGIN + GCI_WAKE_TOWLAN_PO) 882 #define GCI_BT_SWREADY_POS (GCI_BT_BEGIN + GCI_SWREADY_POS) 883 884 /* GCI [639:512] = LTE [127:0] */ 885 #define GCI_LTE_IP_ID 4 886 #define GCI_LTE_BEGIN 512 887 #define GCI_LTE_FRAMESYNC_POS (GCI_LTE_BEGIN + 0) 888 #define GCI_LTE_RX_POS (GCI_LTE_BEGIN + 1) 889 #define GCI_LTE_TX_POS (GCI_LTE_BEGIN + 2) 890 #define GCI_LTE_WCI2TYPE_POS (GCI_LTE_BEGIN + 48) 891 #define GCI_LTE_WCI2TYPE_MASK 7 892 #define GCI_LTE_AUXRXDVALID_POS (GCI_LTE_BEGIN + 56) 893 894 /* Reg Index corresponding to ECI bit no x of ECI space */ 895 #define GCI_REGIDX(x) ((x)/GCI_REG_WIDTH) 896 /* Bit offset of ECI bit no x in 32-bit words */ 897 #define GCI_BITOFFSET(x) ((x)%GCI_REG_WIDTH) 898 899 #define GCI_ECI_HW0(ip_id) (((ip_id) * GCI_EVENT_BITS_PER_CORE) + 0) 900 #define GCI_ECI_HW1(ip_id) (((ip_id) * GCI_EVENT_BITS_PER_CORE) + 1) 901 #define GCI_ECI_SW0(ip_id) (((ip_id) * GCI_EVENT_BITS_PER_CORE) + 2) 902 #define GCI_ECI_SW1(ip_id) (((ip_id) * GCI_EVENT_BITS_PER_CORE) + 3) 903 904 /* BT SMEM Control Register 0 */ 905 #define GCI_BT_SMEM_CTRL0_SUBCORE_ENABLE_PKILL (1 << 28) 906 907 /* GCI RXFIFO Common control */ 908 #define GCI_RXFIFO_CTRL_AUX_EN 0xFF 909 #define GCI_RXFIFO_CTRL_FIFO_EN 0xFF00 910 #define GCI_RXFIFO_CTRL_FIFO_TYPE2_EN 0x400 911 912 /* End - GCI Macros */ 913 914 extern void si_pll_sr_reinit(si_t *sih); 915 extern void si_pll_closeloop(si_t *sih); 916 extern uint si_num_slaveports(const si_t *sih, uint coreid); 917 extern uint32 si_get_slaveport_addr(si_t *sih, uint spidx, uint baidx, 918 uint core_id, uint coreunit); 919 extern uint32 si_get_d11_slaveport_addr(si_t *sih, uint spidx, 920 uint baidx, uint coreunit); 921 void si_introff(const si_t *sih, bcm_int_bitmask_t *intr_val); 922 void si_intrrestore(const si_t *sih, bcm_int_bitmask_t *intr_val); 923 bool si_get_nvram_rfldo3p3_war(const si_t *sih); 924 void si_nvram_res_masks(const si_t *sih, uint32 *min_mask, uint32 *max_mask); 925 extern uint32 si_xtalfreq(const si_t *sih); 926 extern uint8 si_getspurmode(const si_t *sih); 927 extern uint32 si_get_openloop_dco_code(const si_t *sih); 928 extern void si_set_openloop_dco_code(si_t *sih, uint32 openloop_dco_code); 929 extern uint32 si_wrapper_dump_buf_size(const si_t *sih); 930 extern uint32 si_wrapper_dump_binary(const si_t *sih, uchar *p); 931 extern uint32 si_wrapper_dump_last_timeout(const si_t *sih, uint32 *error, uint32 *core, 932 uint32 *ba, uchar *p); 933 934 /* SR Power Control */ 935 extern uint32 si_srpwr_request(const si_t *sih, uint32 mask, uint32 val); 936 extern uint32 si_srpwr_request_on_rev80(si_t *sih, uint32 mask, uint32 val, 937 uint32 ucode_awake); 938 extern uint32 si_srpwr_stat_spinwait(const si_t *sih, uint32 mask, uint32 val); 939 extern uint32 si_srpwr_stat(si_t *sih); 940 extern uint32 si_srpwr_domain(si_t *sih); 941 extern uint32 si_srpwr_domain_all_mask(const si_t *sih); 942 extern uint8 si_srpwr_domain_wl(si_t *sih); 943 extern uint32 si_srpwr_bt_status(si_t *sih); 944 /* SR Power Control */ 945 bool si_srpwr_cap(si_t *sih); 946 #define SRPWR_CAP(sih) (si_srpwr_cap(sih)) 947 948 #ifdef BCMSRPWR 949 extern bool _bcmsrpwr; 950 #if defined(ROM_ENAB_RUNTIME_CHECK) || !defined(DONGLEBUILD) 951 #define SRPWR_ENAB() (_bcmsrpwr) 952 #elif defined(BCMSRPWR_DISABLED) 953 #define SRPWR_ENAB() (0) 954 #else 955 #define SRPWR_ENAB() (1) 956 #endif 957 #else 958 #define SRPWR_ENAB() (0) 959 #endif /* BCMSRPWR */ 960 961 /* 962 * Multi-BackPlane architecture. Each can power up/down independently. 963 * Common backplane: shared between BT and WL 964 * ChipC, PCIe, GCI, PMU, SRs 965 * HW powers up as needed 966 * WL BackPlane (WLBP): 967 * ARM, TCM, Main, Aux 968 * Host needs to power up 969 */ 970 #define MULTIBP_CAP(sih) (BCM4378_CHIP(sih->chip) || \ 971 BCM4387_CHIP(sih->chip) || BCM4388_CHIP(sih->chip) || \ 972 BCM4389_CHIP(sih->chip) || BCM4385_CHIP(sih->chip) || \ 973 BCM4376_CHIP(sih->chip) || BCM4397_CHIP(sih->chip)) 974 #define MULTIBP_ENAB(sih) ((sih) && (sih)->_multibp_enable) 975 976 #ifdef DONGLEBUILD 977 extern bool si_check_enable_backplane_log(const si_t *sih); 978 #endif /* DONGLEBUILD */ 979 980 uint32 si_enum_base(uint devid); 981 982 /* Default ARM PLL freq 4369/4368 */ 983 #define ARMPLL_FREQ_400MHZ (400u) 984 #define ARMPLL_FREQ_800MHZ (800u) 985 /* ARM PLL freq computed using chip defaults is 1002.8235 Mhz */ 986 #define ARMPLL_FREQ_1000MHZ (1003u) 987 988 extern uint8 si_lhl_ps_mode(const si_t *sih); 989 extern uint32 si_get_armpllclkfreq(const si_t *sih); 990 uint8 si_get_ccidiv(const si_t *sih); 991 extern uint8 si_hib_ext_wakeup_isenab(const si_t *sih); 992 993 #ifdef UART_TRAP_DBG 994 void si_dump_APB_Bridge_registers(const si_t *sih); 995 #endif /* UART_TRAP_DBG */ 996 void si_force_clocks(const si_t *sih, uint clock_state); 997 998 #if defined(BCMSDIODEV_ENABLED) && defined(ATE_BUILD) 999 bool si_chipcap_sdio_ate_only(const si_t *sih); 1000 #endif /* BCMSDIODEV_ENABLED && ATE_BUILD */ 1001 1002 /* indicates to the siutils how the PICe BAR0 is mappend. 1003 * here is the current scheme, which are all using BAR0: 1004 * id enum wrapper 1005 * ==== ========= ========= 1006 * 0 0000-0FFF 1000-1FFF 1007 * 1 4000-4FFF 5000-5FFF 1008 * 2 9000-9FFF A000-AFFF 1009 * >= 3 not supported 1010 */ 1011 void si_set_slice_id(si_t *sih, uint8 slice); 1012 uint8 si_get_slice_id(const si_t *sih); 1013 1014 /* query the d11 core type */ 1015 #define D11_CORE_TYPE_NORM 0u 1016 #define D11_CORE_TYPE_SCAN 1u 1017 uint si_core_d11_type(si_t *sih, uint coreunit); 1018 1019 /* check if the package option allows the d11 core */ 1020 bool si_pkgopt_d11_allowed(si_t *sih, uint coreuint); 1021 1022 /* return if scan core is present */ 1023 bool si_scan_core_present(const si_t *sih); 1024 void si_configure_pwrthrottle_gpio(si_t *sih, uint8 pwrthrottle_gpio_pin); 1025 void si_configure_onbody_gpio(si_t *sih, uint8 onbody_gpio_pin); 1026 1027 /* check if HWA core present */ 1028 bool si_hwa_present(const si_t *sih); 1029 1030 /* check if SYSMEM present */ 1031 bool si_sysmem_present(const si_t *sih); 1032 1033 /* return BT state */ 1034 bool si_btc_bt_status_in_reset(si_t *sih); 1035 bool si_btc_bt_status_in_pds(si_t *sih); 1036 int si_btc_bt_pds_wakeup_force(si_t *sih, bool force); 1037 1038 /* RFFE RFEM Functions */ 1039 #ifndef BCMDONGLEHOST 1040 void si_rffe_rfem_init(si_t *sih); 1041 void si_rffe_set_debug_mode(si_t *sih, bool enable); 1042 bool si_rffe_get_debug_mode(si_t *sih); 1043 int si_rffe_set_elnabyp_mode(si_t *sih, uint8 mode); 1044 int8 si_rffe_get_elnabyp_mode(si_t *sih); 1045 int si_rffe_rfem_read(si_t *sih, uint8 dev_id, uint8 antenna, uint16 reg_addr, uint32 *val); 1046 int si_rffe_rfem_write(si_t *sih, uint8 dev_id, uint8 antenna, uint16 reg_addr, uint32 data); 1047 #endif /* !BCMDONGLEHOST */ 1048 extern void si_jtag_udr_pwrsw_main_toggle(si_t *sih, bool on); 1049 extern int si_pmu_res_state_pwrsw_main_wait(si_t *sih); 1050 extern uint32 si_d11_core_sssr_addr(si_t *sih, uint unit, uint32 *sssr_dmp_sz); 1051 1052 #ifdef USE_LHL_TIMER 1053 /* Get current HIB time API */ 1054 uint32 si_cur_hib_time(si_t *sih); 1055 #endif 1056 1057 #endif /* _siutils_h_ */ 1058