1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Structure used by apps whose drivers access SDIO drivers. 3*4882a593Smuzhiyun * Pulled out separately so dhdu and wlu can both use it. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2020, Broadcom. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Unless you and Broadcom execute a separate written software license 8*4882a593Smuzhiyun * agreement governing use of this software, this software is licensed to you 9*4882a593Smuzhiyun * under the terms of the GNU General Public License version 2 (the "GPL"), 10*4882a593Smuzhiyun * available at http://www.broadcom.com/licenses/GPLv2.php, with the 11*4882a593Smuzhiyun * following added to such license: 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * As a special exception, the copyright holders of this software give you 14*4882a593Smuzhiyun * permission to link this software with independent modules, and to copy and 15*4882a593Smuzhiyun * distribute the resulting executable under terms of your choice, provided that 16*4882a593Smuzhiyun * you also meet, for each linked independent module, the terms and conditions of 17*4882a593Smuzhiyun * the license of that module. An independent module is a module which is not 18*4882a593Smuzhiyun * derived from this software. The special exception does not apply to any 19*4882a593Smuzhiyun * modifications of the software. 20*4882a593Smuzhiyun * 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * <<Broadcom-WL-IPTag/Dual:>> 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #ifndef _sdiovar_h_ 26*4882a593Smuzhiyun #define _sdiovar_h_ 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #include <typedefs.h> 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun typedef struct sdreg { 31*4882a593Smuzhiyun int func; 32*4882a593Smuzhiyun int offset; 33*4882a593Smuzhiyun int value; 34*4882a593Smuzhiyun } sdreg_t; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun typedef struct sdreg_64 { 37*4882a593Smuzhiyun int func; 38*4882a593Smuzhiyun int offset; 39*4882a593Smuzhiyun uint64 value; 40*4882a593Smuzhiyun } sdreg_64_t; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* Common msglevel constants */ 43*4882a593Smuzhiyun #define SDH_ERROR_VAL 0x0001 /* Error */ 44*4882a593Smuzhiyun #define SDH_TRACE_VAL 0x0002 /* Trace */ 45*4882a593Smuzhiyun #define SDH_INFO_VAL 0x0004 /* Info */ 46*4882a593Smuzhiyun #define SDH_DEBUG_VAL 0x0008 /* Debug */ 47*4882a593Smuzhiyun #define SDH_DATA_VAL 0x0010 /* Data */ 48*4882a593Smuzhiyun #define SDH_CTRL_VAL 0x0020 /* Control Regs */ 49*4882a593Smuzhiyun #define SDH_LOG_VAL 0x0040 /* Enable bcmlog */ 50*4882a593Smuzhiyun #define SDH_DMA_VAL 0x0080 /* DMA */ 51*4882a593Smuzhiyun #define SDH_COST_VAL 0x8000 /* Control Regs */ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define NUM_PREV_TRANSACTIONS 16 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #ifdef BCMSPI 56*4882a593Smuzhiyun /* Error statistics for gSPI */ 57*4882a593Smuzhiyun struct spierrstats_t { 58*4882a593Smuzhiyun uint32 dna; /* The requested data is not available. */ 59*4882a593Smuzhiyun uint32 rdunderflow; /* FIFO underflow happened due to current (F2, F3) rd command */ 60*4882a593Smuzhiyun uint32 wroverflow; /* FIFO underflow happened due to current (F1, F2, F3) wr command */ 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun uint32 f2interrupt; /* OR of all F2 related intr status bits. */ 63*4882a593Smuzhiyun uint32 f3interrupt; /* OR of all F3 related intr status bits. */ 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun uint32 f2rxnotready; /* F2 FIFO is not ready to receive data (FIFO empty) */ 66*4882a593Smuzhiyun uint32 f3rxnotready; /* F3 FIFO is not ready to receive data (FIFO empty) */ 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun uint32 hostcmddataerr; /* Error in command or host data, detected by CRC/checksum 69*4882a593Smuzhiyun * (optional) 70*4882a593Smuzhiyun */ 71*4882a593Smuzhiyun uint32 f2pktavailable; /* Packet is available in F2 TX FIFO */ 72*4882a593Smuzhiyun uint32 f3pktavailable; /* Packet is available in F2 TX FIFO */ 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun uint32 dstatus[NUM_PREV_TRANSACTIONS]; /* dstatus bits of last 16 gSPI transactions */ 75*4882a593Smuzhiyun uint32 spicmd[NUM_PREV_TRANSACTIONS]; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun #endif /* BCMSPI */ 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun typedef struct sdio_bus_metrics { 80*4882a593Smuzhiyun uint32 active_dur; /* msecs */ 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* Generic */ 83*4882a593Smuzhiyun uint32 data_intr_cnt; /* data interrupt counter */ 84*4882a593Smuzhiyun uint32 mb_intr_cnt; /* mailbox interrupt counter */ 85*4882a593Smuzhiyun uint32 error_intr_cnt; /* error interrupt counter */ 86*4882a593Smuzhiyun uint32 wakehost_cnt; /* counter for OOB wakehost */ 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* DS forcewake */ 89*4882a593Smuzhiyun uint32 ds_wake_on_cnt; /* counter for (clock) ON */ 90*4882a593Smuzhiyun uint32 ds_wake_on_dur; /* duration for (clock) ON) */ 91*4882a593Smuzhiyun uint32 ds_wake_off_cnt; /* counter for (clock) OFF */ 92*4882a593Smuzhiyun uint32 ds_wake_off_dur; /* duration for (clock) OFF */ 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* DS_D0 state */ 95*4882a593Smuzhiyun uint32 ds_d0_cnt; /* counter for DS_D0 state */ 96*4882a593Smuzhiyun uint32 ds_d0_dur; /* duration for DS_D0 state */ 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* DS_D3 state */ 99*4882a593Smuzhiyun uint32 ds_d3_cnt; /* counter for DS_D3 state */ 100*4882a593Smuzhiyun uint32 ds_d3_dur; /* duration for DS_D3 state */ 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* DS DEV_WAKE */ 103*4882a593Smuzhiyun uint32 ds_dw_assrt_cnt; /* counter for DW_ASSERT */ 104*4882a593Smuzhiyun uint32 ds_dw_dassrt_cnt; /* counter for DW_DASSERT */ 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* DS mailbox signals */ 107*4882a593Smuzhiyun uint32 ds_tx_dsreq_cnt; /* counter for tx HMB_DATA_DSREQ */ 108*4882a593Smuzhiyun uint32 ds_tx_dsexit_cnt; /* counter for tx HMB_DATA_DSEXIT */ 109*4882a593Smuzhiyun uint32 ds_tx_d3ack_cnt; /* counter for tx HMB_DATA_D3ACK */ 110*4882a593Smuzhiyun uint32 ds_tx_d3exit_cnt; /* counter for tx HMB_DATA_D3EXIT */ 111*4882a593Smuzhiyun uint32 ds_rx_dsack_cnt; /* counter for rx SMB_DATA_DSACK */ 112*4882a593Smuzhiyun uint32 ds_rx_dsnack_cnt; /* counter for rx SMB_DATA_DSNACK */ 113*4882a593Smuzhiyun uint32 ds_rx_d3inform_cnt; /* counter for rx SMB_DATA_D3INFORM */ 114*4882a593Smuzhiyun } sdio_bus_metrics_t; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun /* Bus interface info for SDIO */ 117*4882a593Smuzhiyun typedef struct wl_pwr_sdio_stats { 118*4882a593Smuzhiyun uint16 type; /* WL_PWRSTATS_TYPE_SDIO */ 119*4882a593Smuzhiyun uint16 len; /* Up to 4K-1, top 4 bits are reserved */ 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun sdio_bus_metrics_t sdio; /* stats from SDIO bus driver */ 122*4882a593Smuzhiyun } wl_pwr_sdio_stats_t; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #endif /* _sdiovar_h_ */ 125