1 /* 2 * BCM47XX Sonics SiliconBackplane embedded ram core 3 * 4 * Copyright (C) 2020, Broadcom. 5 * 6 * Unless you and Broadcom execute a separate written software license 7 * agreement governing use of this software, this software is licensed to you 8 * under the terms of the GNU General Public License version 2 (the "GPL"), 9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10 * following added to such license: 11 * 12 * As a special exception, the copyright holders of this software give you 13 * permission to link this software with independent modules, and to copy and 14 * distribute the resulting executable under terms of your choice, provided that 15 * you also meet, for each linked independent module, the terms and conditions of 16 * the license of that module. An independent module is a module which is not 17 * derived from this software. The special exception does not apply to any 18 * modifications of the software. 19 * 20 * 21 * <<Broadcom-WL-IPTag/Dual:>> 22 */ 23 24 #ifndef _SBSOCRAM_H 25 #define _SBSOCRAM_H 26 27 #ifndef _LANGUAGE_ASSEMBLY 28 29 /* cpp contortions to concatenate w/arg prescan */ 30 #ifndef PAD 31 #define _PADLINE(line) pad ## line 32 #define _XSTR(line) _PADLINE(line) 33 #define PAD _XSTR(__LINE__) 34 #endif /* PAD */ 35 36 /* Memcsocram core registers */ 37 typedef volatile struct sbsocramregs { 38 uint32 coreinfo; 39 uint32 bwalloc; 40 uint32 extracoreinfo; 41 uint32 biststat; 42 uint32 bankidx; 43 uint32 standbyctrl; 44 45 uint32 errlogstatus; /* rev 6 */ 46 uint32 errlogaddr; /* rev 6 */ 47 /* used for patching rev 3 & 5 */ 48 uint32 cambankidx; 49 uint32 cambankstandbyctrl; 50 uint32 cambankpatchctrl; 51 uint32 cambankpatchtblbaseaddr; 52 uint32 cambankcmdreg; 53 uint32 cambankdatareg; 54 uint32 cambankmaskreg; 55 uint32 PAD[1]; 56 uint32 bankinfo; /* corev 8 */ 57 uint32 bankpda; 58 uint32 PAD[14]; 59 uint32 extmemconfig; 60 uint32 extmemparitycsr; 61 uint32 extmemparityerrdata; 62 uint32 extmemparityerrcnt; 63 uint32 extmemwrctrlandsize; 64 uint32 PAD[84]; 65 uint32 workaround; 66 uint32 pwrctl; /* corerev >= 2 */ 67 uint32 PAD[133]; 68 uint32 sr_control; /* corerev >= 15 */ 69 uint32 sr_status; /* corerev >= 15 */ 70 uint32 sr_address; /* corerev >= 15 */ 71 uint32 sr_data; /* corerev >= 15 */ 72 } sbsocramregs_t; 73 74 #endif /* _LANGUAGE_ASSEMBLY */ 75 76 /* Register offsets */ 77 #define SR_COREINFO 0x00 78 #define SR_BWALLOC 0x04 79 #define SR_BISTSTAT 0x0c 80 #define SR_BANKINDEX 0x10 81 #define SR_BANKSTBYCTL 0x14 82 #define SR_PWRCTL 0x1e8 83 84 /* Coreinfo register */ 85 #define SRCI_PT_MASK 0x00070000 /* corerev >= 6; port type[18:16] */ 86 #define SRCI_PT_SHIFT 16 87 /* port types : SRCI_PT_<processorPT>_<backplanePT> */ 88 #define SRCI_PT_OCP_OCP 0 89 #define SRCI_PT_AXI_OCP 1 90 #define SRCI_PT_ARM7AHB_OCP 2 91 #define SRCI_PT_CM3AHB_OCP 3 92 #define SRCI_PT_AXI_AXI 4 93 #define SRCI_PT_AHB_AXI 5 94 /* corerev >= 3 */ 95 #define SRCI_LSS_MASK 0x00f00000 96 #define SRCI_LSS_SHIFT 20 97 #define SRCI_LRS_MASK 0x0f000000 98 #define SRCI_LRS_SHIFT 24 99 100 /* In corerev 0, the memory size is 2 to the power of the 101 * base plus 16 plus to the contents of the memsize field plus 1. 102 */ 103 #define SRCI_MS0_MASK 0xf 104 #define SR_MS0_BASE 16 105 106 /* 107 * In corerev 1 the bank size is 2 ^ the bank size field plus 14, 108 * the memory size is number of banks times bank size. 109 * The same applies to rom size. 110 */ 111 #define SRCI_ROMNB_MASK 0xf000 112 #define SRCI_ROMNB_SHIFT 12 113 #define SRCI_ROMBSZ_MASK 0xf00 114 #define SRCI_ROMBSZ_SHIFT 8 115 #define SRCI_SRNB_MASK 0xf0 116 #define SRCI_SRNB_SHIFT 4 117 #define SRCI_SRBSZ_MASK 0xf 118 #define SRCI_SRBSZ_SHIFT 0 119 120 #define SRCI_SRNB_MASK_EXT 0x100 121 122 #define SR_BSZ_BASE 14 123 124 /* Standby control register */ 125 #define SRSC_SBYOVR_MASK 0x80000000 126 #define SRSC_SBYOVR_SHIFT 31 127 #define SRSC_SBYOVRVAL_MASK 0x60000000 128 #define SRSC_SBYOVRVAL_SHIFT 29 129 #define SRSC_SBYEN_MASK 0x01000000 /* rev >= 3 */ 130 #define SRSC_SBYEN_SHIFT 24 131 132 /* Power control register */ 133 #define SRPC_PMU_STBYDIS_MASK 0x00000010 /* rev >= 3 */ 134 #define SRPC_PMU_STBYDIS_SHIFT 4 135 #define SRPC_STBYOVRVAL_MASK 0x00000008 136 #define SRPC_STBYOVRVAL_SHIFT 3 137 #define SRPC_STBYOVR_MASK 0x00000007 138 #define SRPC_STBYOVR_SHIFT 0 139 140 /* Extra core capability register */ 141 #define SRECC_NUM_BANKS_MASK 0x000000F0 142 #define SRECC_NUM_BANKS_SHIFT 4 143 #define SRECC_BANKSIZE_MASK 0x0000000F 144 #define SRECC_BANKSIZE_SHIFT 0 145 146 #define SRECC_BANKSIZE(value) (1 << (value)) 147 148 /* CAM bank patch control */ 149 #define SRCBPC_PATCHENABLE 0x80000000 150 151 #define SRP_ADDRESS 0x0001FFFC 152 #define SRP_VALID 0x8000 153 154 /* CAM bank command reg */ 155 #define SRCMD_WRITE 0x00020000 156 #define SRCMD_READ 0x00010000 157 #define SRCMD_DONE 0x80000000 158 159 #define SRCMD_DONE_DLY 1000 160 161 /* bankidx and bankinfo reg defines corerev >= 8 */ 162 #define SOCRAM_BANKINFO_SZMASK 0x7f 163 #define SOCRAM_BANKIDX_ROM_MASK 0x100 164 165 #define SOCRAM_BANKIDX_MEMTYPE_SHIFT 8 166 /* socram bankinfo memtype */ 167 #define SOCRAM_MEMTYPE_RAM 0 168 #define SOCRAM_MEMTYPE_ROM 1 169 #define SOCRAM_MEMTYPE_DEVRAM 2 170 171 #define SOCRAM_BANKINFO_REG 0x40 172 #define SOCRAM_BANKIDX_REG 0x10 173 #define SOCRAM_BANKINFO_STDBY_MASK 0x400 174 #define SOCRAM_BANKINFO_STDBY_TIMER 0x800 175 176 /* bankinfo rev >= 10 */ 177 #define SOCRAM_BANKINFO_DEVRAMSEL_SHIFT 13 178 #define SOCRAM_BANKINFO_DEVRAMSEL_MASK 0x2000 179 #define SOCRAM_BANKINFO_DEVRAMPRO_SHIFT 14 180 #define SOCRAM_BANKINFO_DEVRAMPRO_MASK 0x4000 181 #define SOCRAM_BANKINFO_SLPSUPP_SHIFT 15 182 #define SOCRAM_BANKINFO_SLPSUPP_MASK 0x8000 183 #define SOCRAM_BANKINFO_RETNTRAM_SHIFT 16 184 #define SOCRAM_BANKINFO_RETNTRAM_MASK 0x00010000 185 #define SOCRAM_BANKINFO_PDASZ_SHIFT 17 186 #define SOCRAM_BANKINFO_PDASZ_MASK 0x003E0000 187 #define SOCRAM_BANKINFO_DEVRAMREMAP_SHIFT 24 188 #define SOCRAM_BANKINFO_DEVRAMREMAP_MASK 0x01000000 189 190 /* extracoreinfo register */ 191 #define SOCRAM_DEVRAMBANK_MASK 0xF000 192 #define SOCRAM_DEVRAMBANK_SHIFT 12 193 194 /* bank info to calculate bank size */ 195 #define SOCRAM_BANKINFO_SZBASE 8192 196 #define SOCRAM_BANKSIZE_SHIFT 13 /* SOCRAM_BANKINFO_SZBASE */ 197 198 #endif /* _SBSOCRAM_H */ 199