1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * HND OOBR interface header 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2020, Broadcom. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Unless you and Broadcom execute a separate written software license 7*4882a593Smuzhiyun * agreement governing use of this software, this software is licensed to you 8*4882a593Smuzhiyun * under the terms of the GNU General Public License version 2 (the "GPL"), 9*4882a593Smuzhiyun * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10*4882a593Smuzhiyun * following added to such license: 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * As a special exception, the copyright holders of this software give you 13*4882a593Smuzhiyun * permission to link this software with independent modules, and to copy and 14*4882a593Smuzhiyun * distribute the resulting executable under terms of your choice, provided that 15*4882a593Smuzhiyun * you also meet, for each linked independent module, the terms and conditions of 16*4882a593Smuzhiyun * the license of that module. An independent module is a module which is not 17*4882a593Smuzhiyun * derived from this software. The special exception does not apply to any 18*4882a593Smuzhiyun * modifications of the software. 19*4882a593Smuzhiyun * 20*4882a593Smuzhiyun * 21*4882a593Smuzhiyun * <<Broadcom-WL-IPTag/Dual:>> 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #ifndef _hndoobr_h_ 25*4882a593Smuzhiyun #define _hndoobr_h_ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #include <typedefs.h> 28*4882a593Smuzhiyun #include <siutils.h> 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* for 'srcpidx' of hnd_oobr_get_intr_config() */ 31*4882a593Smuzhiyun #define HND_CORE_MAIN_INTR 0 32*4882a593Smuzhiyun #define HND_CORE_ALT_INTR 1 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun uint32 hnd_oobr_get_clkpwrreq(si_t *sih, uint coreid); 35*4882a593Smuzhiyun uint32 hnd_oobr_get_intstatus(si_t *sih); 36*4882a593Smuzhiyun int hnd_oobr_get_intr_config(si_t *sih, uint srccidx, uint srcpidx, uint dstcidx, uint *dstpidx); 37*4882a593Smuzhiyun int hnd_oobr_set_intr_src(si_t *sih, uint dstcidx, uint dstpidx, uint intrnum); 38*4882a593Smuzhiyun void hnd_oobr_init(si_t *sih); 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #ifdef BCMDBG 41*4882a593Smuzhiyun /* dump oobr registers values to console */ 42*4882a593Smuzhiyun void hnd_oobr_dump(si_t *sih); 43*4882a593Smuzhiyun #endif 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define OOBR_INVALID_PORT 0xFFu 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* per core source/dest sel reg */ 48*4882a593Smuzhiyun #define OOBR_INTR_PER_CONFREG 4u /* 4 interrupts per configure reg */ 49*4882a593Smuzhiyun #define OOBR_INTR_NUM_MASK 0x7Fu 50*4882a593Smuzhiyun #define OOBR_INTR_EN 0x80u 51*4882a593Smuzhiyun /* per core config reg */ 52*4882a593Smuzhiyun #define OOBR_CORECNF_OUTPUT_MASK 0x0000FF00u 53*4882a593Smuzhiyun #define OOBR_CORECNF_OUTPUT_SHIFT 8u 54*4882a593Smuzhiyun #define OOBR_CORECNF_INPUT_MASK 0x00FF0000u 55*4882a593Smuzhiyun #define OOBR_CORECNF_INPUT_SHIFT 16u 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define OOBR_EXT_RSRC_REQ_PERCORE_OFFSET 0x34u 58*4882a593Smuzhiyun #define OOBR_EXT_RSRC_OFFSET 0x100u 59*4882a593Smuzhiyun #define OOBR_EXT_RSRC_SHIFT 7u 60*4882a593Smuzhiyun #define OOBR_EXT_RSRC_REQ_ADDR(oodr_base, core_idx) (uint32)((uintptr)(oodr_base) +\ 61*4882a593Smuzhiyun OOBR_EXT_RSRC_OFFSET + ((core_idx) << OOBR_EXT_RSRC_SHIFT) +\ 62*4882a593Smuzhiyun OOBR_EXT_RSRC_REQ_PERCORE_OFFSET) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun typedef volatile struct hndoobr_percore_reg { 65*4882a593Smuzhiyun uint32 sourcesel[OOBR_INTR_PER_CONFREG]; /* 0x00 - 0x0c */ 66*4882a593Smuzhiyun uint32 destsel[OOBR_INTR_PER_CONFREG]; /* 0x10 - 0x1c */ 67*4882a593Smuzhiyun uint32 reserved[4]; 68*4882a593Smuzhiyun uint32 clkpwrreq; /* 0x30 */ 69*4882a593Smuzhiyun uint32 extrsrcreq; /* 0x34 */ 70*4882a593Smuzhiyun uint32 config; /* 0x38 */ 71*4882a593Smuzhiyun uint32 reserved1[17]; /* 0x3c to 0x7c */ 72*4882a593Smuzhiyun } hndoobr_percore_reg_t; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* capability reg */ 75*4882a593Smuzhiyun #define OOBR_CAP_CORECNT_MASK 0x0000001Fu 76*4882a593Smuzhiyun #define OOBR_CAP_MAX_INT2CORE_MASK 0x00F00000u 77*4882a593Smuzhiyun #define OOBR_CAP_MAX_INT2CORE_SHIFT 20u 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define OOBR_MAX_INT_PER_REG 4u 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* CoreNConfig reg */ 82*4882a593Smuzhiyun #define OOBR_PERCORE_CORENCONFIG_INTOUTPUTS_MASK 0x0000FF00u 83*4882a593Smuzhiyun #define OOBR_PERCORE_CORENCONFIG_INTOUTPUTS_SHIFT 8u 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun typedef volatile struct hndoobr_reg { 86*4882a593Smuzhiyun uint32 capability; /* 0x00 */ 87*4882a593Smuzhiyun uint32 reserved[3]; 88*4882a593Smuzhiyun uint32 intstatus[4]; /* 0x10 - 0x1c */ 89*4882a593Smuzhiyun uint32 reserved1[56]; /* 0x20 - 0xfc */ 90*4882a593Smuzhiyun hndoobr_percore_reg_t percore_reg[1]; /* 0x100 */ 91*4882a593Smuzhiyun } hndoobr_reg_t; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #endif /* _hndoobr_h_ */ 94