1 /* 2 * EVENT_LOG System Definitions 3 * 4 * This file describes the payloads of event log entries that are data buffers 5 * rather than formatted string entries. The contents are generally XTLVs. 6 * 7 * Copyright (C) 2020, Broadcom. 8 * 9 * Unless you and Broadcom execute a separate written software license 10 * agreement governing use of this software, this software is licensed to you 11 * under the terms of the GNU General Public License version 2 (the "GPL"), 12 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 13 * following added to such license: 14 * 15 * As a special exception, the copyright holders of this software give you 16 * permission to link this software with independent modules, and to copy and 17 * distribute the resulting executable under terms of your choice, provided that 18 * you also meet, for each linked independent module, the terms and conditions of 19 * the license of that module. An independent module is a module which is not 20 * derived from this software. The special exception does not apply to any 21 * modifications of the software. 22 * 23 * 24 * <<Broadcom-WL-IPTag/Dual:>> 25 */ 26 27 #ifndef _EVENT_LOG_PAYLOAD_H_ 28 #define _EVENT_LOG_PAYLOAD_H_ 29 30 #include <typedefs.h> 31 #include <bcmutils.h> 32 #include <ethernet.h> 33 #include <event_log_tag.h> 34 35 /** 36 * A (legacy) timestamp message 37 */ 38 typedef struct ts_message { 39 uint32 timestamp; 40 uint32 cyclecount; 41 } ts_msg_t; 42 43 /** 44 * Enhanced timestamp message 45 */ 46 typedef struct enhanced_ts_message { 47 uint32 version; 48 /* More data, depending on version */ 49 uint8 data[]; 50 } ets_msg_t; 51 52 #define ENHANCED_TS_MSG_VERSION_1 (1u) 53 54 /** 55 * Enhanced timestamp message, version 1 56 */ 57 typedef struct enhanced_ts_message_v1 { 58 uint32 version; 59 uint32 timestamp; /* PMU time, in milliseconds */ 60 uint32 cyclecount; 61 uint32 cpu_freq; 62 } ets_msg_v1_t; 63 64 #define EVENT_LOG_XTLV_ID_STR 0 /**< XTLV ID for a string */ 65 #define EVENT_LOG_XTLV_ID_TXQ_SUM 1 /**< XTLV ID for txq_summary_t */ 66 #define EVENT_LOG_XTLV_ID_SCBDATA_SUM 2 /**< XTLV ID for cb_subq_summary_t */ 67 #define EVENT_LOG_XTLV_ID_SCBDATA_AMPDU_TX_SUM 3 /**< XTLV ID for scb_ampdu_tx_summary_t */ 68 #define EVENT_LOG_XTLV_ID_BSSCFGDATA_SUM 4 /**< XTLV ID for bsscfg_q_summary_t */ 69 #define EVENT_LOG_XTLV_ID_UCTXSTATUS 5 /**< XTLV ID for ucode TxStatus array */ 70 #define EVENT_LOG_XTLV_ID_TXQ_SUM_V2 6 /**< XTLV ID for txq_summary_v2_t */ 71 #define EVENT_LOG_XTLV_ID_BUF 7 /**< XTLV ID for event_log_buffer_t */ 72 73 /** 74 * An XTLV holding a string 75 * String is not null terminated, length is the XTLV len. 76 */ 77 typedef struct xtlv_string { 78 uint16 id; /* XTLV ID: EVENT_LOG_XTLV_ID_STR */ 79 uint16 len; /* XTLV Len (String length) */ 80 char str[1]; /* var len array characters */ 81 } xtlv_string_t; 82 83 #define XTLV_STRING_FULL_LEN(str_len) (BCM_XTLV_HDR_SIZE + (str_len) * sizeof(char)) 84 85 /** 86 * Summary for a single TxQ context 87 * Two of these will be used per TxQ context---one for the high TxQ, and one for 88 * the low txq that contains DMA prepared pkts. The high TxQ is a full multi-precidence 89 * queue and also has a BSSCFG map to identify the BSSCFGS associated with the queue context. 90 * The low txq counterpart does not populate the BSSCFG map. 91 * The excursion queue will have no bsscfgs associated and is the first queue dumped. 92 */ 93 typedef struct txq_summary { 94 uint16 id; /* XTLV ID: EVENT_LOG_XTLV_ID_TXQ_SUM */ 95 uint16 len; /* XTLV Len */ 96 uint32 bsscfg_map; /* bitmap of bsscfg indexes associated with this queue */ 97 uint32 stopped; /* flow control bitmap */ 98 uint8 prec_count; /* count of precedences/fifos and len of following array */ 99 uint8 pad; 100 uint16 plen[1]; /* var len array of lengths of each prec/fifo in the queue */ 101 } txq_summary_t; 102 103 #define TXQ_SUMMARY_LEN (OFFSETOF(txq_summary_t, plen)) 104 #define TXQ_SUMMARY_FULL_LEN(num_q) (TXQ_SUMMARY_LEN + (num_q) * sizeof(uint16)) 105 106 typedef struct txq_summary_v2 { 107 uint16 id; /* XTLV ID: EVENT_LOG_XTLV_ID_TXQ_SUM_V2 */ 108 uint16 len; /* XTLV Len */ 109 uint32 bsscfg_map; /* bitmap of bsscfg indexes associated with this queue */ 110 uint32 stopped; /* flow control bitmap */ 111 uint32 hw_stopped; /* flow control bitmap */ 112 uint8 prec_count; /* count of precedences/fifos and len of following array */ 113 uint8 pad; 114 uint16 plen[1]; /* var len array of lengths of each prec/fifo in the queue */ 115 } txq_summary_v2_t; 116 117 #define TXQ_SUMMARY_V2_LEN (OFFSETOF(txq_summary_v2_t, plen)) 118 #define TXQ_SUMMARY_V2_FULL_LEN(num_q) (TXQ_SUMMARY_V2_LEN + (num_q) * sizeof(uint16)) 119 120 /** 121 * Summary for tx datapath of an SCB cubby 122 * This is a generic summary structure (one size fits all) with 123 * a cubby ID and sub-ID to differentiate SCB cubby types and possible sub-queues. 124 */ 125 typedef struct scb_subq_summary { 126 uint16 id; /* XTLV ID: EVENT_LOG_XTLV_ID_SCBDATA_SUM */ 127 uint16 len; /* XTLV Len */ 128 uint32 flags; /* cubby specficic flags */ 129 uint8 cubby_id; /* ID registered for cubby */ 130 uint8 sub_id; /* sub ID if a cubby has more than one queue */ 131 uint8 prec_count; /* count of precedences/fifos and len of following array */ 132 uint8 pad; 133 uint16 plen[1]; /* var len array of lengths of each prec/fifo in the queue */ 134 } scb_subq_summary_t; 135 136 #define SCB_SUBQ_SUMMARY_LEN (OFFSETOF(scb_subq_summary_t, plen)) 137 #define SCB_SUBQ_SUMMARY_FULL_LEN(num_q) (SCB_SUBQ_SUMMARY_LEN + (num_q) * sizeof(uint16)) 138 139 /* scb_subq_summary_t.flags for APPS */ 140 #define SCBDATA_APPS_F_PS 0x00000001 141 #define SCBDATA_APPS_F_PSPEND 0x00000002 142 #define SCBDATA_APPS_F_INPVB 0x00000004 143 #define SCBDATA_APPS_F_APSD_USP 0x00000008 144 #define SCBDATA_APPS_F_TXBLOCK 0x00000010 145 #define SCBDATA_APPS_F_APSD_HPKT_TMR 0x00000020 146 #define SCBDATA_APPS_F_APSD_TX_PEND 0x00000040 147 #define SCBDATA_APPS_F_INTRANS 0x00000080 148 #define SCBDATA_APPS_F_OFF_PEND 0x00000100 149 #define SCBDATA_APPS_F_OFF_BLOCKED 0x00000200 150 #define SCBDATA_APPS_F_OFF_IN_PROG 0x00000400 151 152 /** 153 * Summary for tx datapath AMPDU SCB cubby 154 * This is a specific data structure to describe the AMPDU datapath state for an SCB 155 * used instead of scb_subq_summary_t. 156 * Info is for one TID, so one will be dumped per BA TID active for an SCB. 157 */ 158 typedef struct scb_ampdu_tx_summary { 159 uint16 id; /* XTLV ID: EVENT_LOG_XTLV_ID_SCBDATA_AMPDU_TX_SUM */ 160 uint16 len; /* XTLV Len */ 161 uint32 flags; /* misc flags */ 162 uint8 tid; /* initiator TID (priority) */ 163 uint8 ba_state; /* internal BA state */ 164 uint8 bar_cnt; /* number of bars sent with no progress */ 165 uint8 retry_bar; /* reason code if bar to be retried at watchdog */ 166 uint16 barpending_seq; /* seqnum for bar */ 167 uint16 bar_ackpending_seq; /* seqnum of bar for which ack is pending */ 168 uint16 start_seq; /* seqnum of the first unacknowledged packet */ 169 uint16 max_seq; /* max unacknowledged seqnum sent */ 170 uint32 released_bytes_inflight; /* Number of bytes pending in bytes */ 171 uint32 released_bytes_target; 172 } scb_ampdu_tx_summary_t; 173 174 /* scb_ampdu_tx_summary.flags defs */ 175 #define SCBDATA_AMPDU_TX_F_BAR_ACKPEND 0x00000001 /* bar_ackpending */ 176 177 /** XTLV stuct to summarize a BSSCFG's packet queue */ 178 typedef struct bsscfg_q_summary { 179 uint16 id; /* XTLV ID: EVENT_LOG_XTLV_ID_BSSCFGDATA_SUM */ 180 uint16 len; /* XTLV Len */ 181 struct ether_addr BSSID; /* BSSID */ 182 uint8 bsscfg_idx; /* bsscfg index */ 183 uint8 type; /* bsscfg type enumeration: BSSCFG_TYPE_XXX */ 184 uint8 subtype; /* bsscfg subtype enumeration: BSSCFG_SUBTYPE_XXX */ 185 uint8 prec_count; /* count of precedences/fifos and len of following array */ 186 uint16 plen[1]; /* var len array of lengths of each prec/fifo in the queue */ 187 } bsscfg_q_summary_t; 188 189 #define BSSCFG_Q_SUMMARY_LEN (OFFSETOF(bsscfg_q_summary_t, plen)) 190 #define BSSCFG_Q_SUMMARY_FULL_LEN(num_q) (BSSCFG_Q_SUMMARY_LEN + (num_q) * sizeof(uint16)) 191 192 /** 193 * An XTLV holding a TxStats array 194 * TxStatus entries are 8 or 16 bytes, size in words (2 or 4) givent in 195 * entry_size field. 196 * Array is uint32 words 197 */ 198 typedef struct xtlv_uc_txs { 199 uint16 id; /* XTLV ID: EVENT_LOG_XTLV_ID_UCTXSTATUS */ 200 uint16 len; /* XTLV Len */ 201 uint8 entry_size; /* num uint32 words per entry */ 202 uint8 pad[3]; /* reserved, zero */ 203 uint32 w[1]; /* var len array of words */ 204 } xtlv_uc_txs_t; 205 206 #define XTLV_UCTXSTATUS_LEN (OFFSETOF(xtlv_uc_txs_t, w)) 207 #define XTLV_UCTXSTATUS_FULL_LEN(words) (XTLV_UCTXSTATUS_LEN + (words) * sizeof(uint32)) 208 209 #define SCAN_SUMMARY_VERSION_1 1u 210 #ifndef WLSCAN_SUMMARY_VERSION_ALIAS 211 #define SCAN_SUMMARY_VERSION SCAN_SUMMARY_VERSION_1 212 #endif 213 /* Scan flags */ 214 #define SCAN_SUM_CHAN_INFO 0x1 215 /* Scan_sum flags */ 216 #define BAND5G_SIB_ENAB 0x2 217 #define BAND2G_SIB_ENAB 0x4 218 #define PARALLEL_SCAN 0x8 219 #define SCAN_ABORT 0x10 220 /* Note: Definitions being reused in chan_info as SCAN_SUM_SCAN_CORE need clean up */ 221 #define SC_LOWSPAN_SCAN 0x20 222 /* Note: Definitions being reused in scan summary info as WL_SSUM_CLIENT_MASK need clean up */ 223 #define SC_SCAN 0x40 224 225 #define WL_SSUM_CLIENT_MASK 0x1C0u /* bit 8 - 6 */ 226 #define WL_SSUM_CLIENT_SHIFT 6u /* shift client scan opereration */ 227 228 #define WL_SSUM_MODE_MASK 0xE00u /* bit 11 - 9 */ 229 #define WL_SSUM_MODE_SHIFT 9u /* shift mode scan operation */ 230 231 /* Common bits for channel and scan summary info */ 232 #define SCAN_SUM_CHAN_RESHED 0x1000 /* Bit 12 as resched scan for chaninfo and scan summary */ 233 234 #define WL_SSUM_CLIENT_ASSOCSCAN 0x0u /* Log as scan requested client is assoc scan */ 235 #define WL_SSUM_CLIENT_ROAMSCAN 0x1u /* Log as scan requested client is roam scan */ 236 #define WL_SSUM_CLIENT_FWSCAN 0x2u /* Log as scan requested client is other fw scan */ 237 #define WL_SSUM_CLIENT_HOSTSCAN 0x3u /* Log as scan requested client is host scan */ 238 239 #define WL_SSUM_SCANFLAG_INVALID 0x7u /* Log for invalid scan client or mode */ 240 241 /* scan_channel_info flags */ 242 #define ACTIVE_SCAN_SCN_SUM 0x2 243 #define SCAN_SUM_WLC_CORE0 0x4 244 #define SCAN_SUM_WLC_CORE1 0x8 245 #define HOME_CHAN 0x10 246 #define SCAN_SUM_SCAN_CORE 0x20 247 248 typedef struct wl_scan_ssid_info 249 { 250 uint8 ssid_len; /* the length of SSID */ 251 uint8 ssid[32]; /* SSID string */ 252 } wl_scan_ssid_info_t; 253 254 typedef struct wl_scan_channel_info { 255 uint16 chanspec; /* chanspec scanned */ 256 uint16 reserv; 257 uint32 start_time; /* Scan start time in 258 * milliseconds for the chanspec 259 * or home_dwell time start 260 */ 261 uint32 end_time; /* Scan end time in 262 * milliseconds for the chanspec 263 * or home_dwell time end 264 */ 265 uint16 probe_count; /* No of probes sent out. For future use 266 */ 267 uint16 scn_res_count; /* Count of scan_results found per 268 * channel. For future use 269 */ 270 } wl_scan_channel_info_t; 271 272 typedef struct wl_scan_summary_info { 273 uint32 total_chan_num; /* Total number of channels scanned */ 274 uint32 scan_start_time; /* Scan start time in milliseconds */ 275 uint32 scan_end_time; /* Scan end time in milliseconds */ 276 wl_scan_ssid_info_t ssid[1]; /* SSID being scanned in current 277 * channel. For future use 278 */ 279 } wl_scan_summary_info_t; 280 281 struct wl_scan_summary { 282 uint8 version; /* Version */ 283 uint8 reserved; 284 uint16 len; /* Length of the data buffer including SSID 285 * list. 286 */ 287 uint16 sync_id; /* Scan Sync ID */ 288 uint16 scan_flags; /* flags [0] or SCAN_SUM_CHAN_INFO = */ 289 /* channel_info, if not set */ 290 /* it is scan_summary_info */ 291 /* when channel_info is used, */ 292 /* the following flag bits are overridden: */ 293 /* flags[1] or ACTIVE_SCAN_SCN_SUM = active channel if set */ 294 /* passive if not set */ 295 /* flags[2] or WLC_CORE0 = if set, represents wlc_core0 */ 296 /* flags[3] or WLC_CORE1 = if set, represents wlc_core1 */ 297 /* flags[4] or HOME_CHAN = if set, represents home-channel */ 298 /* flags[5] or SCAN_SUM_SCAN_CORE = if set, 299 * represents chan_info from scan core. 300 */ 301 /* flags[12] SCAN_SUM_CHAN_RESHED indicate scan rescheduled */ 302 /* flags[6:11, 13:15] = reserved */ 303 /* when scan_summary_info is used, */ 304 /* the following flag bits are used: */ 305 /* flags[1] or BAND5G_SIB_ENAB = */ 306 /* allowSIBParallelPassiveScan on 5G band */ 307 /* flags[2] or BAND2G_SIB_ENAB = */ 308 /* allowSIBParallelPassiveScan on 2G band */ 309 /* flags[3] or PARALLEL_SCAN = Parallel scan enabled or not */ 310 /* flags[4] or SCAN_ABORT = SCAN_ABORTED scenario */ 311 /* flags[5] = reserved */ 312 /* flags[6:8] is used as count value to identify SCAN CLIENT 313 * WL_SSUM_CLIENT_ASSOCSCAN 0x0u, WL_SSUM_CLIENT_ROAMSCAN 0x1u, 314 * WL_SSUM_CLIENT_FWSCAN 0x2u, WL_SSUM_CLIENT_HOSTSCAN 0x3u 315 */ 316 /* flags[9:11] is used as count value to identify SCAN MODE 317 * WL_SCAN_MODE_HIGH_ACC 0u, WL_SCAN_MODE_LOW_SPAN 1u, 318 * WL_SCAN_MODE_LOW_POWER 2u 319 */ 320 /* flags[12] SCAN_SUM_CHAN_RESHED indicate scan rescheduled */ 321 /* flags[13:15] = reserved */ 322 union { 323 wl_scan_channel_info_t scan_chan_info; /* scan related information 324 * for each channel scanned 325 */ 326 wl_scan_summary_info_t scan_sum_info; /* Cumulative scan related 327 * information. 328 */ 329 } u; 330 }; 331 332 #define SCAN_SUMMARY_VERSION_2 2u 333 struct wl_scan_summary_v2 { 334 uint8 version; /* Version */ 335 uint8 reserved; 336 uint16 len; /* Length of the data buffer including SSID 337 * list. 338 */ 339 uint16 sync_id; /* Scan Sync ID */ 340 uint16 scan_flags; /* flags [0] or SCAN_SUM_CHAN_INFO = */ 341 /* channel_info, if not set */ 342 /* it is scan_summary_info */ 343 /* when channel_info is used, */ 344 /* the following flag bits are overridden: */ 345 /* flags[1] or ACTIVE_SCAN_SCN_SUM = active channel if set */ 346 /* passive if not set */ 347 /* flags[2] or WLC_CORE0 = if set, represents wlc_core0 */ 348 /* flags[3] or WLC_CORE1 = if set, represents wlc_core1 */ 349 /* flags[4] or HOME_CHAN = if set, represents home-channel */ 350 /* flags[5] or SCAN_SUM_SCAN_CORE = if set, 351 * represents chan_info from scan core. 352 */ 353 /* flags[12] SCAN_SUM_CHAN_RESHED indicate scan rescheduled */ 354 /* flags[6:11, 13:15] = reserved */ 355 /* when scan_summary_info is used, */ 356 /* the following flag bits are used: */ 357 /* flags[1] or BAND5G_SIB_ENAB = */ 358 /* allowSIBParallelPassiveScan on 5G band */ 359 /* flags[2] or BAND2G_SIB_ENAB = */ 360 /* allowSIBParallelPassiveScan on 2G band */ 361 /* flags[3] or PARALLEL_SCAN = Parallel scan enabled or not */ 362 /* flags[4] or SCAN_ABORT = SCAN_ABORTED scenario */ 363 /* flags[5] = reserved */ 364 /* flags[6:8] is used as count value to identify SCAN CLIENT 365 * WL_SSUM_CLIENT_ASSOCSCAN 0x0u, WL_SSUM_CLIENT_ROAMSCAN 0x1u, 366 * WL_SSUM_CLIENT_FWSCAN 0x2u, WL_SSUM_CLIENT_HOSTSCAN 0x3u 367 */ 368 /* flags[9:11] is used as count value to identify SCAN MODE 369 * WL_SCAN_MODE_HIGH_ACC 0u, WL_SCAN_MODE_LOW_SPAN 1u, 370 * WL_SCAN_MODE_LOW_POWER 2u 371 */ 372 /* flags[12] SCAN_SUM_CHAN_RESHED indicate scan rescheduled */ 373 /* flags[13:15] = reserved */ 374 /* scan_channel_ctx_t chan_cnt; */ 375 uint8 channel_cnt_aux; /* Number of channels to be scanned on Aux core */ 376 uint8 channel_cnt_main; /* Number of channels to be scanned on Main core */ 377 uint8 channel_cnt_sc; /* Number of channels to be scanned on Scan core */ 378 uint8 active_channel_cnt; 379 uint8 passive_channel_cnt; 380 char pad[3]; /* Pad to keep it 32 bit aligned */ 381 union { 382 wl_scan_channel_info_t scan_chan_info; /* scan related information 383 * for each channel scanned 384 */ 385 wl_scan_summary_info_t scan_sum_info; /* Cumulative scan related 386 * information. 387 */ 388 } u; 389 }; 390 /* Channel switch log record structure 391 * Host may map the following structure on channel switch event log record 392 * received from dongle. Note that all payload entries in event log record are 393 * uint32/int32. 394 */ 395 typedef struct wl_chansw_event_log_record { 396 uint32 time; /* Time in us */ 397 uint32 old_chanspec; /* Old channel spec */ 398 uint32 new_chanspec; /* New channel spec */ 399 uint32 chansw_reason; /* Reason for channel change */ 400 int32 dwell_time; 401 } wl_chansw_event_log_record_t; 402 403 typedef struct wl_chansw_event_log_record_v2 { 404 uint32 time; /* Time in us */ 405 uint32 old_chanspec; /* Old channel spec */ 406 uint32 new_chanspec; /* New channel spec */ 407 uint32 chansw_reason; /* Reason for channel change */ 408 int32 dwell_time; 409 uint32 core; 410 int32 phychanswtime; /* channel switch time */ 411 } wl_chansw_event_log_record_v2_t; 412 413 /* Sub-block type for EVENT_LOG_TAG_AMPDU_DUMP */ 414 typedef enum { 415 WL_AMPDU_STATS_TYPE_RXMCSx1 = 0, /* RX MCS rate (Nss = 1) */ 416 WL_AMPDU_STATS_TYPE_RXMCSx2 = 1, 417 WL_AMPDU_STATS_TYPE_RXMCSx3 = 2, 418 WL_AMPDU_STATS_TYPE_RXMCSx4 = 3, 419 WL_AMPDU_STATS_TYPE_RXVHTx1 = 4, /* RX VHT rate (Nss = 1) */ 420 WL_AMPDU_STATS_TYPE_RXVHTx2 = 5, 421 WL_AMPDU_STATS_TYPE_RXVHTx3 = 6, 422 WL_AMPDU_STATS_TYPE_RXVHTx4 = 7, 423 WL_AMPDU_STATS_TYPE_TXMCSx1 = 8, /* TX MCS rate (Nss = 1) */ 424 WL_AMPDU_STATS_TYPE_TXMCSx2 = 9, 425 WL_AMPDU_STATS_TYPE_TXMCSx3 = 10, 426 WL_AMPDU_STATS_TYPE_TXMCSx4 = 11, 427 WL_AMPDU_STATS_TYPE_TXVHTx1 = 12, /* TX VHT rate (Nss = 1) */ 428 WL_AMPDU_STATS_TYPE_TXVHTx2 = 13, 429 WL_AMPDU_STATS_TYPE_TXVHTx3 = 14, 430 WL_AMPDU_STATS_TYPE_TXVHTx4 = 15, 431 WL_AMPDU_STATS_TYPE_RXMCSSGI = 16, /* RX SGI usage (for all MCS rates) */ 432 WL_AMPDU_STATS_TYPE_TXMCSSGI = 17, /* TX SGI usage (for all MCS rates) */ 433 WL_AMPDU_STATS_TYPE_RXVHTSGI = 18, /* RX SGI usage (for all VHT rates) */ 434 WL_AMPDU_STATS_TYPE_TXVHTSGI = 19, /* TX SGI usage (for all VHT rates) */ 435 WL_AMPDU_STATS_TYPE_RXMCSPER = 20, /* RX PER (for all MCS rates) */ 436 WL_AMPDU_STATS_TYPE_TXMCSPER = 21, /* TX PER (for all MCS rates) */ 437 WL_AMPDU_STATS_TYPE_RXVHTPER = 22, /* RX PER (for all VHT rates) */ 438 WL_AMPDU_STATS_TYPE_TXVHTPER = 23, /* TX PER (for all VHT rates) */ 439 WL_AMPDU_STATS_TYPE_RXDENS = 24, /* RX AMPDU density */ 440 WL_AMPDU_STATS_TYPE_TXDENS = 25, /* TX AMPDU density */ 441 WL_AMPDU_STATS_TYPE_RXMCSOK = 26, /* RX all MCS rates */ 442 WL_AMPDU_STATS_TYPE_RXVHTOK = 27, /* RX all VHT rates */ 443 WL_AMPDU_STATS_TYPE_TXMCSALL = 28, /* TX all MCS rates */ 444 WL_AMPDU_STATS_TYPE_TXVHTALL = 29, /* TX all VHT rates */ 445 WL_AMPDU_STATS_TYPE_TXMCSOK = 30, /* TX all MCS rates */ 446 WL_AMPDU_STATS_TYPE_TXVHTOK = 31, /* TX all VHT rates */ 447 WL_AMPDU_STATS_TYPE_RX_HE_SUOK = 32, /* DL SU MPDU frame per MCS */ 448 WL_AMPDU_STATS_TYPE_RX_HE_SU_DENS = 33, /* DL SU AMPDU DENSITY */ 449 WL_AMPDU_STATS_TYPE_RX_HE_MUMIMOOK = 34, /* DL MUMIMO Frame per MCS */ 450 WL_AMPDU_STATS_TYPE_RX_HE_MUMIMO_DENS = 35, /* DL MUMIMO AMPDU Density */ 451 WL_AMPDU_STATS_TYPE_RX_HE_DLOFDMAOK = 36, /* DL OFDMA Frame per MCS */ 452 WL_AMPDU_STATS_TYPE_RX_HE_DLOFDMA_DENS = 37, /* DL OFDMA AMPDU Density */ 453 WL_AMPDU_STATS_TYPE_RX_HE_DLOFDMA_HIST = 38, /* DL OFDMA frame RU histogram */ 454 WL_AMPDU_STATS_TYPE_TX_HE_MCSALL = 39, /* TX HE (SU+MU) frames, all rates */ 455 WL_AMPDU_STATS_TYPE_TX_HE_MCSOK = 40, /* TX HE (SU+MU) frames succeeded */ 456 WL_AMPDU_STATS_TYPE_TX_HE_MUALL = 41, /* TX MU (UL OFDMA) frames all rates */ 457 WL_AMPDU_STATS_TYPE_TX_HE_MUOK = 42, /* TX MU (UL OFDMA) frames succeeded */ 458 WL_AMPDU_STATS_TYPE_TX_HE_RUBW = 43, /* TX UL RU by BW histogram */ 459 WL_AMPDU_STATS_TYPE_TX_HE_PADDING = 44, /* TX padding total (single value) */ 460 WL_AMPDU_STATS_TYPE_RX_COUNTERS = 45, /* Additional AMPDU_RX module counters 461 * per-slice 462 */ 463 WL_AMPDU_STATS_MAX_CNTS = 64 464 } wl_ampdu_stat_enum_t; 465 typedef struct { 466 uint16 type; /* AMPDU statistics sub-type */ 467 uint16 len; /* Number of 32-bit counters */ 468 uint32 counters[WL_AMPDU_STATS_MAX_CNTS]; 469 } wl_ampdu_stats_generic_t; 470 471 typedef wl_ampdu_stats_generic_t wl_ampdu_stats_rx_t; 472 typedef wl_ampdu_stats_generic_t wl_ampdu_stats_tx_t; 473 474 typedef struct { 475 uint16 type; /* AMPDU statistics sub-type */ 476 uint16 len; /* Number of 32-bit counters + 2 */ 477 uint32 total_ampdu; 478 uint32 total_mpdu; 479 uint32 aggr_dist[WL_AMPDU_STATS_MAX_CNTS + 1]; 480 } wl_ampdu_stats_aggrsz_t; 481 482 /* AMPDU_RX module's per-slice counters. Sent by ecounters as subtype of 483 * WL_IFSTATS_XTLV_RX_AMPDU_STATS ecounters type 484 */ 485 #define WLC_AMPDU_RX_STATS_V1 (1u) 486 typedef struct wlc_ampdu_rx_stats { 487 uint16 version; 488 uint16 len; 489 /* responder side counters */ 490 uint32 rxampdu; /**< ampdus recd */ 491 uint32 rxmpdu; /**< mpdus recd in a ampdu */ 492 uint32 rxht; /**< mpdus recd at ht rate and not in a ampdu */ 493 uint32 rxlegacy; /**< mpdus recd at legacy rate */ 494 uint32 rxampdu_sgi; /**< ampdus recd with sgi */ 495 uint32 rxampdu_stbc; /**< ampdus recd with stbc */ 496 uint32 rxnobapol; /**< mpdus recd without a ba policy */ 497 uint32 rxholes; /**< missed seq numbers on rx side */ 498 uint32 rxqed; /**< pdus buffered before sending up */ 499 uint32 rxdup; /**< duplicate pdus */ 500 uint32 rxstuck; /**< watchdog bailout for stuck state */ 501 uint32 rxoow; /**< out of window pdus */ 502 uint32 rxoos; /**< out of seq pdus */ 503 uint32 rxaddbareq; /**< addba req recd */ 504 uint32 txaddbaresp; /**< addba resp sent */ 505 uint32 rxbar; /**< bar recd */ 506 uint32 txba; /**< ba sent */ 507 508 /* general: both initiator and responder */ 509 uint32 rxunexp; /**< unexpected packets */ 510 uint32 txdelba; /**< delba sent */ 511 uint32 rxdelba; /**< delba recd */ 512 } wlc_ampdu_rx_stats_t; 513 514 /* Sub-block type for WL_IFSTATS_XTLV_HE_TXMU_STATS */ 515 typedef enum { 516 /* Reserve 0 to avoid potential concerns */ 517 WL_HE_TXMU_STATS_TYPE_TIME = 1, /* per-dBm, total usecs transmitted */ 518 WL_HE_TXMU_STATS_TYPE_PAD_TIME = 2, /* per-dBm, padding usecs transmitted */ 519 } wl_he_txmu_stat_enum_t; 520 #define WL_IFSTATS_HE_TXMU_MAX 32u 521 522 /* Sub-block type for EVENT_LOG_TAG_MSCHPROFILE */ 523 #define WL_MSCH_PROFILER_START 0 /* start event check */ 524 #define WL_MSCH_PROFILER_EXIT 1 /* exit event check */ 525 #define WL_MSCH_PROFILER_REQ 2 /* request event */ 526 #define WL_MSCH_PROFILER_CALLBACK 3 /* call back event */ 527 #define WL_MSCH_PROFILER_MESSAGE 4 /* message event */ 528 #define WL_MSCH_PROFILER_PROFILE_START 5 529 #define WL_MSCH_PROFILER_PROFILE_END 6 530 #define WL_MSCH_PROFILER_REQ_HANDLE 7 531 #define WL_MSCH_PROFILER_REQ_ENTITY 8 532 #define WL_MSCH_PROFILER_CHAN_CTXT 9 533 #define WL_MSCH_PROFILER_EVENT_LOG 10 534 #define WL_MSCH_PROFILER_REQ_TIMING 11 535 #define WL_MSCH_PROFILER_TYPE_MASK 0x00ff 536 #define WL_MSCH_PROFILER_WLINDEX_SHIFT 8 537 #define WL_MSCH_PROFILER_WLINDEX_MASK 0x0f00 538 #define WL_MSCH_PROFILER_VER_SHIFT 12 539 #define WL_MSCH_PROFILER_VER_MASK 0xf000 540 541 /* MSCH Event data current verion */ 542 #define WL_MSCH_PROFILER_VER 2 543 544 /* msch version history */ 545 #define WL_MSCH_PROFILER_RSDB_VER 1 546 #define WL_MSCH_PROFILER_REPORT_VER 2 547 548 /* msch collect header size */ 549 #define WL_MSCH_PROFILE_HEAD_SIZE OFFSETOF(msch_collect_tlv_t, value) 550 551 /* msch event log header size */ 552 #define WL_MSCH_EVENT_LOG_HEAD_SIZE OFFSETOF(msch_event_log_profiler_event_data_t, data) 553 554 /* MSCH data buffer size */ 555 #define WL_MSCH_PROFILER_BUFFER_SIZE 512 556 557 /* request type used in wlc_msch_req_param_t struct */ 558 #define WL_MSCH_RT_BOTH_FIXED 0 /* both start and end time is fixed */ 559 #define WL_MSCH_RT_START_FLEX 1 /* start time is flexible and duration is fixed */ 560 #define WL_MSCH_RT_DUR_FLEX 2 /* start time is fixed and end time is flexible */ 561 #define WL_MSCH_RT_BOTH_FLEX 3 /* Both start and duration is flexible */ 562 563 /* Flags used in wlc_msch_req_param_t struct */ 564 #define WL_MSCH_REQ_FLAGS_CHAN_CONTIGUOUS (1 << 0) /* Don't break up channels in chanspec_list */ 565 #define WL_MSCH_REQ_FLAGS_MERGE_CONT_SLOTS (1 << 1) /* No slot end if slots are continous */ 566 #define WL_MSCH_REQ_FLAGS_PREMTABLE (1 << 2) /* Req can be pre-empted by PREMT_CURTS req */ 567 #define WL_MSCH_REQ_FLAGS_PREMT_CURTS (1 << 3) /* Pre-empt request at the end of curts */ 568 #define WL_MSCH_REQ_FLAGS_PREMT_IMMEDIATE (1 << 4) /* Pre-empt cur_ts immediately */ 569 570 /* Requested slot Callback states 571 * req->pend_slot/cur_slot->flags 572 */ 573 #define WL_MSCH_RC_FLAGS_ONCHAN_FIRE (1 << 0) 574 #define WL_MSCH_RC_FLAGS_START_FIRE_DONE (1 << 1) 575 #define WL_MSCH_RC_FLAGS_END_FIRE_DONE (1 << 2) 576 #define WL_MSCH_RC_FLAGS_ONFIRE_DONE (1 << 3) 577 #define WL_MSCH_RC_FLAGS_SPLIT_SLOT_START (1 << 4) 578 #define WL_MSCH_RC_FLAGS_SPLIT_SLOT_END (1 << 5) 579 #define WL_MSCH_RC_FLAGS_PRE_ONFIRE_DONE (1 << 6) 580 581 /* Request entity flags */ 582 #define WL_MSCH_ENTITY_FLAG_MULTI_INSTANCE (1 << 0) 583 584 /* Request Handle flags */ 585 #define WL_MSCH_REQ_HDL_FLAGS_NEW_REQ (1 << 0) /* req_start callback */ 586 587 /* MSCH state flags (msch_info->flags) */ 588 #define WL_MSCH_STATE_IN_TIEMR_CTXT 0x1 589 #define WL_MSCH_STATE_SCHD_PENDING 0x2 590 591 /* MSCH callback type */ 592 #define WL_MSCH_CT_REQ_START 0x1 593 #define WL_MSCH_CT_ON_CHAN 0x2 594 #define WL_MSCH_CT_SLOT_START 0x4 595 #define WL_MSCH_CT_SLOT_END 0x8 596 #define WL_MSCH_CT_SLOT_SKIP 0x10 597 #define WL_MSCH_CT_OFF_CHAN 0x20 598 #define WL_MSCH_CT_OFF_CHAN_DONE 0x40 599 #define WL_MSCH_CT_REQ_END 0x80 600 #define WL_MSCH_CT_PARTIAL 0x100 601 #define WL_MSCH_CT_PRE_ONCHAN 0x200 602 #define WL_MSCH_CT_PRE_REQ_START 0x400 603 604 /* MSCH command bits */ 605 #define WL_MSCH_CMD_ENABLE_BIT 0x01 606 #define WL_MSCH_CMD_PROFILE_BIT 0x02 607 #define WL_MSCH_CMD_CALLBACK_BIT 0x04 608 #define WL_MSCH_CMD_REGISTER_BIT 0x08 609 #define WL_MSCH_CMD_ERROR_BIT 0x10 610 #define WL_MSCH_CMD_DEBUG_BIT 0x20 611 #define WL_MSCH_CMD_INFOM_BIT 0x40 612 #define WL_MSCH_CMD_TRACE_BIT 0x80 613 #define WL_MSCH_CMD_ALL_BITS 0xfe 614 #define WL_MSCH_CMD_SIZE_MASK 0x00ff0000 615 #define WL_MSCH_CMD_SIZE_SHIFT 16 616 #define WL_MSCH_CMD_VER_MASK 0xff000000 617 #define WL_MSCH_CMD_VER_SHIFT 24 618 619 /* maximum channels returned by the get valid channels iovar */ 620 #define WL_MSCH_NUMCHANNELS 64 621 622 typedef struct msch_collect_tlv { 623 uint16 type; 624 uint16 size; 625 char value[1]; 626 } msch_collect_tlv_t; 627 628 typedef struct msch_profiler_event_data { 629 uint32 time_lo; /* Request time */ 630 uint32 time_hi; 631 } msch_profiler_event_data_t; 632 633 typedef struct msch_start_profiler_event_data { 634 uint32 time_lo; /* Request time */ 635 uint32 time_hi; 636 uint32 status; 637 } msch_start_profiler_event_data_t; 638 639 typedef struct msch_message_profiler_event_data { 640 uint32 time_lo; /* Request time */ 641 uint32 time_hi; 642 char message[1]; /* message */ 643 } msch_message_profiler_event_data_t; 644 645 typedef struct msch_event_log_profiler_event_data { 646 uint32 time_lo; /* Request time */ 647 uint32 time_hi; 648 event_log_hdr_t hdr; /* event log header */ 649 uint32 data[9]; /* event data */ 650 } msch_event_log_profiler_event_data_t; 651 652 typedef struct msch_req_param_profiler_event_data { 653 uint16 flags; /* Describe various request properties */ 654 uint8 req_type; /* Describe start and end time flexiblilty */ 655 uint8 priority; /* Define the request priority */ 656 uint32 start_time_l; /* Requested start time offset in us unit */ 657 uint32 start_time_h; 658 uint32 duration; /* Requested duration in us unit */ 659 uint32 interval; /* Requested periodic interval in us unit, 660 * 0 means non-periodic 661 */ 662 union { 663 uint32 dur_flex; /* MSCH_REG_DUR_FLEX, min_dur = duration - dur_flex */ 664 struct { 665 uint32 min_dur; /* min duration for traffic, maps to home_time */ 666 uint32 max_away_dur; /* max acceptable away dur, maps to home_away_time */ 667 uint32 hi_prio_time_l; 668 uint32 hi_prio_time_h; 669 uint32 hi_prio_interval; /* repeated high priority interval */ 670 } bf; 671 } flex; 672 } msch_req_param_profiler_event_data_t; 673 674 typedef struct msch_req_timing_profiler_event_data { 675 uint32 p_req_timing; 676 uint32 p_prev; 677 uint32 p_next; 678 uint16 flags; 679 uint16 timeslot_ptr; 680 uint32 fire_time_l; 681 uint32 fire_time_h; 682 uint32 pre_start_time_l; 683 uint32 pre_start_time_h; 684 uint32 start_time_l; 685 uint32 start_time_h; 686 uint32 end_time_l; 687 uint32 end_time_h; 688 uint32 p_timeslot; 689 } msch_req_timing_profiler_event_data_t; 690 691 typedef struct msch_chan_ctxt_profiler_event_data { 692 uint32 p_chan_ctxt; 693 uint32 p_prev; 694 uint32 p_next; 695 uint16 chanspec; 696 uint16 bf_sch_pending; 697 uint32 bf_link_prev; 698 uint32 bf_link_next; 699 uint32 onchan_time_l; 700 uint32 onchan_time_h; 701 uint32 actual_onchan_dur_l; 702 uint32 actual_onchan_dur_h; 703 uint32 pend_onchan_dur_l; 704 uint32 pend_onchan_dur_h; 705 uint16 req_entity_list_cnt; 706 uint16 req_entity_list_ptr; 707 uint16 bf_entity_list_cnt; 708 uint16 bf_entity_list_ptr; 709 uint32 bf_skipped_count; 710 } msch_chan_ctxt_profiler_event_data_t; 711 712 typedef struct msch_req_entity_profiler_event_data { 713 uint32 p_req_entity; 714 uint32 req_hdl_link_prev; 715 uint32 req_hdl_link_next; 716 uint32 chan_ctxt_link_prev; 717 uint32 chan_ctxt_link_next; 718 uint32 rt_specific_link_prev; 719 uint32 rt_specific_link_next; 720 uint32 start_fixed_link_prev; 721 uint32 start_fixed_link_next; 722 uint32 both_flex_list_prev; 723 uint32 both_flex_list_next; 724 uint16 chanspec; 725 uint16 priority; 726 uint16 cur_slot_ptr; 727 uint16 pend_slot_ptr; 728 uint16 pad; 729 uint16 chan_ctxt_ptr; 730 uint32 p_chan_ctxt; 731 uint32 p_req_hdl; 732 uint32 bf_last_serv_time_l; 733 uint32 bf_last_serv_time_h; 734 uint16 onchan_chn_idx; 735 uint16 cur_chn_idx; 736 uint32 flags; 737 uint32 actual_start_time_l; 738 uint32 actual_start_time_h; 739 uint32 curts_fire_time_l; 740 uint32 curts_fire_time_h; 741 } msch_req_entity_profiler_event_data_t; 742 743 typedef struct msch_req_handle_profiler_event_data { 744 uint32 p_req_handle; 745 uint32 p_prev; 746 uint32 p_next; 747 uint32 cb_func; 748 uint32 cb_ctxt; 749 uint16 req_param_ptr; 750 uint16 req_entity_list_cnt; 751 uint16 req_entity_list_ptr; 752 uint16 chan_cnt; 753 uint32 flags; 754 uint16 chanspec_list; 755 uint16 chanspec_cnt; 756 uint16 chan_idx; 757 uint16 last_chan_idx; 758 uint32 req_time_l; 759 uint32 req_time_h; 760 } msch_req_handle_profiler_event_data_t; 761 762 typedef struct msch_profiler_profiler_event_data { 763 uint32 time_lo; /* Request time */ 764 uint32 time_hi; 765 uint32 free_req_hdl_list; 766 uint32 free_req_entity_list; 767 uint32 free_chan_ctxt_list; 768 uint32 free_chanspec_list; 769 uint16 cur_msch_timeslot_ptr; 770 uint16 next_timeslot_ptr; 771 uint32 p_cur_msch_timeslot; 772 uint32 p_next_timeslot; 773 uint32 cur_armed_timeslot; 774 uint32 flags; 775 uint32 ts_id; 776 uint32 service_interval; 777 uint32 max_lo_prio_interval; 778 uint16 flex_list_cnt; 779 uint16 msch_chanspec_alloc_cnt; 780 uint16 msch_req_entity_alloc_cnt; 781 uint16 msch_req_hdl_alloc_cnt; 782 uint16 msch_chan_ctxt_alloc_cnt; 783 uint16 msch_timeslot_alloc_cnt; 784 uint16 msch_req_hdl_list_cnt; 785 uint16 msch_req_hdl_list_ptr; 786 uint16 msch_chan_ctxt_list_cnt; 787 uint16 msch_chan_ctxt_list_ptr; 788 uint16 msch_req_timing_list_cnt; 789 uint16 msch_req_timing_list_ptr; 790 uint16 msch_start_fixed_list_cnt; 791 uint16 msch_start_fixed_list_ptr; 792 uint16 msch_both_flex_req_entity_list_cnt; 793 uint16 msch_both_flex_req_entity_list_ptr; 794 uint16 msch_start_flex_list_cnt; 795 uint16 msch_start_flex_list_ptr; 796 uint16 msch_both_flex_list_cnt; 797 uint16 msch_both_flex_list_ptr; 798 uint32 slotskip_flag; 799 } msch_profiler_profiler_event_data_t; 800 801 typedef struct msch_req_profiler_event_data { 802 uint32 time_lo; /* Request time */ 803 uint32 time_hi; 804 uint16 chanspec_cnt; 805 uint16 chanspec_ptr; 806 uint16 req_param_ptr; 807 uint16 pad; 808 } msch_req_profiler_event_data_t; 809 810 typedef struct msch_callback_profiler_event_data { 811 uint32 time_lo; /* Request time */ 812 uint32 time_hi; 813 uint16 type; /* callback type */ 814 uint16 chanspec; /* actual chanspec, may different with requested one */ 815 uint32 start_time_l; /* time slot start time low 32bit */ 816 uint32 start_time_h; /* time slot start time high 32bit */ 817 uint32 end_time_l; /* time slot end time low 32 bit */ 818 uint32 end_time_h; /* time slot end time high 32 bit */ 819 uint32 timeslot_id; /* unique time slot id */ 820 uint32 p_req_hdl; 821 uint32 onchan_idx; /* Current channel index */ 822 uint32 cur_chan_seq_start_time_l; /* start time of current sequence */ 823 uint32 cur_chan_seq_start_time_h; 824 } msch_callback_profiler_event_data_t; 825 826 typedef struct msch_timeslot_profiler_event_data { 827 uint32 p_timeslot; 828 uint32 timeslot_id; 829 uint32 pre_start_time_l; 830 uint32 pre_start_time_h; 831 uint32 end_time_l; 832 uint32 end_time_h; 833 uint32 sch_dur_l; 834 uint32 sch_dur_h; 835 uint32 p_chan_ctxt; 836 uint32 fire_time_l; 837 uint32 fire_time_h; 838 uint32 state; 839 } msch_timeslot_profiler_event_data_t; 840 841 typedef struct msch_register_params { 842 uint16 wlc_index; /* Optional wlc index */ 843 uint16 flags; /* Describe various request properties */ 844 uint32 req_type; /* Describe start and end time flexiblilty */ 845 uint16 id; /* register id */ 846 uint16 priority; /* Define the request priority */ 847 uint32 start_time; /* Requested start time offset in ms unit */ 848 uint32 duration; /* Requested duration in ms unit */ 849 uint32 interval; /* Requested periodic interval in ms unit, 850 * 0 means non-periodic 851 */ 852 uint32 dur_flex; /* MSCH_REG_DUR_FLEX, min_dur = duration - dur_flex */ 853 uint32 min_dur; /* min duration for traffic, maps to home_time */ 854 uint32 max_away_dur; /* max acceptable away dur, maps to home_away_time */ 855 uint32 hi_prio_time; 856 uint32 hi_prio_interval; /* repeated high priority interval */ 857 uint32 chanspec_cnt; 858 uint16 chanspec_list[WL_MSCH_NUMCHANNELS]; 859 } msch_register_params_t; 860 861 typedef struct { 862 uint32 txallfrm; /**< total number of frames sent, incl. Data, ACK, RTS, CTS, 863 * Control Management (includes retransmissions) 864 */ 865 uint32 rxrsptmout; /**< number of response timeouts for transmitted frames 866 * expecting a response 867 */ 868 uint32 rxstrt; /**< number of received frames with a good PLCP */ 869 uint32 rxbadplcp; /**< number of parity check of the PLCP header failed */ 870 uint32 rxcrsglitch; /**< PHY was able to correlate the preamble but not the header */ 871 uint32 rxnodelim; /**< number of no valid delimiter detected by ampdu parser */ 872 uint32 bphy_badplcp; /**< number of bad PLCP reception on BPHY rate */ 873 uint32 bphy_rxcrsglitch; /**< PHY count of bphy glitches */ 874 uint32 rxbadfcs; /**< number of frames for which the CRC check failed in the MAC */ 875 uint32 rxanyerr; /**< Any RX error that is not counted by other counters. */ 876 uint32 rxbeaconmbss; /**< beacons received from member of BSS */ 877 uint32 rxdtucastmbss; /**< number of received DATA frames with good FCS and matching RA */ 878 uint32 rxdtocast; /**< number of received DATA frames (good FCS and no matching RA) */ 879 uint32 rxtoolate; /**< receive too late */ 880 uint32 goodfcs; /**< Good fcs counters */ 881 uint32 rxf0ovfl; /** < Rx FIFO0 overflow counters information */ 882 uint32 rxf1ovfl; /** < Rx FIFO1 overflow counters information */ 883 } phy_periodic_counters_v1_t; 884 885 typedef struct { 886 887 /* RX error related */ 888 uint32 rxrsptmout; /* number of response timeouts for transmitted frames 889 * expecting a response 890 */ 891 uint32 rxbadplcp; /* number of parity check of the PLCP header failed */ 892 uint32 rxcrsglitch; /* PHY was able to correlate the preamble but not the header */ 893 uint32 rxnodelim; /* number of no valid delimiter detected by ampdu parser */ 894 uint32 bphy_badplcp; /* number of bad PLCP reception on BPHY rate */ 895 uint32 bphy_rxcrsglitch; /* PHY count of bphy glitches */ 896 uint32 rxbadfcs; /* number of frames for which the CRC check failed in the MAC */ 897 uint32 rxtoolate; /* receive too late */ 898 uint32 rxf0ovfl; /* Rx FIFO0 overflow counters information */ 899 uint32 rxf1ovfl; /* Rx FIFO1 overflow counters information */ 900 uint32 rxanyerr; /* Any RX error that is not counted by other counters. */ 901 uint32 rxdropped; /* Frame dropped */ 902 uint32 rxnobuf; /* Rx error due to no buffer */ 903 uint32 rxrunt; /* Runt frame counter */ 904 uint32 rxfrmtoolong; /* Number of received frame that are too long */ 905 uint32 rxdrop20s; 906 907 /* RX related */ 908 uint32 rxstrt; /* number of received frames with a good PLCP */ 909 uint32 rxbeaconmbss; /* beacons received from member of BSS */ 910 uint32 rxdtucastmbss; /* number of received DATA frames with good FCS and matching RA */ 911 uint32 rxdtocast; /* number of received DATA frames (good FCS and no matching RA) */ 912 uint32 goodfcs; /* Good fcs counters */ 913 uint32 rxctl; /* Number of control frames */ 914 uint32 rxaction; /* Number of action frames */ 915 uint32 rxback; /* Number of block ack frames rcvd */ 916 uint32 rxctlucast; /* Number of received unicast ctl frames */ 917 uint32 rxframe; /* Number of received frames */ 918 919 /* TX related */ 920 uint32 txallfrm; /* total number of frames sent, incl. Data, ACK, RTS, CTS, 921 * Control Management (includes retransmissions) 922 */ 923 uint32 txmpdu; /* Numer of transmitted mpdus */ 924 uint32 txackbackctsfrm; /* Number of ACK + BACK + CTS */ 925 926 /* TX error related */ 927 uint32 txrtsfail; /* RTS TX failure count */ 928 uint32 txphyerr; /* PHY TX error count */ 929 930 uint16 nav_cntr_l; /* The state of the NAV */ 931 uint16 nav_cntr_h; 932 } phy_periodic_counters_v3_t; 933 934 typedef struct phy_periodic_counters_v4 { 935 uint32 txallfrm; /**< total number of frames sent, incl. Data, ACK, RTS, CTS, 936 * Control Management (includes retransmissions) 937 */ 938 uint32 rxrsptmout; /**< number of response timeouts for transmitted frames 939 * expecting a response 940 */ 941 uint32 rxstrt; /**< number of received frames with a good PLCP */ 942 uint32 rxbadplcp; /**< number of parity check of the PLCP header failed */ 943 uint32 rxcrsglitch; /**< PHY was able to correlate the preamble but not the header */ 944 uint32 bphy_badplcp; /**< number of bad PLCP reception on BPHY rate */ 945 uint32 bphy_rxcrsglitch; /**< PHY count of bphy glitches */ 946 uint32 rxbeaconmbss; /**< beacons received from member of BSS */ 947 uint32 rxdtucastmbss; /**< number of received DATA frames with good FCS and matching RA */ 948 uint32 rxf0ovfl; /** < Rx FIFO0 overflow counters information */ 949 uint32 rxf1ovfl; /** < Rx FIFO1 overflow counters information */ 950 uint32 rxdtocast; /**< number of received DATA frames (good FCS and no matching RA) */ 951 uint32 rxtoolate; /**< receive too late */ 952 uint32 rxbadfcs; /**< number of frames for which the CRC check failed in the MAC */ 953 uint32 rxdropped; 954 uint32 rxcrc; 955 uint32 rxnobuf; 956 uint32 rxrunt; 957 uint32 rxgiant; 958 uint32 rxctl; 959 uint32 rxaction; 960 uint32 rxdrop20s; 961 uint32 rxctsucast; 962 uint32 rxrtsucast; 963 uint32 txctsfrm; 964 uint32 rxackucast; 965 uint32 rxback; 966 uint32 txphyerr; 967 uint32 txrtsfrm; 968 uint32 txackfrm; 969 uint32 txback; 970 uint32 rxnodelim; 971 uint32 rxfrmtoolong; 972 uint32 rxctlucast; 973 uint32 txbcnfrm; 974 uint32 txdnlfrm; 975 uint32 txampdu; 976 uint32 txmpdu; 977 uint32 txinrtstxop; 978 uint32 prs_timeout; 979 } phy_periodic_counters_v4_t; 980 981 typedef struct phycal_log_cmn { 982 uint16 chanspec; /* Current phy chanspec */ 983 uint8 last_cal_reason; /* Last Cal Reason */ 984 uint8 pad1; /* Padding byte to align with word */ 985 uint32 last_cal_time; /* Last cal time in sec */ 986 } phycal_log_cmn_t; 987 988 typedef struct phycal_log_cmn_v2 { 989 uint16 chanspec; /* current phy chanspec */ 990 uint8 reason; /* cal reason */ 991 uint8 phase; /* cal phase */ 992 uint32 time; /* time at which cal happened in sec */ 993 uint16 temp; /* temperature at the time of cal */ 994 uint16 dur; /* duration of cal in usec */ 995 996 /* Misc general purpose debug counters (will be used for future debugging) */ 997 uint16 debug_01; 998 uint16 debug_02; 999 uint16 debug_03; 1000 uint16 debug_04; 1001 } phycal_log_cmn_v2_t; 1002 1003 typedef struct phycal_log_core { 1004 uint16 ofdm_txa; /* OFDM Tx IQ Cal a coeff */ 1005 uint16 ofdm_txb; /* OFDM Tx IQ Cal b coeff */ 1006 uint16 ofdm_txd; /* contain di & dq */ 1007 uint16 bphy_txa; /* BPHY Tx IQ Cal a coeff */ 1008 uint16 bphy_txb; /* BPHY Tx IQ Cal b coeff */ 1009 uint16 bphy_txd; /* contain di & dq */ 1010 1011 uint16 rxa; /* Rx IQ Cal A coeffecient */ 1012 uint16 rxb; /* Rx IQ Cal B coeffecient */ 1013 int32 rxs; /* FDIQ Slope coeffecient */ 1014 1015 uint8 baseidx; /* TPC Base index */ 1016 uint8 adc_coeff_cap0_adcI; /* ADC CAP Cal Cap0 I */ 1017 uint8 adc_coeff_cap1_adcI; /* ADC CAP Cal Cap1 I */ 1018 uint8 adc_coeff_cap2_adcI; /* ADC CAP Cal Cap2 I */ 1019 uint8 adc_coeff_cap0_adcQ; /* ADC CAP Cal Cap0 Q */ 1020 uint8 adc_coeff_cap1_adcQ; /* ADC CAP Cal Cap1 Q */ 1021 uint8 adc_coeff_cap2_adcQ; /* ADC CAP Cal Cap2 Q */ 1022 uint8 pad; /* Padding byte to align with word */ 1023 } phycal_log_core_t; 1024 1025 typedef struct phycal_log_core_v3 { 1026 uint16 ofdm_txa; /* OFDM Tx IQ Cal a coeff */ 1027 uint16 ofdm_txb; /* OFDM Tx IQ Cal b coeff */ 1028 uint16 ofdm_txd; /* contain di & dq */ 1029 uint16 bphy_txa; /* BPHY Tx IQ Cal a coeff */ 1030 uint16 bphy_txb; /* BPHY Tx IQ Cal b coeff */ 1031 uint16 bphy_txd; /* contain di & dq */ 1032 1033 uint16 rxa; /* Rx IQ Cal A coeffecient */ 1034 uint16 rxb; /* Rx IQ Cal B coeffecient */ 1035 int32 rxs; /* FDIQ Slope coeffecient */ 1036 1037 uint8 baseidx; /* TPC Base index */ 1038 uint8 adc_coeff_cap0_adcI; /* ADC CAP Cal Cap0 I */ 1039 uint8 adc_coeff_cap1_adcI; /* ADC CAP Cal Cap1 I */ 1040 uint8 adc_coeff_cap2_adcI; /* ADC CAP Cal Cap2 I */ 1041 uint8 adc_coeff_cap0_adcQ; /* ADC CAP Cal Cap0 Q */ 1042 uint8 adc_coeff_cap1_adcQ; /* ADC CAP Cal Cap1 Q */ 1043 uint8 adc_coeff_cap2_adcQ; /* ADC CAP Cal Cap2 Q */ 1044 uint8 pad; /* Padding byte to align with word */ 1045 1046 /* Gain index based txiq ceffiecients for 2G(3 gain indices) */ 1047 uint16 txiqlo_2g_a0; /* 2G TXIQ Cal a coeff for high TX gain */ 1048 uint16 txiqlo_2g_b0; /* 2G TXIQ Cal b coeff for high TX gain */ 1049 uint16 txiqlo_2g_a1; /* 2G TXIQ Cal a coeff for mid TX gain */ 1050 uint16 txiqlo_2g_b1; /* 2G TXIQ Cal b coeff for mid TX gain */ 1051 uint16 txiqlo_2g_a2; /* 2G TXIQ Cal a coeff for low TX gain */ 1052 uint16 txiqlo_2g_b2; /* 2G TXIQ Cal b coeff for low TX gain */ 1053 1054 uint16 rxa_vpoff; /* Rx IQ Cal A coeff Vp off */ 1055 uint16 rxb_vpoff; /* Rx IQ Cal B coeff Vp off */ 1056 uint16 rxa_ipoff; /* Rx IQ Cal A coeff Ip off */ 1057 uint16 rxb_ipoff; /* Rx IQ Cal B coeff Ip off */ 1058 int32 rxs_vpoff; /* FDIQ Slope coeff Vp off */ 1059 int32 rxs_ipoff; /* FDIQ Slope coeff Ip off */ 1060 } phycal_log_core_v3_t; 1061 1062 #define PHYCAL_LOG_VER1 (1u) 1063 1064 typedef struct phycal_log_v1 { 1065 uint8 version; /* Logging structure version */ 1066 uint8 numcores; /* Numbe of cores for which core specific data present */ 1067 uint16 length; /* Length of the entire structure */ 1068 phycal_log_cmn_t phycal_log_cmn; /* Logging common structure */ 1069 /* This will be a variable length based on the numcores field defined above */ 1070 phycal_log_core_t phycal_log_core[1]; 1071 } phycal_log_v1_t; 1072 1073 typedef struct phy_periodic_log_cmn { 1074 uint16 chanspec; /* Current phy chanspec */ 1075 uint16 vbatmeas; /* Measured VBAT sense value */ 1076 uint16 featureflag; /* Currently active feature flags */ 1077 int8 chiptemp; /* Chip temparature */ 1078 int8 femtemp; /* Fem temparature */ 1079 1080 uint32 nrate; /* Current Tx nrate */ 1081 1082 uint8 cal_phase_id; /* Current Multi phase cal ID */ 1083 uint8 rxchain; /* Rx Chain */ 1084 uint8 txchain; /* Tx Chain */ 1085 uint8 ofdm_desense; /* OFDM desense */ 1086 1087 uint8 bphy_desense; /* BPHY desense */ 1088 uint8 pll_lockstatus; /* PLL Lock status */ 1089 uint8 pad1; /* Padding byte to align with word */ 1090 uint8 pad2; /* Padding byte to align with word */ 1091 1092 uint32 duration; /**< millisecs spent sampling this channel */ 1093 uint32 congest_ibss; /**< millisecs in our bss (presumably this traffic will */ 1094 /**< move if cur bss moves channels) */ 1095 uint32 congest_obss; /**< traffic not in our bss */ 1096 uint32 interference; /**< millisecs detecting a non 802.11 interferer. */ 1097 1098 } phy_periodic_log_cmn_t; 1099 1100 typedef struct phy_periodic_log_cmn_v2 { 1101 uint16 chanspec; /* Current phy chanspec */ 1102 uint16 vbatmeas; /* Measured VBAT sense value */ 1103 uint16 featureflag; /* Currently active feature flags */ 1104 int8 chiptemp; /* Chip temparature */ 1105 int8 femtemp; /* Fem temparature */ 1106 1107 uint32 nrate; /* Current Tx nrate */ 1108 1109 uint8 cal_phase_id; /* Current Multi phase cal ID */ 1110 uint8 rxchain; /* Rx Chain */ 1111 uint8 txchain; /* Tx Chain */ 1112 uint8 ofdm_desense; /* OFDM desense */ 1113 1114 uint8 bphy_desense; /* BPHY desense */ 1115 uint8 pll_lockstatus; /* PLL Lock status */ 1116 1117 uint32 duration; /* millisecs spent sampling this channel */ 1118 uint32 congest_ibss; /* millisecs in our bss (presumably this traffic will */ 1119 /* move if cur bss moves channels) */ 1120 uint32 congest_obss; /* traffic not in our bss */ 1121 uint32 interference; /* millisecs detecting a non 802.11 interferer. */ 1122 1123 uint8 slice; 1124 uint8 version; /* version of fw/ucode for debug purposes */ 1125 bool phycal_disable; /* Set if calibration is disabled */ 1126 uint8 pad; 1127 uint16 phy_log_counter; 1128 uint16 noise_mmt_overdue; /* Count up if ucode noise mmt is overdue for 5 sec */ 1129 uint16 chan_switch_tm; /* Channel switch time */ 1130 1131 /* HP2P related params */ 1132 uint16 shm_mpif_cnt_val; 1133 uint16 shm_thld_cnt_val; 1134 uint16 shm_nav_cnt_val; 1135 uint16 shm_cts_cnt_val; 1136 1137 uint16 shm_m_prewds_cnt; /* Count of pre-wds fired in the ucode */ 1138 uint32 last_cal_time; /* Last cal execution time */ 1139 uint16 deaf_count; /* Depth of stay_in_carrier_search function */ 1140 uint32 ed20_crs0; /* ED-CRS status on core 0 */ 1141 uint32 ed20_crs1; /* ED-CRS status on core 1 */ 1142 uint32 noise_cal_req_ts; /* Time-stamp when noise cal was requested */ 1143 uint32 noise_cal_intr_ts; /* Time-stamp when noise cal was completed */ 1144 uint32 phywdg_ts; /* Time-stamp when wd was fired */ 1145 uint32 phywd_dur; /* Duration of the watchdog */ 1146 uint32 noise_mmt_abort_crs; /* Count of CRS during noise mmt */ 1147 uint32 chanspec_set_ts; /* Time-stamp when chanspec was set */ 1148 uint32 vcopll_failure_cnt; /* Number of VCO cal failures 1149 * (including failures detected in ucode). 1150 */ 1151 uint32 dcc_fail_counter; /* Number of DC cal failures */ 1152 uint32 log_ts; /* Time-stamp when this log was collected */ 1153 1154 uint16 btcxovrd_dur; /* Cumulative btcx overide between WDGs */ 1155 uint16 btcxovrd_err_cnt; /* BTCX override flagged errors */ 1156 1157 uint16 femtemp_read_fail_counter; /* Fem temparature read fail counter */ 1158 /* Misc general purpose debug counters (will be used for future debugging) */ 1159 uint16 debug_01; 1160 uint16 debug_02; 1161 } phy_periodic_log_cmn_v2_t; 1162 1163 typedef struct phy_periodic_log_cmn_v3 { 1164 uint32 nrate; /* Current Tx nrate */ 1165 uint32 duration; /**< millisecs spent sampling this channel */ 1166 uint32 congest_ibss; /**< millisecs in our bss (presumably this traffic will */ 1167 /**< move if cur bss moves channels) */ 1168 uint32 congest_obss; /**< traffic not in our bss */ 1169 uint32 interference; /**< millisecs detecting a non 802.11 interferer. */ 1170 uint32 noise_cfg_exit1; 1171 uint32 noise_cfg_exit2; 1172 uint32 noise_cfg_exit3; 1173 uint32 noise_cfg_exit4; 1174 uint32 ed20_crs0; 1175 uint32 ed20_crs1; 1176 uint32 noise_cal_req_ts; 1177 uint32 noise_cal_crs_ts; 1178 uint32 log_ts; 1179 uint32 last_cal_time; 1180 uint32 phywdg_ts; 1181 uint32 chanspec_set_ts; 1182 uint32 noise_zero_inucode; 1183 uint32 phy_crs_during_noisemmt; 1184 uint32 wd_dur; 1185 1186 int32 deaf_count; 1187 1188 uint16 chanspec; /* Current phy chanspec */ 1189 uint16 vbatmeas; /* Measured VBAT sense value */ 1190 uint16 featureflag; /* Currently active feature flags */ 1191 uint16 nav_cntr_l; 1192 uint16 nav_cntr_h; 1193 uint16 chanspec_set_last; 1194 uint16 ucode_noise_fb_overdue; 1195 uint16 phy_log_counter; 1196 uint16 shm_mpif_cnt_val; 1197 uint16 shm_thld_cnt_val; 1198 uint16 shm_nav_cnt_val; 1199 uint16 shm_dc_cnt_val; 1200 uint16 shm_txff_cnt_val; 1201 uint16 shm_cts_cnt_val; 1202 uint16 shm_m_prewds_cnt; 1203 1204 uint8 cal_phase_id; /* Current Multi phase cal ID */ 1205 uint8 rxchain; /* Rx Chain */ 1206 uint8 txchain; /* Tx Chain */ 1207 uint8 ofdm_desense; /* OFDM desense */ 1208 uint8 bphy_desense; /* BPHY desense */ 1209 uint8 pll_lockstatus; /* PLL Lock status */ 1210 int8 chiptemp; /* Chip temparature */ 1211 int8 femtemp; /* Fem temparature */ 1212 1213 bool phycal_disable; 1214 uint8 pad; /* Padding byte to align with word */ 1215 } phy_periodic_log_cmn_v3_t; 1216 1217 typedef struct phy_periodic_log_cmn_v4 { 1218 uint16 chanspec; /* Current phy chanspec */ 1219 uint16 vbatmeas; /* Measured VBAT sense value */ 1220 1221 uint16 featureflag; /* Currently active feature flags */ 1222 int8 chiptemp; /* Chip temparature */ 1223 int8 femtemp; /* Fem temparature */ 1224 1225 uint32 nrate; /* Current Tx nrate */ 1226 1227 uint8 cal_phase_id; /* Current Multi phase cal ID */ 1228 uint8 rxchain; /* Rx Chain */ 1229 uint8 txchain; /* Tx Chain */ 1230 uint8 ofdm_desense; /* OFDM desense */ 1231 1232 uint8 slice; 1233 uint8 dbgfw_ver; /* version of fw/ucode for debug purposes */ 1234 uint8 bphy_desense; /* BPHY desense */ 1235 uint8 pll_lockstatus; /* PLL Lock status */ 1236 1237 uint32 duration; /* millisecs spent sampling this channel */ 1238 uint32 congest_ibss; /* millisecs in our bss (presumably this traffic will */ 1239 /* move if cur bss moves channels) */ 1240 uint32 congest_obss; /* traffic not in our bss */ 1241 uint32 interference; /* millisecs detecting a non 802.11 interferer. */ 1242 1243 /* HP2P related params */ 1244 uint16 shm_mpif_cnt_val; 1245 uint16 shm_thld_cnt_val; 1246 uint16 shm_nav_cnt_val; 1247 uint16 shm_cts_cnt_val; 1248 1249 uint16 shm_m_prewds_cnt; /* Count of pre-wds fired in the ucode */ 1250 uint16 deaf_count; /* Depth of stay_in_carrier_search function */ 1251 uint32 last_cal_time; /* Last cal execution time */ 1252 uint32 ed20_crs0; /* ED-CRS status on core 0 */ 1253 uint32 ed20_crs1; /* ED-CRS status on core 1 */ 1254 uint32 noise_cal_req_ts; /* Time-stamp when noise cal was requested */ 1255 uint32 noise_cal_intr_ts; /* Time-stamp when noise cal was completed */ 1256 uint32 phywdg_ts; /* Time-stamp when wd was fired */ 1257 uint32 phywd_dur; /* Duration of the watchdog */ 1258 uint32 noise_mmt_abort_crs; /* Count of CRS during noise mmt */ 1259 uint32 chanspec_set_ts; /* Time-stamp when chanspec was set */ 1260 uint32 vcopll_failure_cnt; /* Number of VCO cal failures 1261 * (including failures detected in ucode). 1262 */ 1263 uint16 dcc_attempt_counter; /* Number of DC cal attempts */ 1264 uint16 dcc_fail_counter; /* Number of DC cal failures */ 1265 uint32 log_ts; /* Time-stamp when this log was collected */ 1266 1267 uint16 btcxovrd_dur; /* Cumulative btcx overide between WDGs */ 1268 uint16 btcxovrd_err_cnt; /* BTCX override flagged errors */ 1269 1270 uint16 femtemp_read_fail_counter; /* Fem temparature read fail counter */ 1271 uint16 phy_log_counter; 1272 uint16 noise_mmt_overdue; /* Count up if ucode noise mmt is overdue for 5 sec */ 1273 uint16 chan_switch_tm; /* Channel switch time */ 1274 1275 bool phycal_disable; /* Set if calibration is disabled */ 1276 1277 /* dccal dcoe & idacc */ 1278 uint8 dcc_err; /* dccal health check error status */ 1279 uint8 dcoe_num_tries; /* number of retries on dcoe cal */ 1280 uint8 idacc_num_tries; /* number of retries on idac cal */ 1281 1282 uint8 dccal_phyrxchain; /* phy rxchain during dc calibration */ 1283 uint8 dccal_type; /* DC cal type: single/multi phase, chan change, etc. */ 1284 uint16 dcc_hcfail; /* dcc health check failure count */ 1285 uint16 dcc_calfail; /* dcc failure count */ 1286 1287 /* Misc general purpose debug counters (will be used for future debugging) */ 1288 uint16 debug_01; 1289 uint16 debug_02; 1290 uint16 debug_03; 1291 uint16 debug_04; 1292 uint16 debug_05; 1293 } phy_periodic_log_cmn_v4_t; 1294 1295 typedef struct phy_periodic_log_core { 1296 uint8 baseindxval; /* TPC Base index */ 1297 int8 tgt_pwr; /* Programmed Target power */ 1298 int8 estpwradj; /* Current Est Power Adjust value */ 1299 int8 crsmin_pwr; /* CRS Min/Noise power */ 1300 int8 rssi_per_ant; /* RSSI Per antenna */ 1301 int8 snr_per_ant; /* SNR Per antenna */ 1302 int8 pad1; /* Padding byte to align with word */ 1303 int8 pad2; /* Padding byte to align with word */ 1304 } phy_periodic_log_core_t; 1305 1306 typedef struct phy_periodic_log_core_v3 { 1307 uint8 baseindxval; /* TPC Base index */ 1308 int8 tgt_pwr; /* Programmed Target power */ 1309 int8 estpwradj; /* Current Est Power Adjust value */ 1310 int8 crsmin_pwr; /* CRS Min/Noise power */ 1311 int8 rssi_per_ant; /* RSSI Per antenna */ 1312 int8 snr_per_ant; /* SNR Per antenna */ 1313 1314 /* dccal dcoe & idacc */ 1315 uint16 dcoe_done_0; /* dccal control register 44 */ 1316 uint16 dcoe_done_1; /* dccal control register 45 */ 1317 uint16 dcoe_done_2; /* dccal control register 46 */ 1318 uint16 idacc_done_0; /* dccal control register 21 */ 1319 uint16 idacc_done_1; /* dccal control register 60 */ 1320 uint16 idacc_done_2; /* dccal control register 61 */ 1321 int16 psb; /* psb read during dccal health check */ 1322 uint8 pktproc; /* pktproc read during dccal health check */ 1323 1324 int8 pad1; /* Padding byte to align with word */ 1325 int8 pad2; /* Padding byte to align with word */ 1326 int8 pad3; /* Padding byte to align with word */ 1327 } phy_periodic_log_core_v3_t; 1328 1329 typedef struct phy_periodic_log_core_v2 { 1330 int32 rxs; /* FDIQ Slope coeffecient */ 1331 1332 uint16 ofdm_txa; /* OFDM Tx IQ Cal a coeff */ 1333 uint16 ofdm_txb; /* OFDM Tx IQ Cal b coeff */ 1334 uint16 ofdm_txd; /* contain di & dq */ 1335 uint16 rxa; /* Rx IQ Cal A coeffecient */ 1336 uint16 rxb; /* Rx IQ Cal B coeffecient */ 1337 uint16 baseidx; /* TPC Base index */ 1338 1339 uint8 baseindxval; /* TPC Base index */ 1340 1341 int8 tgt_pwr; /* Programmed Target power */ 1342 int8 estpwradj; /* Current Est Power Adjust value */ 1343 int8 crsmin_pwr; /* CRS Min/Noise power */ 1344 int8 rssi_per_ant; /* RSSI Per antenna */ 1345 int8 snr_per_ant; /* SNR Per antenna */ 1346 int8 pad1; /* Padding byte to align with word */ 1347 int8 pad2; /* Padding byte to align with word */ 1348 } phy_periodic_log_core_v2_t; 1349 1350 #define PHY_PERIODIC_LOG_VER1 (1u) 1351 1352 typedef struct phy_periodic_log_v1 { 1353 uint8 version; /* Logging structure version */ 1354 uint8 numcores; /* Number of cores for which core specific data present */ 1355 uint16 length; /* Length of the entire structure */ 1356 phy_periodic_log_cmn_t phy_perilog_cmn; 1357 phy_periodic_counters_v1_t counters_peri_log; 1358 /* This will be a variable length based on the numcores field defined above */ 1359 phy_periodic_log_core_t phy_perilog_core[1]; 1360 } phy_periodic_log_v1_t; 1361 1362 #define PHYCAL_LOG_VER3 (3u) 1363 #define PHY_PERIODIC_LOG_VER3 (3u) 1364 1365 /* 4387 onwards */ 1366 typedef struct phy_periodic_log_v3 { 1367 uint8 version; /* Logging structure version */ 1368 uint8 numcores; /* Number of cores for which core specific data present */ 1369 uint16 length; /* Length of the structure */ 1370 1371 /* Logs general PHY parameters */ 1372 phy_periodic_log_cmn_v2_t phy_perilog_cmn; 1373 1374 /* Logs ucode counters and NAVs */ 1375 phy_periodic_counters_v3_t counters_peri_log; 1376 1377 /* Logs data pertaining to each core */ 1378 phy_periodic_log_core_t phy_perilog_core[1]; 1379 } phy_periodic_log_v3_t; 1380 1381 #define PHY_PERIODIC_LOG_VER5 (5u) 1382 1383 typedef struct phy_periodic_log_v5 { 1384 uint8 version; /* Logging structure version */ 1385 uint8 numcores; /* Number of cores for which core specific data present */ 1386 uint16 length; /* Length of the structure */ 1387 1388 /* Logs general PHY parameters */ 1389 phy_periodic_log_cmn_v4_t phy_perilog_cmn; 1390 1391 /* Logs ucode counters and NAVs */ 1392 phy_periodic_counters_v3_t counters_peri_log; 1393 1394 /* Logs data pertaining to each core */ 1395 phy_periodic_log_core_v3_t phy_perilog_core[1]; 1396 } phy_periodic_log_v5_t; 1397 1398 typedef struct phycal_log_v3 { 1399 uint8 version; /* Logging structure version */ 1400 uint8 numcores; /* Number of cores for which core specific data present */ 1401 uint16 length; /* Length of the entire structure */ 1402 phycal_log_cmn_v2_t phycal_log_cmn; /* Logging common structure */ 1403 /* This will be a variable length based on the numcores field defined above */ 1404 phycal_log_core_v3_t phycal_log_core[1]; 1405 } phycal_log_v3_t; 1406 1407 /* Note: The version 2 is reserved for 4357 only. Future chips must not use this version. */ 1408 1409 #define MAX_CORE_4357 (2u) 1410 #define PHYCAL_LOG_VER2 (2u) 1411 #define PHY_PERIODIC_LOG_VER2 (2u) 1412 1413 typedef struct { 1414 uint32 txallfrm; /**< total number of frames sent, incl. Data, ACK, RTS, CTS, 1415 * Control Management (includes retransmissions) 1416 */ 1417 uint32 rxrsptmout; /**< number of response timeouts for transmitted frames 1418 * expecting a response 1419 */ 1420 uint32 rxstrt; /**< number of received frames with a good PLCP */ 1421 uint32 rxbadplcp; /**< number of parity check of the PLCP header failed */ 1422 uint32 rxcrsglitch; /**< PHY was able to correlate the preamble but not the header */ 1423 uint32 bphy_badplcp; /**< number of bad PLCP reception on BPHY rate */ 1424 uint32 bphy_rxcrsglitch; /**< PHY count of bphy glitches */ 1425 uint32 rxbeaconmbss; /**< beacons received from member of BSS */ 1426 uint32 rxdtucastmbss; /**< number of received DATA frames with good FCS and matching RA */ 1427 uint32 rxf0ovfl; /** < Rx FIFO0 overflow counters information */ 1428 uint32 rxf1ovfl; /** < Rx FIFO1 overflow counters information */ 1429 uint32 rxdtocast; /**< number of received DATA frames (good FCS and no matching RA) */ 1430 uint32 rxtoolate; /**< receive too late */ 1431 uint32 rxbadfcs; /**< number of frames for which the CRC check failed in the MAC */ 1432 } phy_periodic_counters_v2_t; 1433 1434 /* Note: The version 2 is reserved for 4357 only. All future chips must not use this version. */ 1435 1436 typedef struct phycal_log_core_v2 { 1437 uint16 ofdm_txa; /* OFDM Tx IQ Cal a coeff */ 1438 uint16 ofdm_txb; /* OFDM Tx IQ Cal b coeff */ 1439 uint16 ofdm_txd; /* contain di & dq */ 1440 uint16 rxa; /* Rx IQ Cal A coeffecient */ 1441 uint16 rxb; /* Rx IQ Cal B coeffecient */ 1442 uint8 baseidx; /* TPC Base index */ 1443 uint8 pad; 1444 int32 rxs; /* FDIQ Slope coeffecient */ 1445 } phycal_log_core_v2_t; 1446 1447 /* Note: The version 2 is reserved for 4357 only. All future chips must not use this version. */ 1448 1449 typedef struct phycal_log_v2 { 1450 uint8 version; /* Logging structure version */ 1451 uint16 length; /* Length of the entire structure */ 1452 uint8 pad; 1453 phycal_log_cmn_t phycal_log_cmn; /* Logging common structure */ 1454 phycal_log_core_v2_t phycal_log_core[MAX_CORE_4357]; 1455 } phycal_log_v2_t; 1456 1457 /* Note: The version 2 is reserved for 4357 only. All future chips must not use this version. */ 1458 1459 typedef struct phy_periodic_log_v2 { 1460 uint8 version; /* Logging structure version */ 1461 uint16 length; /* Length of the entire structure */ 1462 uint8 pad; 1463 phy_periodic_log_cmn_t phy_perilog_cmn; 1464 phy_periodic_counters_v2_t counters_peri_log; 1465 phy_periodic_log_core_t phy_perilog_core[MAX_CORE_4357]; 1466 } phy_periodic_log_v2_t; 1467 1468 #define PHY_PERIODIC_LOG_VER4 (4u) 1469 1470 /* 1471 * Note: The version 4 is reserved for 4357 Deafness Debug only. 1472 * All future chips must not use this version. 1473 */ 1474 typedef struct phy_periodic_log_v4 { 1475 uint8 version; /* Logging structure version */ 1476 uint8 pad; 1477 uint16 length; /* Length of the entire structure */ 1478 phy_periodic_log_cmn_v3_t phy_perilog_cmn; 1479 phy_periodic_counters_v4_t counters_peri_log; 1480 phy_periodic_log_core_v2_t phy_perilog_core[MAX_CORE_4357]; 1481 } phy_periodic_log_v4_t; 1482 1483 /* Event log payload for enhanced roam log */ 1484 typedef enum { 1485 ROAM_LOG_SCANSTART = 1, /* EVT log for roam scan start */ 1486 ROAM_LOG_SCAN_CMPLT = 2, /* EVT log for roam scan completeted */ 1487 ROAM_LOG_ROAM_CMPLT = 3, /* EVT log for roam done */ 1488 ROAM_LOG_NBR_REQ = 4, /* EVT log for Neighbor REQ */ 1489 ROAM_LOG_NBR_REP = 5, /* EVT log for Neighbor REP */ 1490 ROAM_LOG_BCN_REQ = 6, /* EVT log for BCNRPT REQ */ 1491 ROAM_LOG_BCN_REP = 7, /* EVT log for BCNRPT REP */ 1492 ROAM_LOG_BTM_REP = 8, /* EVT log for BTM REP */ 1493 ROAM_LOG_WIPS_EVENT = 9, /* EVT log for WIPS Event */ 1494 PRSV_PERIODIC_ID_MAX 1495 } prsv_periodic_id_enum_t; 1496 1497 typedef struct prsv_periodic_log_hdr { 1498 uint8 version; 1499 uint8 id; 1500 uint16 length; 1501 } prsv_periodic_log_hdr_t; 1502 1503 #define ROAM_LOG_VER_1 (1u) 1504 #define ROAM_LOG_VER_2 (2u) 1505 #define ROAM_LOG_VER_3 (3u) 1506 #define ROAM_SSID_LEN (32u) 1507 typedef struct roam_log_trig_v1 { 1508 prsv_periodic_log_hdr_t hdr; 1509 int8 rssi; 1510 uint8 current_cu; 1511 uint8 pad[2]; 1512 uint reason; 1513 int result; 1514 union { 1515 struct { 1516 uint rcvd_reason; 1517 } prt_roam; 1518 struct { 1519 uint8 req_mode; 1520 uint8 token; 1521 uint16 nbrlist_size; 1522 uint32 disassoc_dur; 1523 uint32 validity_dur; 1524 uint32 bss_term_dur; 1525 } bss_trans; 1526 }; 1527 } roam_log_trig_v1_t; 1528 1529 typedef struct roam_log_trig_v2 { 1530 prsv_periodic_log_hdr_t hdr; 1531 int8 rssi; 1532 uint8 current_cu; 1533 uint8 full_scan; 1534 uint8 pad; 1535 uint reason; 1536 int result; 1537 union { 1538 struct { 1539 uint rcvd_reason; 1540 } prt_roam; 1541 struct { 1542 uint8 req_mode; 1543 uint8 token; 1544 uint16 nbrlist_size; 1545 uint32 disassoc_dur; 1546 uint32 validity_dur; 1547 uint32 bss_term_dur; 1548 } bss_trans; 1549 struct { 1550 int rssi_threshold; 1551 } low_rssi; 1552 }; 1553 } roam_log_trig_v2_t; 1554 1555 #define ROAM_LOG_RPT_SCAN_LIST_SIZE 3 1556 #define ROAM_LOG_INVALID_TPUT 0xFFFFFFFFu 1557 typedef struct roam_scan_ap_info { 1558 int8 rssi; 1559 uint8 cu; 1560 uint8 pad[2]; 1561 uint32 score; 1562 uint16 chanspec; 1563 struct ether_addr addr; 1564 uint32 estm_tput; 1565 } roam_scan_ap_info_t; 1566 1567 typedef struct roam_log_scan_cmplt_v1 { 1568 prsv_periodic_log_hdr_t hdr; 1569 uint8 full_scan; 1570 uint8 scan_count; 1571 uint8 scan_list_size; 1572 uint8 pad; 1573 int32 score_delta; 1574 roam_scan_ap_info_t cur_info; 1575 roam_scan_ap_info_t scan_list[ROAM_LOG_RPT_SCAN_LIST_SIZE]; 1576 } roam_log_scan_cmplt_v1_t; 1577 1578 #define ROAM_CHN_UNI_2A 36u 1579 #define ROAM_CHN_UNI_2A_MAX 64u 1580 #define ROAM_CHN_UNI_2C 100u 1581 #define ROAM_CHN_UNI_2C_MAX 144u 1582 #define ROAM_CHN_UNI_3 149u 1583 #define ROAM_CHN_UNI_3_MAX 165u 1584 #define ROAM_CHN_SPACE 2u /* channel index space for 5G */ 1585 1586 typedef struct roam_log_scan_cmplt_v2 { 1587 prsv_periodic_log_hdr_t hdr; 1588 uint8 scan_count; 1589 uint8 scan_list_size; 1590 uint8 chan_num; 1591 uint8 pad; 1592 uint16 band2g_chan_list; 1593 uint16 uni2a_chan_list; 1594 uint8 uni2c_chan_list[3]; 1595 uint8 uni3_chan_list; 1596 int32 score_delta; 1597 roam_scan_ap_info_t cur_info; 1598 roam_scan_ap_info_t scan_list[ROAM_LOG_RPT_SCAN_LIST_SIZE]; 1599 } roam_log_scan_cmplt_v2_t; 1600 1601 typedef struct roam_log_cmplt_v1 { 1602 prsv_periodic_log_hdr_t hdr; 1603 uint status; /* status code WLC_E STATUS */ 1604 uint reason; /* roam trigger reason */ 1605 uint16 chanspec; /* new bssid chansepc */ 1606 struct ether_addr addr; /* ether addr */ 1607 uint8 pad[3]; 1608 uint8 retry; 1609 } roam_log_cmplt_v1_t; 1610 1611 typedef roam_log_cmplt_v1_t roam_log_cmplt_v2_t; 1612 1613 typedef struct roam_log_nbrrep { 1614 prsv_periodic_log_hdr_t hdr; 1615 uint channel_num; 1616 } roam_log_nbrrep_v1_t; 1617 1618 typedef struct roam_log_nbrrep_v2 { 1619 prsv_periodic_log_hdr_t hdr; 1620 uint channel_num; 1621 uint16 band2g_chan_list; /* channel bit map */ 1622 uint16 uni2a_chan_list; 1623 uint8 uni2c_chan_list[3]; 1624 uint8 uni3_chan_list; 1625 } roam_log_nbrrep_v2_t; 1626 1627 typedef struct roam_log_nbrreq { 1628 prsv_periodic_log_hdr_t hdr; 1629 uint token; 1630 } roam_log_nbrreq_v1_t; 1631 1632 typedef roam_log_nbrreq_v1_t roam_log_nbrreq_v2_t; 1633 1634 typedef struct roam_log_bcnrptreq { 1635 prsv_periodic_log_hdr_t hdr; 1636 int32 result; 1637 uint8 reg; /* operating class */ 1638 uint8 channel; /* number of requesting channel */ 1639 uint8 mode; /* request mode d11 rmreq bcn */ 1640 uint8 bssid_wild; /* is wild bssid */ 1641 uint8 ssid_len; /* length of SSID */ 1642 uint8 pad; 1643 uint16 duration; /* duration */ 1644 uint8 ssid[ROAM_SSID_LEN]; 1645 } roam_log_bcnrpt_req_v1_t; 1646 1647 typedef roam_log_bcnrpt_req_v1_t roam_log_bcnrpt_req_v2_t; 1648 1649 typedef struct roam_log_bcnrptrep { 1650 prsv_periodic_log_hdr_t hdr; 1651 uint32 count; 1652 } roam_log_bcnrpt_rep_v1_t; 1653 1654 typedef struct roam_log_bcnrptrep_v2 { 1655 prsv_periodic_log_hdr_t hdr; 1656 uint8 scan_inprogress; /* if scan in progress TRUE */ 1657 uint8 reason; /* report mode d11 RMREP mode */ 1658 uint32 count; 1659 } roam_log_bcnrpt_rep_v2_t; 1660 1661 typedef struct roam_log_btmrep_v2 { 1662 prsv_periodic_log_hdr_t hdr; 1663 uint8 req_mode; /* d11 BSSTRANS req mode */ 1664 uint8 status; /* d11 BSSTRANS response status code */ 1665 uint16 pad[2]; 1666 int result; 1667 } roam_log_btm_rep_v2_t; 1668 1669 /* ROAM_LOG_VER_3 specific structures */ 1670 typedef struct roam_log_btmrep_v3 { 1671 prsv_periodic_log_hdr_t hdr; 1672 uint8 req_mode; /* d11 BSSTRANS req mode */ 1673 uint8 status; /* d11 BSSTRANS response status code */ 1674 uint16 pad[2]; 1675 struct ether_addr target_addr; /* bssid to move */ 1676 int result; 1677 } roam_log_btm_rep_v3_t; 1678 1679 typedef struct roam_log_bcnrptreq_v3 { 1680 prsv_periodic_log_hdr_t hdr; 1681 int32 result; 1682 uint8 reg; /* operating class */ 1683 uint8 channel; /* number of requesting channel */ 1684 uint8 mode; /* request mode d11 rmreq bcn */ 1685 uint8 bssid_wild; /* is wild bssid */ 1686 uint8 ssid_len; /* length of SSID */ 1687 uint8 pad; 1688 uint16 duration; /* duration */ 1689 uint8 ssid[ROAM_SSID_LEN]; 1690 uint channel_num; /* number of scan channel */ 1691 uint16 band2g_chan_list; /* channel bit map */ 1692 uint16 uni2a_chan_list; 1693 uint8 uni2c_chan_list[3]; 1694 uint8 uni3_chan_list; 1695 } roam_log_bcnrpt_req_v3_t; 1696 1697 #define BCNRPT_RSN_SUCCESS 0 1698 #define BCNRPT_RSN_BADARG 1 1699 #define BCNRPT_RSN_SCAN_ING 2 1700 #define BCNRPT_RSN_SCAN_FAIL 3 1701 1702 typedef struct roam_log_bcnrptrep_v3 { 1703 prsv_periodic_log_hdr_t hdr; 1704 uint8 scan_status; /* scan status */ 1705 uint8 reason; /* report mode d11 RMREP mode */ 1706 uint16 reason_detail; 1707 uint32 count; 1708 uint16 duration; /* duration */ 1709 uint16 pad; 1710 } roam_log_bcnrpt_rep_v3_t; 1711 1712 typedef struct roam_log_wips_evt_v3 { 1713 prsv_periodic_log_hdr_t hdr; 1714 uint32 timestamp; 1715 struct ether_addr bssid; /* ether addr */ 1716 uint16 misdeauth; 1717 int16 current_rssi; 1718 int16 deauth_rssi; 1719 } roam_log_wips_evt_v3_t; 1720 1721 #define EVENT_LOG_BUFFER_ID_PMK 0 1722 #define EVENT_LOG_BUFFER_ID_ANONCE 1 1723 #define EVENT_LOG_BUFFER_ID_SNONCE 2 1724 #define EVENT_LOG_BUFFER_ID_WPA_M3_KEYDATA 3 1725 #define EVENT_LOG_BUFFER_ID_WPA_CACHED_KEYDATA 4 1726 1727 typedef struct event_log_buffer { 1728 uint16 id; /* XTLV ID: EVENT_LOG_XTLV_ID_BUF */ 1729 uint16 len; /* XTLV Len */ 1730 uint16 buf_id; /* One of the above EVENT_LOG_BUFFER_ID_XXXs */ 1731 uint16 pad; /* for 4-byte start alignment of data */ 1732 uint8 data[]; /* the payload of interest */ 1733 } event_log_buffer_t; 1734 1735 #define XTLV_EVENT_LOG_BUFFER_LEN (OFFSETOF(event_log_buffer_t, data)) 1736 #define XTLV_EVENT_LOG_BUFFER_FULL_LEN(buf_len) ALIGN_SIZE((XTLV_EVENT_LOG_BUFFER_LEN + \ 1737 (buf_len) * sizeof(uint8)), sizeof(uint32)) 1738 1739 /* Structures for parsing FSM log data 1740 * Only used by host to parse data coming in FSM log set 1741 * Following log tags use this structured data: 1742 * EVENT_LOG_TAG_ASSOC_SM 1743 * EVENT_LOG_TAG_SUP_SM 1744 * EVENT_LOG_TAG_AUTH_SM 1745 * EVENT_LOG_TAG_SAE_SM 1746 * EVENT_LOG_TAG_FTM_SM 1747 * EVENT_LOG_TAG_NAN_SM 1748 * More state machine log tags may also use this format 1749 */ 1750 1751 /* Generic FSM structure for logging. Must be wrapped into a proper structure. The wrapper 1752 * structure can add more information but this needs to be one of the members of the wrapper 1753 * structure. 1754 */ 1755 typedef struct event_log_generic_fsm_struct { 1756 uint32 old_state; 1757 uint32 new_state; 1758 uint32 reason; 1759 uint32 caller; 1760 } event_log_generic_fsm_struct_t; 1761 1762 typedef struct event_log_wl_fsm_struct { 1763 uint32 unit; 1764 uint32 bsscfg_idx; 1765 event_log_generic_fsm_struct_t generic_fsm; 1766 uint32 data[]; /* Any other information relevant to this state transition */ 1767 } event_log_wl_fsm_struct_t; 1768 1769 /* To be used by DVFS event log FSM logging */ 1770 typedef struct event_log_rte_dvfs_fsm_struct { 1771 event_log_generic_fsm_struct_t generic_fsm; 1772 uint32 data[]; /* Any other information relevant to this state transition */ 1773 } event_log_rte_dvfs_fsm_struct_t; 1774 1775 #endif /* _EVENT_LOG_PAYLOAD_H_ */ 1776