xref: /OK3568_Linux_fs/external/rkwifibt/drivers/bcmdhd/include/dnglevent.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Broadcom Event protocol definitions
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Dependencies: bcmeth.h
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Copyright (C) 2020, Broadcom.
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  *      Unless you and Broadcom execute a separate written software license
9*4882a593Smuzhiyun  * agreement governing use of this software, this software is licensed to you
10*4882a593Smuzhiyun  * under the terms of the GNU General Public License version 2 (the "GPL"),
11*4882a593Smuzhiyun  * available at http://www.broadcom.com/licenses/GPLv2.php, with the
12*4882a593Smuzhiyun  * following added to such license:
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  *      As a special exception, the copyright holders of this software give you
15*4882a593Smuzhiyun  * permission to link this software with independent modules, and to copy and
16*4882a593Smuzhiyun  * distribute the resulting executable under terms of your choice, provided that
17*4882a593Smuzhiyun  * you also meet, for each linked independent module, the terms and conditions of
18*4882a593Smuzhiyun  * the license of that module.  An independent module is a module which is not
19*4882a593Smuzhiyun  * derived from this software.  The special exception does not apply to any
20*4882a593Smuzhiyun  * modifications of the software.
21*4882a593Smuzhiyun  *
22*4882a593Smuzhiyun  *
23*4882a593Smuzhiyun  * <<Broadcom-WL-IPTag/Dual:>>
24*4882a593Smuzhiyun  *
25*4882a593Smuzhiyun  * -----------------------------------------------------------------------------
26*4882a593Smuzhiyun  *
27*4882a593Smuzhiyun  */
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun /*
30*4882a593Smuzhiyun  * Broadcom dngl Ethernet Events protocol defines
31*4882a593Smuzhiyun  *
32*4882a593Smuzhiyun  */
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun #ifndef _DNGLEVENT_H_
35*4882a593Smuzhiyun #define _DNGLEVENT_H_
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun #ifndef _TYPEDEFS_H_
38*4882a593Smuzhiyun #include <typedefs.h>
39*4882a593Smuzhiyun #endif
40*4882a593Smuzhiyun #include <bcmeth.h>
41*4882a593Smuzhiyun #include <ethernet.h>
42*4882a593Smuzhiyun #ifdef HEALTH_CHECK
43*4882a593Smuzhiyun #include <dngl_defs.h>
44*4882a593Smuzhiyun #endif /* HEALTH_CHECK */
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun /* This marks the start of a packed structure section. */
47*4882a593Smuzhiyun #include <packed_section_start.h>
48*4882a593Smuzhiyun #define BCM_DNGL_EVENT_MSG_VERSION		1
49*4882a593Smuzhiyun #define DNGL_E_RSRVD_1				0x0
50*4882a593Smuzhiyun #define DNGL_E_RSRVD_2				0x1
51*4882a593Smuzhiyun #define DNGL_E_SOCRAM_IND			0x2
52*4882a593Smuzhiyun #define DNGL_E_PROFILE_DATA_IND			0x3
53*4882a593Smuzhiyun typedef BWL_PRE_PACKED_STRUCT struct
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun 	uint16  version; /* Current version is 1 */
56*4882a593Smuzhiyun 	uint16  reserved; /* reserved for any future extension */
57*4882a593Smuzhiyun 	uint16  event_type; /* DNGL_E_SOCRAM_IND */
58*4882a593Smuzhiyun 	uint16  datalen; /* Length of the event payload */
59*4882a593Smuzhiyun } BWL_POST_PACKED_STRUCT bcm_dngl_event_msg_t;
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun typedef BWL_PRE_PACKED_STRUCT struct bcm_dngl_event {
62*4882a593Smuzhiyun 	struct ether_header eth;
63*4882a593Smuzhiyun 	bcmeth_hdr_t        bcm_hdr;
64*4882a593Smuzhiyun 	bcm_dngl_event_msg_t      dngl_event;
65*4882a593Smuzhiyun 	/* data portion follows */
66*4882a593Smuzhiyun } BWL_POST_PACKED_STRUCT bcm_dngl_event_t;
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun typedef BWL_PRE_PACKED_STRUCT struct bcm_dngl_socramind {
69*4882a593Smuzhiyun 	uint16			tag;	/* data tag */
70*4882a593Smuzhiyun 	uint16			length; /* data length */
71*4882a593Smuzhiyun 	uint8			value[1]; /* data value with variable length specified by length */
72*4882a593Smuzhiyun } BWL_POST_PACKED_STRUCT bcm_dngl_socramind_t;
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun typedef BWL_PRE_PACKED_STRUCT struct bcm_dngl_profile_data_ind_t {
75*4882a593Smuzhiyun 	uint16 tag;
76*4882a593Smuzhiyun 	uint16 length;
77*4882a593Smuzhiyun 	uint8 value[];
78*4882a593Smuzhiyun } BWL_POST_PACKED_STRUCT bcm_dngl_profile_data_ind_t;
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun typedef BWL_PRE_PACKED_STRUCT struct bcm_dngl_arm_event {
81*4882a593Smuzhiyun 	uint32 type;
82*4882a593Smuzhiyun 	uint32 value;
83*4882a593Smuzhiyun } BWL_POST_PACKED_STRUCT bcm_dngl_arm_event_t;
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun #define PROFILE_DATA_IND_INFO 0x1
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun #define PROFILE_SUB_TYPE_ARM_STATS_INFO 0x1
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun typedef BWL_PRE_PACKED_STRUCT struct bcm_dngl_arm_stats_ind {
90*4882a593Smuzhiyun 	uint16	tag;
91*4882a593Smuzhiyun 	uint16	length;
92*4882a593Smuzhiyun 	uint8	value[];
93*4882a593Smuzhiyun } BWL_POST_PACKED_STRUCT bcm_dngl_arm_stats_ind_t;
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun typedef BWL_PRE_PACKED_STRUCT struct bcm_dngl_arm_stats {
96*4882a593Smuzhiyun 	uint32	cycles;
97*4882a593Smuzhiyun 	uint32	timestamp;
98*4882a593Smuzhiyun 	uint16	freq;
99*4882a593Smuzhiyun 	uint16	roh;
100*4882a593Smuzhiyun 	uint16	num_events;
101*4882a593Smuzhiyun 	uint16  seq_no;
102*4882a593Smuzhiyun 	uint8	value[];
103*4882a593Smuzhiyun } BWL_POST_PACKED_STRUCT bcm_dngl_arm_stats_t;
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun /* SOCRAM_IND type tags */
106*4882a593Smuzhiyun typedef enum socram_ind_tag {
107*4882a593Smuzhiyun 	SOCRAM_IND_ASSERT_TAG = 1,
108*4882a593Smuzhiyun 	SOCRAM_IND_TAG_HEALTH_CHECK = 2
109*4882a593Smuzhiyun } socram_ind_tag_t;
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun /* Health check top level module tags */
112*4882a593Smuzhiyun typedef BWL_PRE_PACKED_STRUCT struct bcm_dngl_healthcheck {
113*4882a593Smuzhiyun 	uint16			top_module_tag;	/* top level module tag */
114*4882a593Smuzhiyun 	uint16			top_module_len; /* Type of PCIE issue indication */
115*4882a593Smuzhiyun 	uint8			value[1]; /* data value with variable length specified by length */
116*4882a593Smuzhiyun } BWL_POST_PACKED_STRUCT bcm_dngl_healthcheck_t;
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun /* Health check top level module tags */
119*4882a593Smuzhiyun #define HEALTH_CHECK_TOP_LEVEL_MODULE_PCIEDEV_RTE 1
120*4882a593Smuzhiyun #define HEALTH_CHECK_PCIEDEV_VERSION_1	1
121*4882a593Smuzhiyun #define HEALTH_CHECK_PCIEDEV_FLAG_IN_D3_SHIFT	0
122*4882a593Smuzhiyun #define HEALTH_CHECK_PCIEDEV_FLAG_AER_SHIFT		1
123*4882a593Smuzhiyun #define HEALTH_CHECK_PCIEDEV_FLAG_LINKDOWN_SHIFT		2
124*4882a593Smuzhiyun #define HEALTH_CHECK_PCIEDEV_FLAG_MSI_INT_SHIFT			3
125*4882a593Smuzhiyun #define HEALTH_CHECK_PCIEDEV_FLAG_NODS_SHIFT			4
126*4882a593Smuzhiyun #define HEALTH_CHECK_PCIEDEV_FLAG_NO_HOST_WAKE_SHIFT		5
127*4882a593Smuzhiyun #define HEALTH_CHECK_PCIEDEV_FLAG_IN_D3	1 << HEALTH_CHECK_PCIEDEV_FLAG_IN_D3_SHIFT
128*4882a593Smuzhiyun #define HEALTH_CHECK_PCIEDEV_FLAG_AER	1 << HEALTH_CHECK_PCIEDEV_FLAG_AER_SHIFT
129*4882a593Smuzhiyun #define HEALTH_CHECK_PCIEDEV_FLAG_LINKDOWN	1 << HEALTH_CHECK_PCIEDEV_FLAG_LINKDOWN_SHIFT
130*4882a593Smuzhiyun #define HEALTH_CHECK_PCIEDEV_FLAG_MSI_INT	1 << HEALTH_CHECK_PCIEDEV_FLAG_MSI_INT_SHIFT
131*4882a593Smuzhiyun #define HEALTH_CHECK_PCIEDEV_FLAG_NODS	1 << HEALTH_CHECK_PCIEDEV_FLAG_NODS_SHIFT
132*4882a593Smuzhiyun #define HEALTH_CHECK_PCIEDEV_FLAG_NO_HOST_WAKE	1 << HEALTH_CHECK_PCIEDEV_FLAG_NO_HOST_WAKE_SHIFT
133*4882a593Smuzhiyun /* PCIE Module TAGs */
134*4882a593Smuzhiyun #define HEALTH_CHECK_PCIEDEV_INDUCED_IND	0x1
135*4882a593Smuzhiyun #define HEALTH_CHECK_PCIEDEV_H2D_DMA_IND	0x2
136*4882a593Smuzhiyun #define HEALTH_CHECK_PCIEDEV_D2H_DMA_IND	0x3
137*4882a593Smuzhiyun #define HEALTH_CHECK_PCIEDEV_IOCTL_STALL_IND	0x4
138*4882a593Smuzhiyun #define HEALTH_CHECK_PCIEDEV_D3ACK_STALL_IND	0x5
139*4882a593Smuzhiyun #define HEALTH_CHECK_PCIEDEV_NODS_IND	0x6
140*4882a593Smuzhiyun #define HEALTH_CHECK_PCIEDEV_LINKSPEED_FALLBACK_IND	0x7
141*4882a593Smuzhiyun #define HEALTH_CHECK_PCIEDEV_DSACK_STALL_IND	0x8
142*4882a593Smuzhiyun #define HEALTH_CHECK_PCIEDEV_FLOWRING_IND	0x9
143*4882a593Smuzhiyun #define HEALTH_CHECK_PCIEDEV_HW_ASSERT_LONG_IND 0xA
144*4882a593Smuzhiyun #define HEALTH_CHECK_PCIEDEV_RXPOST_LONG_IND	0xB
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun #define HC_PCIEDEV_CONFIG_REGLIST_MAX	25
147*4882a593Smuzhiyun typedef BWL_PRE_PACKED_STRUCT struct bcm_dngl_pcie_hc {
148*4882a593Smuzhiyun 	uint16			version; /* HEALTH_CHECK_PCIEDEV_VERSION_1 */
149*4882a593Smuzhiyun 	uint16			reserved;
150*4882a593Smuzhiyun 	uint16			pcie_err_ind_type; /* PCIE Module TAGs */
151*4882a593Smuzhiyun 	uint16			pcie_flag;
152*4882a593Smuzhiyun 	uint32			pcie_control_reg;
153*4882a593Smuzhiyun 	uint32			pcie_config_regs[HC_PCIEDEV_CONFIG_REGLIST_MAX];
154*4882a593Smuzhiyun } BWL_POST_PACKED_STRUCT bcm_dngl_pcie_hc_t;
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun /* define to avoid compile issues in older branches which define hchk_sw_entity_t */
157*4882a593Smuzhiyun #ifdef HCHK_COMMON_SW_EVENT
158*4882a593Smuzhiyun /* Enumerating top level SW entities for use by health check */
159*4882a593Smuzhiyun typedef enum {
160*4882a593Smuzhiyun 	HCHK_SW_ENTITY_UNDEFINED = 0,
161*4882a593Smuzhiyun 	HCHK_SW_ENTITY_PCIE = 1,
162*4882a593Smuzhiyun 	HCHK_SW_ENTITY_SDIO = 2,
163*4882a593Smuzhiyun 	HCHK_SW_ENTITY_USB = 3,
164*4882a593Smuzhiyun 	HCHK_SW_ENTITY_RTE = 4,
165*4882a593Smuzhiyun 	HCHK_SW_ENTITY_WL_PRIMARY = 5, /* WL instance 0 */
166*4882a593Smuzhiyun 	HCHK_SW_ENTITY_WL_SECONDARY = 6, /* WL instance 1 */
167*4882a593Smuzhiyun 	HCHK_SW_ENTITY_MAX
168*4882a593Smuzhiyun } hchk_sw_entity_t;
169*4882a593Smuzhiyun #endif /* HCHK_COMMON_SW_EVENT */
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun /* This marks the end of a packed structure section. */
172*4882a593Smuzhiyun #include <packed_section_end.h>
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun #endif /* _DNGLEVENT_H_ */
175