xref: /OK3568_Linux_fs/external/rkwifibt/drivers/bcmdhd/include/dhdioctl.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Definitions for ioctls to access DHD iovars.
3*4882a593Smuzhiyun  * Based on wlioctl.h (for Broadcom 802.11abg driver).
4*4882a593Smuzhiyun  * (Moves towards generic ioctls for BCM drivers/iovars.)
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Definitions subject to change without notice.
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * Copyright (C) 2020, Broadcom.
9*4882a593Smuzhiyun  *
10*4882a593Smuzhiyun  *      Unless you and Broadcom execute a separate written software license
11*4882a593Smuzhiyun  * agreement governing use of this software, this software is licensed to you
12*4882a593Smuzhiyun  * under the terms of the GNU General Public License version 2 (the "GPL"),
13*4882a593Smuzhiyun  * available at http://www.broadcom.com/licenses/GPLv2.php, with the
14*4882a593Smuzhiyun  * following added to such license:
15*4882a593Smuzhiyun  *
16*4882a593Smuzhiyun  *      As a special exception, the copyright holders of this software give you
17*4882a593Smuzhiyun  * permission to link this software with independent modules, and to copy and
18*4882a593Smuzhiyun  * distribute the resulting executable under terms of your choice, provided that
19*4882a593Smuzhiyun  * you also meet, for each linked independent module, the terms and conditions of
20*4882a593Smuzhiyun  * the license of that module.  An independent module is a module which is not
21*4882a593Smuzhiyun  * derived from this software.  The special exception does not apply to any
22*4882a593Smuzhiyun  * modifications of the software.
23*4882a593Smuzhiyun  *
24*4882a593Smuzhiyun  *
25*4882a593Smuzhiyun  * <<Broadcom-WL-IPTag/Dual:>>
26*4882a593Smuzhiyun  */
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #ifndef _dhdioctl_h_
29*4882a593Smuzhiyun #define	_dhdioctl_h_
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun #include <typedefs.h>
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun /* Linux network driver ioctl encoding */
34*4882a593Smuzhiyun typedef struct dhd_ioctl {
35*4882a593Smuzhiyun 	uint32 cmd;	/* common ioctl definition */
36*4882a593Smuzhiyun 	void *buf;	/* pointer to user buffer */
37*4882a593Smuzhiyun 	uint32 len;	/* length of user buffer */
38*4882a593Smuzhiyun 	uint32 set;	/* get or set request boolean (optional) */
39*4882a593Smuzhiyun 	uint32 used;	/* bytes read or written (optional) */
40*4882a593Smuzhiyun 	uint32 needed;	/* bytes needed (optional) */
41*4882a593Smuzhiyun 	uint32 driver;	/* to identify target driver */
42*4882a593Smuzhiyun } dhd_ioctl_t;
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun /* Underlying BUS definition */
45*4882a593Smuzhiyun enum {
46*4882a593Smuzhiyun 	BUS_TYPE_USB = 0, /* for USB dongles */
47*4882a593Smuzhiyun 	BUS_TYPE_SDIO, /* for SDIO dongles */
48*4882a593Smuzhiyun 	BUS_TYPE_PCIE /* for PCIE dongles */
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun typedef enum {
52*4882a593Smuzhiyun 	DMA_XFER_SUCCESS = 0,
53*4882a593Smuzhiyun 	DMA_XFER_IN_PROGRESS,
54*4882a593Smuzhiyun 	DMA_XFER_FAILED
55*4882a593Smuzhiyun } dma_xfer_status_t;
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun typedef enum d11_lpbk_type {
58*4882a593Smuzhiyun 	M2M_DMA_LPBK = 0,
59*4882a593Smuzhiyun 	D11_LPBK = 1,
60*4882a593Smuzhiyun 	BMC_LPBK = 2,
61*4882a593Smuzhiyun 	M2M_NON_DMA_LPBK = 3,
62*4882a593Smuzhiyun 	D11_HOST_MEM_LPBK = 4,
63*4882a593Smuzhiyun 	BMC_HOST_MEM_LPBK = 5,
64*4882a593Smuzhiyun 	M2M_WRITE_TO_RAM = 6,
65*4882a593Smuzhiyun 	M2M_READ_FROM_RAM = 7,
66*4882a593Smuzhiyun 	D11_WRITE_TO_RAM = 8,
67*4882a593Smuzhiyun 	D11_READ_FROM_RAM = 9,
68*4882a593Smuzhiyun 	MAX_LPBK = 10
69*4882a593Smuzhiyun } dma_xfer_type_t;
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun typedef struct dmaxfer_info {
72*4882a593Smuzhiyun 	uint16 version;
73*4882a593Smuzhiyun 	uint16 length;
74*4882a593Smuzhiyun 	dma_xfer_status_t status;
75*4882a593Smuzhiyun 	dma_xfer_type_t type;
76*4882a593Smuzhiyun 	uint src_delay;
77*4882a593Smuzhiyun 	uint dest_delay;
78*4882a593Smuzhiyun 	uint should_wait;
79*4882a593Smuzhiyun 	uint core_num;
80*4882a593Smuzhiyun 	int error_code;
81*4882a593Smuzhiyun 	uint32 num_bytes;
82*4882a593Smuzhiyun 	uint64 time_taken;
83*4882a593Smuzhiyun 	uint64 tput;
84*4882a593Smuzhiyun } dma_xfer_info_t;
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun #define DHD_DMAXFER_VERSION 0x1
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun #define DHD_FILENAME_MAX 64
89*4882a593Smuzhiyun #define DHD_PATHNAME_MAX 128
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun #ifdef EFI
92*4882a593Smuzhiyun struct control_signal_ops {
93*4882a593Smuzhiyun 	uint32 signal;
94*4882a593Smuzhiyun 	uint32 val;
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun enum {
97*4882a593Smuzhiyun 	WL_REG_ON = 0,
98*4882a593Smuzhiyun 	DEVICE_WAKE = 1,
99*4882a593Smuzhiyun 	TIME_SYNC = 2
100*4882a593Smuzhiyun };
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun typedef struct wifi_properties {
103*4882a593Smuzhiyun 	uint8 version;
104*4882a593Smuzhiyun 	uint32 vendor;
105*4882a593Smuzhiyun 	uint32 model;
106*4882a593Smuzhiyun 	uint8 mac_addr[6];
107*4882a593Smuzhiyun 	uint32 chip_revision;
108*4882a593Smuzhiyun 	uint8 silicon_revision;
109*4882a593Smuzhiyun 	uint8 is_powered;
110*4882a593Smuzhiyun 	uint8 is_sleeping;
111*4882a593Smuzhiyun 	char module_revision[16];	/* null terminated string */
112*4882a593Smuzhiyun 	uint8 is_fw_loaded;
113*4882a593Smuzhiyun 	char  fw_filename[DHD_FILENAME_MAX];		/* null terminated string */
114*4882a593Smuzhiyun 	char nvram_filename[DHD_FILENAME_MAX];	/* null terminated string */
115*4882a593Smuzhiyun 	uint8 channel;
116*4882a593Smuzhiyun 	uint8 module_sn[6];
117*4882a593Smuzhiyun } wifi_properties_t;
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun #define DHD_WIFI_PROPERTIES_VERSION 0x1
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun #define DHD_OTP_SIZE_WORDS 912
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun typedef struct intr_poll_data {
124*4882a593Smuzhiyun 	uint16 version;
125*4882a593Smuzhiyun 	uint16 length;
126*4882a593Smuzhiyun 	uint32 type;
127*4882a593Smuzhiyun 	uint32 value;
128*4882a593Smuzhiyun } intr_poll_t;
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun typedef enum intr_poll_data_type {
131*4882a593Smuzhiyun 	INTR_POLL_DATA_PERIOD = 0,
132*4882a593Smuzhiyun 	INTR_POLL_DATA_NUM_PKTS_THRESH,
133*4882a593Smuzhiyun 	INTR_POLL_DATA_PKT_INTVL_THRESH
134*4882a593Smuzhiyun } intr_poll_type_t;
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun #define DHD_INTR_POLL_VERSION 0x1u
137*4882a593Smuzhiyun #endif /* EFI */
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun typedef struct tput_test {
140*4882a593Smuzhiyun 	uint16 version;
141*4882a593Smuzhiyun 	uint16 length;
142*4882a593Smuzhiyun 	uint8 direction;
143*4882a593Smuzhiyun 	uint8 tput_test_running;
144*4882a593Smuzhiyun 	uint8 mac_sta[6];
145*4882a593Smuzhiyun 	uint8 mac_ap[6];
146*4882a593Smuzhiyun 	uint8 PAD[2];
147*4882a593Smuzhiyun 	uint32 payload_size;
148*4882a593Smuzhiyun 	uint32 num_pkts;
149*4882a593Smuzhiyun 	uint32 timeout_ms;
150*4882a593Smuzhiyun 	uint32 flags;
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	uint32 pkts_good;
153*4882a593Smuzhiyun 	uint32 pkts_bad;
154*4882a593Smuzhiyun 	uint32 pkts_cmpl;
155*4882a593Smuzhiyun 	uint64 time_ms;
156*4882a593Smuzhiyun 	uint64 tput_bps;
157*4882a593Smuzhiyun } tput_test_t;
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun typedef enum {
160*4882a593Smuzhiyun 	TPUT_DIR_TX = 0,
161*4882a593Smuzhiyun 	TPUT_DIR_RX
162*4882a593Smuzhiyun } tput_dir_t;
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun /*
165*4882a593Smuzhiyun  * Current supported roles considered for policy management are AP, P2P and NAN.
166*4882a593Smuzhiyun  * Hence max value is limited to 3.
167*4882a593Smuzhiyun  */
168*4882a593Smuzhiyun #define DHD_MAX_IFACE_PRIORITY 3u
169*4882a593Smuzhiyun typedef enum dhd_iftype {
170*4882a593Smuzhiyun 	DHD_IF_TYPE_STA		= 0,
171*4882a593Smuzhiyun 	DHD_IF_TYPE_AP		= 1,
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun #ifdef DHD_AWDL
174*4882a593Smuzhiyun 	DHD_IF_TYPE_AWDL	= 2,
175*4882a593Smuzhiyun #endif /* DHD_AWDL */
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	DHD_IF_TYPE_NAN_NMI	= 3,
178*4882a593Smuzhiyun 	DHD_IF_TYPE_NAN		= 4,
179*4882a593Smuzhiyun 	DHD_IF_TYPE_P2P_GO	= 5,
180*4882a593Smuzhiyun 	DHD_IF_TYPE_P2P_GC	= 6,
181*4882a593Smuzhiyun 	DHD_IF_TYPE_P2P_DISC	= 7,
182*4882a593Smuzhiyun 	DHD_IF_TYPE_IBSS	= 8,
183*4882a593Smuzhiyun 	DHD_IF_TYPE_MONITOR	= 9,
184*4882a593Smuzhiyun 	DHD_IF_TYPE_AIBSS	= 10,
185*4882a593Smuzhiyun 	DHD_IF_TYPE_MAX
186*4882a593Smuzhiyun } dhd_iftype_t;
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun typedef struct dhd_iface_mgmt_data {
189*4882a593Smuzhiyun 	uint8 policy;
190*4882a593Smuzhiyun 	uint8 priority[DHD_IF_TYPE_MAX];
191*4882a593Smuzhiyun } dhd_iface_mgmt_data_t;
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun typedef enum dhd_iface_mgmt_policy {
194*4882a593Smuzhiyun 	DHD_IF_POLICY_DEFAULT		= 0,
195*4882a593Smuzhiyun 	DHD_IF_POLICY_FCFS		= 1,
196*4882a593Smuzhiyun 	DHD_IF_POLICY_LP		= 2,
197*4882a593Smuzhiyun 	DHD_IF_POLICY_ROLE_PRIORITY	= 3,
198*4882a593Smuzhiyun 	DHD_IF_POLICY_CUSTOM		= 4,
199*4882a593Smuzhiyun 	DHD_IF_POLICY_INVALID		= 5
200*4882a593Smuzhiyun } dhd_iface_mgmt_policy_t;
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun #define TPUT_TEST_T_VER 1
203*4882a593Smuzhiyun #define TPUT_TEST_T_LEN 68
204*4882a593Smuzhiyun #define TPUT_TEST_MIN_PAYLOAD_SIZE 16
205*4882a593Smuzhiyun #define TPUT_TEST_USE_ETHERNET_HDR 0x1
206*4882a593Smuzhiyun #define TPUT_TEST_USE_802_11_HDR 0x2
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun /* per-driver magic numbers */
209*4882a593Smuzhiyun #define DHD_IOCTL_MAGIC		0x00444944
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun /* bump this number if you change the ioctl interface */
212*4882a593Smuzhiyun #define DHD_IOCTL_VERSION	1
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun /*
215*4882a593Smuzhiyun  * Increase the DHD_IOCTL_MAXLEN to 16K for supporting download of NVRAM files of size
216*4882a593Smuzhiyun  * > 8K. In the existing implementation when NVRAM is to be downloaded via the "vars"
217*4882a593Smuzhiyun  * DHD IOVAR, the NVRAM is copied to the DHD Driver memory. Later on when "dwnldstate" is
218*4882a593Smuzhiyun  * invoked with FALSE option, the NVRAM gets copied from the DHD driver to the Dongle
219*4882a593Smuzhiyun  * memory. The simple way to support this feature without modifying the DHD application,
220*4882a593Smuzhiyun  * driver logic is to increase the DHD_IOCTL_MAXLEN size. This macro defines the "size"
221*4882a593Smuzhiyun  * of the buffer in which data is exchanged between the DHD App and DHD driver.
222*4882a593Smuzhiyun  */
223*4882a593Smuzhiyun #define	DHD_IOCTL_MAXLEN	(16384)	/* max length ioctl buffer required */
224*4882a593Smuzhiyun #define	DHD_IOCTL_SMLEN		256		/* "small" length ioctl buffer required */
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun /*
227*4882a593Smuzhiyun  * For cases where 16K buf is not sufficient.
228*4882a593Smuzhiyun  * Ex:- DHD dump output beffer is more than 16K.
229*4882a593Smuzhiyun  */
230*4882a593Smuzhiyun #define	DHD_IOCTL_MAXLEN_32K	(32768u)
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun /* common ioctl definitions */
233*4882a593Smuzhiyun #define DHD_GET_MAGIC				0
234*4882a593Smuzhiyun #define DHD_GET_VERSION				1
235*4882a593Smuzhiyun #define DHD_GET_VAR				2
236*4882a593Smuzhiyun #define DHD_SET_VAR				3
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun /* message levels */
239*4882a593Smuzhiyun #define DHD_ERROR_VAL	0x0001
240*4882a593Smuzhiyun #define DHD_TRACE_VAL	0x0002
241*4882a593Smuzhiyun #define DHD_INFO_VAL	0x0004
242*4882a593Smuzhiyun #define DHD_DATA_VAL	0x0008
243*4882a593Smuzhiyun #define DHD_CTL_VAL	0x0010
244*4882a593Smuzhiyun #define DHD_TIMER_VAL	0x0020
245*4882a593Smuzhiyun #define DHD_HDRS_VAL	0x0040
246*4882a593Smuzhiyun #define DHD_BYTES_VAL	0x0080
247*4882a593Smuzhiyun #define DHD_INTR_VAL	0x0100
248*4882a593Smuzhiyun #define DHD_LOG_VAL	0x0200
249*4882a593Smuzhiyun #define DHD_GLOM_VAL	0x0400
250*4882a593Smuzhiyun #define DHD_EVENT_VAL	0x0800
251*4882a593Smuzhiyun #define DHD_BTA_VAL	0x1000
252*4882a593Smuzhiyun #if defined(NDIS) && (NDISVER >= 0x0630) && defined(BCMDONGLEHOST)
253*4882a593Smuzhiyun #define DHD_SCAN_VAL	0x2000
254*4882a593Smuzhiyun #else
255*4882a593Smuzhiyun #define DHD_ISCAN_VAL	0x2000
256*4882a593Smuzhiyun #endif
257*4882a593Smuzhiyun #define DHD_ARPOE_VAL	0x4000
258*4882a593Smuzhiyun #define DHD_REORDER_VAL	0x8000
259*4882a593Smuzhiyun #define DHD_NOCHECKDIED_VAL		0x20000 /* UTF WAR */
260*4882a593Smuzhiyun #define DHD_PNO_VAL		0x80000
261*4882a593Smuzhiyun #define DHD_RTT_VAL		0x100000
262*4882a593Smuzhiyun #define DHD_MSGTRACE_VAL	0x200000
263*4882a593Smuzhiyun #define DHD_FWLOG_VAL		0x400000
264*4882a593Smuzhiyun #define DHD_DBGIF_VAL		0x800000
265*4882a593Smuzhiyun #ifdef DHD_PCIE_RUNTIMEPM
266*4882a593Smuzhiyun #define DHD_RPM_VAL		0x1000000
267*4882a593Smuzhiyun #else
268*4882a593Smuzhiyun #define DHD_RPM_VAL		DHD_ERROR_VAL
269*4882a593Smuzhiyun #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
270*4882a593Smuzhiyun #define DHD_PKT_MON_VAL		0x2000000
271*4882a593Smuzhiyun #define DHD_PKT_MON_DUMP_VAL	0x4000000
272*4882a593Smuzhiyun #define DHD_ERROR_MEM_VAL	0x8000000
273*4882a593Smuzhiyun #define DHD_DNGL_IOVAR_SET_VAL	0x10000000 /**< logs the setting of dongle iovars */
274*4882a593Smuzhiyun #define DHD_LPBKDTDUMP_VAL	0x20000000
275*4882a593Smuzhiyun #define DHD_PRSRV_MEM_VAL	0x40000000
276*4882a593Smuzhiyun #define DHD_IOVAR_MEM_VAL	0x80000000
277*4882a593Smuzhiyun #define DHD_ANDROID_VAL	0x10000
278*4882a593Smuzhiyun #define DHD_IW_VAL	0x20000
279*4882a593Smuzhiyun #define DHD_CFG_VAL	0x40000
280*4882a593Smuzhiyun #define DHD_CONFIG_VAL	0x80000
281*4882a593Smuzhiyun #define DHD_DUMP_VAL	0x100000
282*4882a593Smuzhiyun #define DUMP_EAPOL_VAL	0x0001
283*4882a593Smuzhiyun #define DUMP_ARP_VAL	0x0002
284*4882a593Smuzhiyun #define DUMP_DHCP_VAL	0x0004
285*4882a593Smuzhiyun #define DUMP_ICMP_VAL	0x0008
286*4882a593Smuzhiyun #define DUMP_DNS_VAL	0x0010
287*4882a593Smuzhiyun #define DUMP_TRX_VAL	0x0080
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun #ifdef SDTEST
290*4882a593Smuzhiyun /* For pktgen iovar */
291*4882a593Smuzhiyun typedef struct dhd_pktgen {
292*4882a593Smuzhiyun 	uint32 version;		/* To allow structure change tracking */
293*4882a593Smuzhiyun 	uint32 freq;		/* Max ticks between tx/rx attempts */
294*4882a593Smuzhiyun 	uint32 count;		/* Test packets to send/rcv each attempt */
295*4882a593Smuzhiyun 	uint32 print;		/* Print counts every <print> attempts */
296*4882a593Smuzhiyun 	uint32 total;		/* Total packets (or bursts) */
297*4882a593Smuzhiyun 	uint32 minlen;		/* Minimum length of packets to send */
298*4882a593Smuzhiyun 	uint32 maxlen;		/* Maximum length of packets to send */
299*4882a593Smuzhiyun 	uint32 numsent;		/* Count of test packets sent */
300*4882a593Smuzhiyun 	uint32 numrcvd;		/* Count of test packets received */
301*4882a593Smuzhiyun 	uint32 numfail;		/* Count of test send failures */
302*4882a593Smuzhiyun 	uint32 mode;		/* Test mode (type of test packets) */
303*4882a593Smuzhiyun 	uint32 stop;		/* Stop after this many tx failures */
304*4882a593Smuzhiyun } dhd_pktgen_t;
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun /* Version in case structure changes */
307*4882a593Smuzhiyun #define DHD_PKTGEN_VERSION 2
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun /* Type of test packets to use */
310*4882a593Smuzhiyun #define DHD_PKTGEN_ECHO		1 /* Send echo requests */
311*4882a593Smuzhiyun #define DHD_PKTGEN_SEND 	2 /* Send discard packets */
312*4882a593Smuzhiyun #define DHD_PKTGEN_RXBURST	3 /* Request dongle send N packets */
313*4882a593Smuzhiyun #define DHD_PKTGEN_RECV		4 /* Continuous rx from continuous tx dongle */
314*4882a593Smuzhiyun #endif /* SDTEST */
315*4882a593Smuzhiyun 
316*4882a593Smuzhiyun /* Enter idle immediately (no timeout) */
317*4882a593Smuzhiyun #define DHD_IDLE_IMMEDIATE	(-1)
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun /* Values for idleclock iovar: other values are the sd_divisor to use when idle */
320*4882a593Smuzhiyun #define DHD_IDLE_ACTIVE	0	/* Do not request any SD clock change when idle */
321*4882a593Smuzhiyun #define DHD_IDLE_STOP   (-1)	/* Request SD clock be stopped (and use SD1 mode) */
322*4882a593Smuzhiyun 
323*4882a593Smuzhiyun enum dhd_maclist_xtlv_type {
324*4882a593Smuzhiyun 	DHD_MACLIST_XTLV_R = 0x1,
325*4882a593Smuzhiyun 	DHD_MACLIST_XTLV_X = 0x2,
326*4882a593Smuzhiyun 	DHD_SVMPLIST_XTLV = 0x3
327*4882a593Smuzhiyun };
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun typedef struct _dhd_maclist_t {
330*4882a593Smuzhiyun 	uint16 version;		/* Version */
331*4882a593Smuzhiyun 	uint16 bytes_len;	/* Total bytes length of lists, XTLV headers and paddings */
332*4882a593Smuzhiyun 	uint8 plist[1];		/* Pointer to the first list */
333*4882a593Smuzhiyun } dhd_maclist_t;
334*4882a593Smuzhiyun 
335*4882a593Smuzhiyun typedef struct _dhd_pd11regs_param {
336*4882a593Smuzhiyun 	uint16 start_idx;
337*4882a593Smuzhiyun 	uint8 verbose;
338*4882a593Smuzhiyun 	uint8 pad;
339*4882a593Smuzhiyun 	uint8 plist[1];
340*4882a593Smuzhiyun } dhd_pd11regs_param;
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun typedef struct _dhd_pd11regs_buf {
343*4882a593Smuzhiyun 	uint16 idx;
344*4882a593Smuzhiyun 	uint8 pad[2];
345*4882a593Smuzhiyun 	uint8 pbuf[1];
346*4882a593Smuzhiyun } dhd_pd11regs_buf;
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun /* BT logging and memory dump */
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun #define BT_LOG_BUF_MAX_SIZE		(DHD_IOCTL_MAXLEN - (2 * sizeof(int)))
351*4882a593Smuzhiyun #define BT_LOG_BUF_NOT_AVAILABLE	0
352*4882a593Smuzhiyun #define BT_LOG_NEXT_BUF_NOT_AVAIL	1
353*4882a593Smuzhiyun #define BT_LOG_NEXT_BUF_AVAIL		2
354*4882a593Smuzhiyun #define BT_LOG_NOT_READY		3
355*4882a593Smuzhiyun 
356*4882a593Smuzhiyun typedef struct bt_log_buf_info {
357*4882a593Smuzhiyun 	int availability;
358*4882a593Smuzhiyun 	int size;
359*4882a593Smuzhiyun 	char buf[BT_LOG_BUF_MAX_SIZE];
360*4882a593Smuzhiyun } bt_log_buf_info_t;
361*4882a593Smuzhiyun 
362*4882a593Smuzhiyun /* request BT memory in chunks */
363*4882a593Smuzhiyun typedef struct bt_mem_req {
364*4882a593Smuzhiyun 	int offset;	/* offset from BT memory start */
365*4882a593Smuzhiyun 	int buf_size;	/* buffer size per chunk */
366*4882a593Smuzhiyun } bt_mem_req_t;
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun typedef struct fw_download_info {
369*4882a593Smuzhiyun 	uint32  fw_start_addr;
370*4882a593Smuzhiyun 	uint32  fw_size;
371*4882a593Smuzhiyun 	uint32  fw_entry_pt;
372*4882a593Smuzhiyun 	char    fw_signature_fname[DHD_FILENAME_MAX];
373*4882a593Smuzhiyun 	char    bootloader_fname[DHD_FILENAME_MAX];
374*4882a593Smuzhiyun 	uint32  bootloader_start_addr;
375*4882a593Smuzhiyun 	char    fw_path[DHD_PATHNAME_MAX];
376*4882a593Smuzhiyun } fw_download_info_t;
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun /* max dest supported */
379*4882a593Smuzhiyun #define DEBUG_BUF_DEST_MAX	4
380*4882a593Smuzhiyun 
381*4882a593Smuzhiyun /* debug buf dest stat */
382*4882a593Smuzhiyun typedef struct debug_buf_dest_stat {
383*4882a593Smuzhiyun 	uint32 stat[DEBUG_BUF_DEST_MAX];
384*4882a593Smuzhiyun } debug_buf_dest_stat_t;
385*4882a593Smuzhiyun 
386*4882a593Smuzhiyun #ifdef DHD_PKTTS
387*4882a593Smuzhiyun /* max pktts flow config supported */
388*4882a593Smuzhiyun #define PKTTS_CONFIG_MAX 8
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun #define PKTTS_OFFSET_INVALID ((uint32)(~0))
391*4882a593Smuzhiyun 
392*4882a593Smuzhiyun /* pktts flow configuration */
393*4882a593Smuzhiyun typedef struct pktts_flow {
394*4882a593Smuzhiyun 	uint16 ver;     /**< version of this struct */
395*4882a593Smuzhiyun 	uint16 len;     /**< length in bytes of this structure */
396*4882a593Smuzhiyun 	uint32 src_ip;  /**< source ip address */
397*4882a593Smuzhiyun 	uint32 dst_ip;  /**< destination ip address */
398*4882a593Smuzhiyun 	uint32 src_port; /**< source port */
399*4882a593Smuzhiyun 	uint32 dst_port; /**< destination port */
400*4882a593Smuzhiyun 	uint32 proto;    /**< protocol */
401*4882a593Smuzhiyun 	uint32 ip_prec;  /**< ip precedence */
402*4882a593Smuzhiyun 	uint32 pkt_offset; /**< offset from data[0] (TCP/UDP payload) */
403*4882a593Smuzhiyun 	uint32 chksum;   /**< 5 tuple checksum */
404*4882a593Smuzhiyun } pktts_flow_t;
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun #define BCM_TS_MAGIC	0xB055B055
407*4882a593Smuzhiyun #define BCM_TS_MAGIC_V2	0xB055B056
408*4882a593Smuzhiyun #define BCM_TS_TX	 1u
409*4882a593Smuzhiyun #define BCM_TS_RX	 2u
410*4882a593Smuzhiyun #define BCM_TS_UTX	 3u /* ucode tx timestamps */
411*4882a593Smuzhiyun 
412*4882a593Smuzhiyun #define PKTTS_MAX_FWTX		4u
413*4882a593Smuzhiyun #define PKTTS_MAX_UCTX		5u
414*4882a593Smuzhiyun #define PKTTS_MAX_UCCNT		8u
415*4882a593Smuzhiyun #define PKTTS_MAX_FWRX		2u
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun /* Firmware timestamp header */
418*4882a593Smuzhiyun typedef struct bcm_to_info_hdr {
419*4882a593Smuzhiyun 	uint magic;  /**< magic word */
420*4882a593Smuzhiyun 	uint type;   /**< tx/rx type */
421*4882a593Smuzhiyun 	uint flowid; /**< 5 tuple checksum */
422*4882a593Smuzhiyun 	uint prec; /**< ip precedence (IP_PREC) */
423*4882a593Smuzhiyun 	uint8 xbytes[16]; /**< 16bytes info from pkt offset */
424*4882a593Smuzhiyun } bcm_to_info_hdr_t;
425*4882a593Smuzhiyun 
426*4882a593Smuzhiyun /* Firmware tx timestamp payload structure */
427*4882a593Smuzhiyun typedef struct bcm_to_info_tx_ts {
428*4882a593Smuzhiyun 	bcm_to_info_hdr_t hdr;
429*4882a593Smuzhiyun 	uint64 dhdt0; /**< system time - DHDT0 */
430*4882a593Smuzhiyun 	uint64 dhdt5; /**< system time - DHDT5 */
431*4882a593Smuzhiyun 	uint fwts[PKTTS_MAX_FWTX];	/**< fw timestamp - FWT0..FWT4 */
432*4882a593Smuzhiyun 	uint ucts[PKTTS_MAX_UCTX];	/**< uc timestamp - UCT0..UCT4 */
433*4882a593Smuzhiyun 	uint uccnt[PKTTS_MAX_UCCNT];	/**< uc counters */
434*4882a593Smuzhiyun } bcm_to_info_tx_ts_t;
435*4882a593Smuzhiyun 
436*4882a593Smuzhiyun /* Firmware rx timestamp payload structure */
437*4882a593Smuzhiyun typedef struct bcm_to_info_rx_ts {
438*4882a593Smuzhiyun 	bcm_to_info_hdr_t hdr;
439*4882a593Smuzhiyun 	uint64 dhdr3; /**< system time - DHDR3 */
440*4882a593Smuzhiyun 	uint fwts[PKTTS_MAX_FWRX]; /**< fw timestamp - FWT0, FWT1 */
441*4882a593Smuzhiyun } bcm_to_info_rx_ts_t;
442*4882a593Smuzhiyun #endif /* DHD_PKTTS */
443*4882a593Smuzhiyun 
444*4882a593Smuzhiyun /* devreset */
445*4882a593Smuzhiyun #define DHD_DEVRESET_VERSION 1
446*4882a593Smuzhiyun 
447*4882a593Smuzhiyun typedef struct devreset_info {
448*4882a593Smuzhiyun 	uint16 version;
449*4882a593Smuzhiyun 	uint16 length;
450*4882a593Smuzhiyun 	uint16 mode;
451*4882a593Smuzhiyun 	int16 status;
452*4882a593Smuzhiyun } devreset_info_t;
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun #ifdef DHD_TX_PROFILE
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun #define DHD_TX_PROFILE_VERSION	1
457*4882a593Smuzhiyun 
458*4882a593Smuzhiyun /* tx_profile structure for tagging */
459*4882a593Smuzhiyun typedef struct dhd_tx_profile_protocol {
460*4882a593Smuzhiyun 	uint16	version;
461*4882a593Smuzhiyun 	uint8	profile_index;
462*4882a593Smuzhiyun 	uint8	layer;
463*4882a593Smuzhiyun 	uint32	protocol_number;
464*4882a593Smuzhiyun 	uint16	src_port;
465*4882a593Smuzhiyun 	uint16	dest_port;
466*4882a593Smuzhiyun } dhd_tx_profile_protocol_t;
467*4882a593Smuzhiyun 
468*4882a593Smuzhiyun #define DHD_TX_PROFILE_DATA_LINK_LAYER	(2u)	/* data link layer protocols */
469*4882a593Smuzhiyun #define DHD_TX_PROFILE_NETWORK_LAYER	(3u)	/* network layer protocols */
470*4882a593Smuzhiyun 
471*4882a593Smuzhiyun #define DHD_MAX_PROFILE_INDEX	(7u)	/* three bits are available to encode
472*4882a593Smuzhiyun 					   the tx profile index in the rate
473*4882a593Smuzhiyun 					   field in host_txbuf_post_t
474*4882a593Smuzhiyun 					 */
475*4882a593Smuzhiyun #define DHD_MAX_PROFILES	(1u)	/* ucode only supports 1 profile atm */
476*4882a593Smuzhiyun 
477*4882a593Smuzhiyun #endif /* defined(DHD_TX_PROFILE) */
478*4882a593Smuzhiyun #endif /* _dhdioctl_h_ */
479