xref: /OK3568_Linux_fs/external/rkwifibt/drivers/bcmdhd/include/bcmspibrcm.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * SD-SPI Protocol Conversion - BCMSDH->gSPI Translation Layer
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Copyright (C) 2020, Broadcom.
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  *      Unless you and Broadcom execute a separate written software license
7*4882a593Smuzhiyun  * agreement governing use of this software, this software is licensed to you
8*4882a593Smuzhiyun  * under the terms of the GNU General Public License version 2 (the "GPL"),
9*4882a593Smuzhiyun  * available at http://www.broadcom.com/licenses/GPLv2.php, with the
10*4882a593Smuzhiyun  * following added to such license:
11*4882a593Smuzhiyun  *
12*4882a593Smuzhiyun  *      As a special exception, the copyright holders of this software give you
13*4882a593Smuzhiyun  * permission to link this software with independent modules, and to copy and
14*4882a593Smuzhiyun  * distribute the resulting executable under terms of your choice, provided that
15*4882a593Smuzhiyun  * you also meet, for each linked independent module, the terms and conditions of
16*4882a593Smuzhiyun  * the license of that module.  An independent module is a module which is not
17*4882a593Smuzhiyun  * derived from this software.  The special exception does not apply to any
18*4882a593Smuzhiyun  * modifications of the software.
19*4882a593Smuzhiyun  *
20*4882a593Smuzhiyun  *
21*4882a593Smuzhiyun  * <<Broadcom-WL-IPTag/Dual:>>
22*4882a593Smuzhiyun  */
23*4882a593Smuzhiyun #ifndef	_BCM_SPI_BRCM_H
24*4882a593Smuzhiyun #define	_BCM_SPI_BRCM_H
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #ifndef SPI_MAX_IOFUNCS
27*4882a593Smuzhiyun /* Maximum number of I/O funcs */
28*4882a593Smuzhiyun #define SPI_MAX_IOFUNCS		4
29*4882a593Smuzhiyun #endif
30*4882a593Smuzhiyun /* global msglevel for debug messages - bitvals come from sdiovar.h */
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #if defined(BCMDBG) || defined(DHD_DEBUG)
33*4882a593Smuzhiyun #define sd_err(x)	do { if (sd_msglevel & SDH_ERROR_VAL) printf x; } while (0)
34*4882a593Smuzhiyun #define sd_trace(x)	do { if (sd_msglevel & SDH_TRACE_VAL) printf x; } while (0)
35*4882a593Smuzhiyun #define sd_info(x)	do { if (sd_msglevel & SDH_INFO_VAL)  printf x; } while (0)
36*4882a593Smuzhiyun #define sd_debug(x)	do { if (sd_msglevel & SDH_DEBUG_VAL) printf x; } while (0)
37*4882a593Smuzhiyun #define sd_data(x)	do { if (sd_msglevel & SDH_DATA_VAL)  printf x; } while (0)
38*4882a593Smuzhiyun #define sd_ctrl(x)	do { if (sd_msglevel & SDH_CTRL_VAL)  printf x; } while (0)
39*4882a593Smuzhiyun #else
40*4882a593Smuzhiyun #define sd_err(x)
41*4882a593Smuzhiyun #define sd_trace(x)
42*4882a593Smuzhiyun #define sd_info(x)
43*4882a593Smuzhiyun #define sd_debug(x)
44*4882a593Smuzhiyun #define sd_data(x)
45*4882a593Smuzhiyun #define sd_ctrl(x)
46*4882a593Smuzhiyun #endif
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun #ifdef BCMPERFSTATS
49*4882a593Smuzhiyun #define sd_log(x)	do { if (sd_msglevel & SDH_LOG_VAL)	 bcmlog x; } while (0)
50*4882a593Smuzhiyun #else
51*4882a593Smuzhiyun #define sd_log(x)
52*4882a593Smuzhiyun #endif
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun #define SDIOH_ASSERT(exp) \
55*4882a593Smuzhiyun 	do { if (!(exp)) \
56*4882a593Smuzhiyun 		printf("!!!ASSERT fail: file %s lines %d", __FILE__, __LINE__); \
57*4882a593Smuzhiyun 	} while (0)
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun #define BLOCK_SIZE_F1		64
60*4882a593Smuzhiyun #define BLOCK_SIZE_F2 		2048
61*4882a593Smuzhiyun #define BLOCK_SIZE_F3 		2048
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun /* internal return code */
64*4882a593Smuzhiyun #define SUCCESS	0
65*4882a593Smuzhiyun #undef ERROR
66*4882a593Smuzhiyun #define ERROR	1
67*4882a593Smuzhiyun #define ERROR_UF	2
68*4882a593Smuzhiyun #define ERROR_OF	3
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun /* private bus modes */
71*4882a593Smuzhiyun #define SDIOH_MODE_SPI		0
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun #define USE_BLOCKMODE		0x2	/* Block mode can be single block or multi */
74*4882a593Smuzhiyun #define USE_MULTIBLOCK		0x4
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun struct sdioh_info {
77*4882a593Smuzhiyun 	uint		cfg_bar;		/* pci cfg address for bar */
78*4882a593Smuzhiyun 	uint32		caps;			/* cached value of capabilities reg */
79*4882a593Smuzhiyun #ifndef BCMSPI_ANDROID
80*4882a593Smuzhiyun 	void		*bar0;			/* BAR0 for PCI Device */
81*4882a593Smuzhiyun #endif /* !BCMSPI_ANDROID */
82*4882a593Smuzhiyun 	osl_t		*osh;			/* osh handler */
83*4882a593Smuzhiyun 	void		*controller;	/* Pointer to SPI Controller's private data struct */
84*4882a593Smuzhiyun 	uint		lockcount;		/* nest count of spi_lock() calls */
85*4882a593Smuzhiyun 	bool		client_intr_enabled;	/* interrupt connnected flag */
86*4882a593Smuzhiyun 	bool		intr_handler_valid;	/* client driver interrupt handler valid */
87*4882a593Smuzhiyun 	sdioh_cb_fn_t	intr_handler;		/* registered interrupt handler */
88*4882a593Smuzhiyun 	void		*intr_handler_arg;	/* argument to call interrupt handler */
89*4882a593Smuzhiyun 	bool		initialized;		/* card initialized */
90*4882a593Smuzhiyun 	uint32		target_dev;		/* Target device ID */
91*4882a593Smuzhiyun 	uint32		intmask;		/* Current active interrupts */
92*4882a593Smuzhiyun 	void		*sdos_info;		/* Pointer to per-OS private data */
93*4882a593Smuzhiyun 	uint32		controller_type;	/* Host controller type */
94*4882a593Smuzhiyun 	uint8		version;		/* Host Controller Spec Compliance Version */
95*4882a593Smuzhiyun 	uint		irq;			/* Client irq */
96*4882a593Smuzhiyun 	uint32		intrcount;		/* Client interrupts */
97*4882a593Smuzhiyun 	uint32		local_intrcount;	/* Controller interrupts */
98*4882a593Smuzhiyun 	bool 		host_init_done;		/* Controller initted */
99*4882a593Smuzhiyun 	bool 		card_init_done;		/* Client SDIO interface initted */
100*4882a593Smuzhiyun 	bool 		polled_mode;		/* polling for command completion */
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	bool		sd_use_dma;		/* DMA on CMD53 */
103*4882a593Smuzhiyun 	bool 		sd_blockmode;		/* sd_blockmode == FALSE => 64 Byte Cmd 53s. */
104*4882a593Smuzhiyun 						/*  Must be on for sd_multiblock to be effective */
105*4882a593Smuzhiyun 	bool 		use_client_ints;	/* If this is false, make sure to restore */
106*4882a593Smuzhiyun 						/*  polling hack in wl_linux.c:wl_timer() */
107*4882a593Smuzhiyun 	int 		adapter_slot;		/* Maybe dealing with multiple slots/controllers */
108*4882a593Smuzhiyun 	int 		sd_mode;		/* SD1/SD4/SPI */
109*4882a593Smuzhiyun 	int 		client_block_size[SPI_MAX_IOFUNCS];		/* Blocksize */
110*4882a593Smuzhiyun 	uint32 		data_xfer_count;	/* Current transfer */
111*4882a593Smuzhiyun 	uint16 		card_rca;		/* Current Address */
112*4882a593Smuzhiyun 	uint8 		num_funcs;		/* Supported funcs on client */
113*4882a593Smuzhiyun 	uint32 		card_dstatus;		/* 32bit device status */
114*4882a593Smuzhiyun 	uint32 		com_cis_ptr;
115*4882a593Smuzhiyun 	uint32 		func_cis_ptr[SPI_MAX_IOFUNCS];
116*4882a593Smuzhiyun 	void		*dma_buf;
117*4882a593Smuzhiyun 	ulong		dma_phys;
118*4882a593Smuzhiyun 	int 		r_cnt;			/* rx count */
119*4882a593Smuzhiyun 	int 		t_cnt;			/* tx_count */
120*4882a593Smuzhiyun 	uint32		wordlen;			/* host processor 16/32bits */
121*4882a593Smuzhiyun 	uint32		prev_fun;
122*4882a593Smuzhiyun 	uint32		chip;
123*4882a593Smuzhiyun 	uint32		chiprev;
124*4882a593Smuzhiyun 	bool		resp_delay_all;
125*4882a593Smuzhiyun 	bool		dwordmode;
126*4882a593Smuzhiyun 	bool		resp_delay_new;
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	struct spierrstats_t spierrstats;
129*4882a593Smuzhiyun };
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun /************************************************************
132*4882a593Smuzhiyun  * Internal interfaces: per-port references into bcmspibrcm.c
133*4882a593Smuzhiyun  */
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun /* Global message bits */
136*4882a593Smuzhiyun extern uint sd_msglevel;
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun /**************************************************************
139*4882a593Smuzhiyun  * Internal interfaces: bcmspibrcm.c references to per-port code
140*4882a593Smuzhiyun  */
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun /* Interrupt (de)registration routines */
143*4882a593Smuzhiyun extern int spi_register_irq(sdioh_info_t *sd, uint irq);
144*4882a593Smuzhiyun extern void spi_free_irq(uint irq, sdioh_info_t *sd);
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun /* OS-specific interrupt wrappers (atomic interrupt enable/disable) */
147*4882a593Smuzhiyun extern void spi_lock(sdioh_info_t *sd);
148*4882a593Smuzhiyun extern void spi_unlock(sdioh_info_t *sd);
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun /* Allocate/init/free per-OS private data */
151*4882a593Smuzhiyun extern int spi_osinit(sdioh_info_t *sd);
152*4882a593Smuzhiyun extern void spi_osfree(sdioh_info_t *sd);
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun #define SPI_RW_FLAG_M			BITFIELD_MASK(1)	/* Bit [31] - R/W Command Bit */
155*4882a593Smuzhiyun #define SPI_RW_FLAG_S			31
156*4882a593Smuzhiyun #define SPI_ACCESS_M			BITFIELD_MASK(1)	/* Bit [30] - Fixed/Incr Access */
157*4882a593Smuzhiyun #define SPI_ACCESS_S			30
158*4882a593Smuzhiyun #define SPI_FUNCTION_M			BITFIELD_MASK(2)	/* Bit [29:28] - Function Number */
159*4882a593Smuzhiyun #define SPI_FUNCTION_S			28
160*4882a593Smuzhiyun #define SPI_REG_ADDR_M			BITFIELD_MASK(17)	/* Bit [27:11] - Address */
161*4882a593Smuzhiyun #define SPI_REG_ADDR_S			11
162*4882a593Smuzhiyun #define SPI_LEN_M			BITFIELD_MASK(11)	/* Bit [10:0] - Packet length */
163*4882a593Smuzhiyun #define SPI_LEN_S			0
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun #endif /* _BCM_SPI_BRCM_H */
166