1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2016 Rockchip Electronics Co., Ltd.
3*4882a593Smuzhiyun * Authors:
4*4882a593Smuzhiyun * Zhiqin Wei <wzq@rock-chips.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Licensed under the Apache License, Version 2.0 (the "License");
7*4882a593Smuzhiyun * you may not use this file except in compliance with the License.
8*4882a593Smuzhiyun * You may obtain a copy of the License at
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * http://www.apache.org/licenses/LICENSE-2.0
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * Unless required by applicable law or agreed to in writing, software
13*4882a593Smuzhiyun * distributed under the License is distributed on an "AS IS" BASIS,
14*4882a593Smuzhiyun * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15*4882a593Smuzhiyun * See the License for the specific language governing permissions and
16*4882a593Smuzhiyun * limitations under the License.
17*4882a593Smuzhiyun */
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #ifndef _rk_drm_rga_
20*4882a593Smuzhiyun #define _rk_drm_rga_
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #include <stdint.h>
23*4882a593Smuzhiyun #include <errno.h>
24*4882a593Smuzhiyun #include <sys/cdefs.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #include "rga.h"
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #ifdef ANDROID
29*4882a593Smuzhiyun #define DRMRGA_HARDWARE_MODULE_ID "librga"
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #include <hardware/gralloc.h>
32*4882a593Smuzhiyun #include <hardware/hardware.h>
33*4882a593Smuzhiyun #include <system/graphics.h>
34*4882a593Smuzhiyun #include <cutils/native_handle.h>
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #ifdef ANDROID_12
37*4882a593Smuzhiyun #include <hardware/hardware_rockchip.h>
38*4882a593Smuzhiyun #endif
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #endif
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #define RGA_BLIT_SYNC 0x5017
43*4882a593Smuzhiyun #define RGA_BLIT_ASYNC 0x5018
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun #ifndef ANDROID /* LINUX */
46*4882a593Smuzhiyun /* flip source image horizontally (around the vertical axis) */
47*4882a593Smuzhiyun #define HAL_TRANSFORM_FLIP_H 0x01
48*4882a593Smuzhiyun /* flip source image vertically (around the horizontal axis)*/
49*4882a593Smuzhiyun #define HAL_TRANSFORM_FLIP_V 0x02
50*4882a593Smuzhiyun /* rotate source image 90 degrees clockwise */
51*4882a593Smuzhiyun #define HAL_TRANSFORM_ROT_90 0x04
52*4882a593Smuzhiyun /* rotate source image 180 degrees */
53*4882a593Smuzhiyun #define HAL_TRANSFORM_ROT_180 0x03
54*4882a593Smuzhiyun /* rotate source image 270 degrees clockwise */
55*4882a593Smuzhiyun #define HAL_TRANSFORM_ROT_270 0x07
56*4882a593Smuzhiyun #endif
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun #define HAL_TRANSFORM_FLIP_H_V 0x08
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /*****************************************************************************/
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun /* for compatibility */
63*4882a593Smuzhiyun #define DRM_RGA_MODULE_API_VERSION HWC_MODULE_API_VERSION_0_1
64*4882a593Smuzhiyun #define DRM_RGA_DEVICE_API_VERSION HWC_DEVICE_API_VERSION_0_1
65*4882a593Smuzhiyun #define DRM_RGA_API_VERSION HWC_DEVICE_API_VERSION
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun #define DRM_RGA_TRANSFORM_ROT_MASK 0x0000000F
68*4882a593Smuzhiyun #define DRM_RGA_TRANSFORM_ROT_0 0x00000000
69*4882a593Smuzhiyun #define DRM_RGA_TRANSFORM_ROT_90 HAL_TRANSFORM_ROT_90
70*4882a593Smuzhiyun #define DRM_RGA_TRANSFORM_ROT_180 HAL_TRANSFORM_ROT_180
71*4882a593Smuzhiyun #define DRM_RGA_TRANSFORM_ROT_270 HAL_TRANSFORM_ROT_270
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun #define DRM_RGA_TRANSFORM_FLIP_MASK 0x00000003
74*4882a593Smuzhiyun #define DRM_RGA_TRANSFORM_FLIP_H HAL_TRANSFORM_FLIP_H
75*4882a593Smuzhiyun #define DRM_RGA_TRANSFORM_FLIP_V HAL_TRANSFORM_FLIP_V
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun enum {
78*4882a593Smuzhiyun AWIDTH = 0,
79*4882a593Smuzhiyun AHEIGHT,
80*4882a593Smuzhiyun ASTRIDE,
81*4882a593Smuzhiyun AFORMAT,
82*4882a593Smuzhiyun ASIZE,
83*4882a593Smuzhiyun ATYPE,
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun /*****************************************************************************/
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun #ifndef ANDROID /* LINUX */
88*4882a593Smuzhiyun /* memory type definitions. */
89*4882a593Smuzhiyun enum drm_rockchip_gem_mem_type {
90*4882a593Smuzhiyun /* Physically Continuous memory and used as default. */
91*4882a593Smuzhiyun ROCKCHIP_BO_CONTIG = 1 << 0,
92*4882a593Smuzhiyun /* cachable mapping. */
93*4882a593Smuzhiyun ROCKCHIP_BO_CACHABLE = 1 << 1,
94*4882a593Smuzhiyun /* write-combine mapping. */
95*4882a593Smuzhiyun ROCKCHIP_BO_WC = 1 << 2,
96*4882a593Smuzhiyun ROCKCHIP_BO_SECURE = 1 << 3,
97*4882a593Smuzhiyun ROCKCHIP_BO_MASK = ROCKCHIP_BO_CONTIG | ROCKCHIP_BO_CACHABLE |
98*4882a593Smuzhiyun ROCKCHIP_BO_WC | ROCKCHIP_BO_SECURE
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun typedef struct bo {
102*4882a593Smuzhiyun int fd;
103*4882a593Smuzhiyun void *ptr;
104*4882a593Smuzhiyun size_t size;
105*4882a593Smuzhiyun size_t offset;
106*4882a593Smuzhiyun size_t pitch;
107*4882a593Smuzhiyun unsigned handle;
108*4882a593Smuzhiyun } bo_t;
109*4882a593Smuzhiyun #endif
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /*
112*4882a593Smuzhiyun @value size: user not need care about.For avoid read/write out of memory
113*4882a593Smuzhiyun */
114*4882a593Smuzhiyun typedef struct rga_rect {
115*4882a593Smuzhiyun int xoffset;
116*4882a593Smuzhiyun int yoffset;
117*4882a593Smuzhiyun int width;
118*4882a593Smuzhiyun int height;
119*4882a593Smuzhiyun int wstride;
120*4882a593Smuzhiyun int hstride;
121*4882a593Smuzhiyun int format;
122*4882a593Smuzhiyun int size;
123*4882a593Smuzhiyun } rga_rect_t;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun typedef struct rga_nn {
126*4882a593Smuzhiyun int nn_flag;
127*4882a593Smuzhiyun int scale_r;
128*4882a593Smuzhiyun int scale_g;
129*4882a593Smuzhiyun int scale_b;
130*4882a593Smuzhiyun int offset_r;
131*4882a593Smuzhiyun int offset_g;
132*4882a593Smuzhiyun int offset_b;
133*4882a593Smuzhiyun } rga_nn_t;
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun typedef struct rga_dither {
136*4882a593Smuzhiyun int enable;
137*4882a593Smuzhiyun int mode;
138*4882a593Smuzhiyun int lut0_l;
139*4882a593Smuzhiyun int lut0_h;
140*4882a593Smuzhiyun int lut1_l;
141*4882a593Smuzhiyun int lut1_h;
142*4882a593Smuzhiyun } rga_dither_t;
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun struct rga_mosaic_info {
145*4882a593Smuzhiyun uint8_t enable;
146*4882a593Smuzhiyun uint8_t mode;
147*4882a593Smuzhiyun };
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun struct rga_pre_intr_info {
150*4882a593Smuzhiyun uint8_t enable;
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun uint8_t read_intr_en;
153*4882a593Smuzhiyun uint8_t write_intr_en;
154*4882a593Smuzhiyun uint8_t read_hold_en;
155*4882a593Smuzhiyun uint32_t read_threshold;
156*4882a593Smuzhiyun uint32_t write_start;
157*4882a593Smuzhiyun uint32_t write_step;
158*4882a593Smuzhiyun };
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun /* MAX(min, (max - channel_value)) */
161*4882a593Smuzhiyun struct rga_osd_invert_factor {
162*4882a593Smuzhiyun uint8_t alpha_max;
163*4882a593Smuzhiyun uint8_t alpha_min;
164*4882a593Smuzhiyun uint8_t yg_max;
165*4882a593Smuzhiyun uint8_t yg_min;
166*4882a593Smuzhiyun uint8_t crb_max;
167*4882a593Smuzhiyun uint8_t crb_min;
168*4882a593Smuzhiyun };
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun struct rga_color {
171*4882a593Smuzhiyun union {
172*4882a593Smuzhiyun struct {
173*4882a593Smuzhiyun uint8_t red;
174*4882a593Smuzhiyun uint8_t green;
175*4882a593Smuzhiyun uint8_t blue;
176*4882a593Smuzhiyun uint8_t alpha;
177*4882a593Smuzhiyun };
178*4882a593Smuzhiyun uint32_t value;
179*4882a593Smuzhiyun };
180*4882a593Smuzhiyun };
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun struct rga_osd_bpp2 {
183*4882a593Smuzhiyun uint8_t ac_swap; // ac swap flag
184*4882a593Smuzhiyun // 0: CA
185*4882a593Smuzhiyun // 1: AC
186*4882a593Smuzhiyun uint8_t endian_swap; // rgba2bpp endian swap
187*4882a593Smuzhiyun // 0: Big endian
188*4882a593Smuzhiyun // 1: Little endian
189*4882a593Smuzhiyun struct rga_color color0;
190*4882a593Smuzhiyun struct rga_color color1;
191*4882a593Smuzhiyun };
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun struct rga_osd_mode_ctrl {
194*4882a593Smuzhiyun uint8_t mode; // OSD cal mode:
195*4882a593Smuzhiyun // 0b'1: statistics mode
196*4882a593Smuzhiyun // 1b'1: auto inversion overlap mode
197*4882a593Smuzhiyun uint8_t direction_mode; // horizontal or vertical
198*4882a593Smuzhiyun // 0: horizontal
199*4882a593Smuzhiyun // 1: vertical
200*4882a593Smuzhiyun uint8_t width_mode; // using @fix_width or LUT width
201*4882a593Smuzhiyun // 0: fix width
202*4882a593Smuzhiyun // 1: LUT width
203*4882a593Smuzhiyun uint16_t block_fix_width; // OSD block fixed width
204*4882a593Smuzhiyun // real width = (fix_width + 1) * 2
205*4882a593Smuzhiyun uint8_t block_num; // OSD block num
206*4882a593Smuzhiyun uint16_t flags_index; // auto invert flags index
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun /* invertion config */
209*4882a593Smuzhiyun uint8_t color_mode; // selete color
210*4882a593Smuzhiyun // 0: src1 color
211*4882a593Smuzhiyun // 1: config data color
212*4882a593Smuzhiyun uint8_t invert_flags_mode; // invert flag selete
213*4882a593Smuzhiyun // 0: use RAM flag
214*4882a593Smuzhiyun // 1: usr last result
215*4882a593Smuzhiyun uint8_t default_color_sel; // default color mode
216*4882a593Smuzhiyun // 0: default is bright
217*4882a593Smuzhiyun // 1: default is dark
218*4882a593Smuzhiyun uint8_t invert_enable; // invert channel enable
219*4882a593Smuzhiyun // 1 << 0: aplha enable
220*4882a593Smuzhiyun // 1 << 1: Y/G disable
221*4882a593Smuzhiyun // 1 << 2: C/RB disable
222*4882a593Smuzhiyun uint8_t invert_mode; // invert cal mode
223*4882a593Smuzhiyun // 0: normal(max-data)
224*4882a593Smuzhiyun // 1: swap
225*4882a593Smuzhiyun uint8_t invert_thresh; // if luma > thresh, osd_flag to be 1
226*4882a593Smuzhiyun uint8_t unfix_index; // OSD width config index
227*4882a593Smuzhiyun };
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun struct rga_osd_info {
230*4882a593Smuzhiyun uint8_t enable;
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun struct rga_osd_mode_ctrl mode_ctrl;
233*4882a593Smuzhiyun struct rga_osd_invert_factor cal_factor;
234*4882a593Smuzhiyun struct rga_osd_bpp2 bpp2_info;
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun union {
237*4882a593Smuzhiyun struct {
238*4882a593Smuzhiyun uint32_t last_flags1;
239*4882a593Smuzhiyun uint32_t last_flags0;
240*4882a593Smuzhiyun };
241*4882a593Smuzhiyun uint64_t last_flags;
242*4882a593Smuzhiyun };
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun union {
245*4882a593Smuzhiyun struct {
246*4882a593Smuzhiyun uint32_t cur_flags1;
247*4882a593Smuzhiyun uint32_t cur_flags0;
248*4882a593Smuzhiyun };
249*4882a593Smuzhiyun uint64_t cur_flags;
250*4882a593Smuzhiyun };
251*4882a593Smuzhiyun };
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun /*
254*4882a593Smuzhiyun @value fd: use fd to share memory, it can be ion shard fd,and dma fd.
255*4882a593Smuzhiyun @value virAddr:userspace address
256*4882a593Smuzhiyun @value phyAddr:use phy address
257*4882a593Smuzhiyun @value hnd: use buffer_handle_t
258*4882a593Smuzhiyun */
259*4882a593Smuzhiyun typedef struct rga_info {
260*4882a593Smuzhiyun int fd;
261*4882a593Smuzhiyun void *virAddr;
262*4882a593Smuzhiyun void *phyAddr;
263*4882a593Smuzhiyun #ifndef ANDROID /* LINUX */
264*4882a593Smuzhiyun unsigned hnd;
265*4882a593Smuzhiyun #else /* Android */
266*4882a593Smuzhiyun buffer_handle_t hnd;
267*4882a593Smuzhiyun #endif
268*4882a593Smuzhiyun int format;
269*4882a593Smuzhiyun rga_rect_t rect;
270*4882a593Smuzhiyun unsigned int blend;
271*4882a593Smuzhiyun int bufferSize;
272*4882a593Smuzhiyun int rotation;
273*4882a593Smuzhiyun int color;
274*4882a593Smuzhiyun int testLog;
275*4882a593Smuzhiyun int mmuFlag;
276*4882a593Smuzhiyun int colorkey_en;
277*4882a593Smuzhiyun int colorkey_mode;
278*4882a593Smuzhiyun int colorkey_max;
279*4882a593Smuzhiyun int colorkey_min;
280*4882a593Smuzhiyun int scale_mode;
281*4882a593Smuzhiyun int color_space_mode;
282*4882a593Smuzhiyun int sync_mode;
283*4882a593Smuzhiyun rga_nn_t nn;
284*4882a593Smuzhiyun rga_dither_t dither;
285*4882a593Smuzhiyun int rop_code;
286*4882a593Smuzhiyun int rd_mode;
287*4882a593Smuzhiyun unsigned short is_10b_compact;
288*4882a593Smuzhiyun unsigned short is_10b_endian;
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun int in_fence_fd;
291*4882a593Smuzhiyun int out_fence_fd;
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun int core;
294*4882a593Smuzhiyun int priority;
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun unsigned short enable;
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun int handle;
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun struct rga_mosaic_info mosaic_info;
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun struct rga_osd_info osd_info;
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun struct rga_pre_intr_info pre_intr;
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun int mpi_mode;
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun union {
309*4882a593Smuzhiyun int ctx_id;
310*4882a593Smuzhiyun int job_handle;
311*4882a593Smuzhiyun };
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun char reserve[402];
314*4882a593Smuzhiyun } rga_info_t;
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun typedef struct drm_rga {
318*4882a593Smuzhiyun rga_rect_t src;
319*4882a593Smuzhiyun rga_rect_t dst;
320*4882a593Smuzhiyun } drm_rga_t;
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun /*
323*4882a593Smuzhiyun @fun rga_set_rect:For use to set the rects esayly
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun @param rect:The rect user want to set,like setting the src rect:
326*4882a593Smuzhiyun drm_rga_t rects;
327*4882a593Smuzhiyun rga_set_rect(rects.src,0,0,1920,1080,1920,NV12);
328*4882a593Smuzhiyun mean to set the src rect to the value.
329*4882a593Smuzhiyun */
rga_set_rect(rga_rect_t * rect,int x,int y,int w,int h,int sw,int sh,int f)330*4882a593Smuzhiyun static inline int rga_set_rect(rga_rect_t *rect,
331*4882a593Smuzhiyun int x, int y, int w, int h, int sw, int sh, int f) {
332*4882a593Smuzhiyun if (!rect)
333*4882a593Smuzhiyun return -EINVAL;
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun rect->xoffset = x;
336*4882a593Smuzhiyun rect->yoffset = y;
337*4882a593Smuzhiyun rect->width = w;
338*4882a593Smuzhiyun rect->height = h;
339*4882a593Smuzhiyun rect->wstride = sw;
340*4882a593Smuzhiyun rect->hstride = sh;
341*4882a593Smuzhiyun rect->format = f;
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun return 0;
344*4882a593Smuzhiyun }
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun #ifndef ANDROID /* LINUX */
rga_set_rotation(rga_info_t * info,int angle)347*4882a593Smuzhiyun static inline void rga_set_rotation(rga_info_t *info, int angle) {
348*4882a593Smuzhiyun if (angle == 90)
349*4882a593Smuzhiyun info->rotation = HAL_TRANSFORM_ROT_90;
350*4882a593Smuzhiyun else if (angle == 180)
351*4882a593Smuzhiyun info->rotation = HAL_TRANSFORM_ROT_180;
352*4882a593Smuzhiyun else if (angle == 270)
353*4882a593Smuzhiyun info->rotation = HAL_TRANSFORM_ROT_270;
354*4882a593Smuzhiyun }
355*4882a593Smuzhiyun #endif
356*4882a593Smuzhiyun /*****************************************************************************/
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun #endif
359