1*4882a593Smuzhiyun #ifndef __DDR_TEST_H_ 2*4882a593Smuzhiyun #define __DDR_TEST_H_ 3*4882a593Smuzhiyun #include "rk_pcba_test_led.h" 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #ifdef PCBA_3308 6*4882a593Smuzhiyun #define DDR_CAPACITY 256 7*4882a593Smuzhiyun #endif 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifdef PCBA_PX3SE 10*4882a593Smuzhiyun #define DDR_CAPACITY 1010 11*4882a593Smuzhiyun #endif 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifdef PCBA_3229GVA 14*4882a593Smuzhiyun #define DDR_CAPACITY 256 15*4882a593Smuzhiyun #endif 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifdef PCBA_1808 18*4882a593Smuzhiyun #define DDR_CAPACITY 928 19*4882a593Smuzhiyun #endif 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #ifdef PCBA_3326 22*4882a593Smuzhiyun //TODO: According to real DDR Capacity to setting 23*4882a593Smuzhiyun #define DDR_CAPACITY 4096 24*4882a593Smuzhiyun #endif 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #ifdef PCBA_PX30 27*4882a593Smuzhiyun //TODO: According to real DDR Capacity to setting 28*4882a593Smuzhiyun #define DDR_CAPACITY 4096 29*4882a593Smuzhiyun #endif 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #ifdef PCBA_3288 32*4882a593Smuzhiyun //TODO: According to real DDR Capacity to setting 33*4882a593Smuzhiyun #define DDR_CAPACITY 4096 34*4882a593Smuzhiyun #endif 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #ifdef PCBA_3328 37*4882a593Smuzhiyun //TODO: According to real DDR Capacity to setting 38*4882a593Smuzhiyun #define DDR_CAPACITY 4096 39*4882a593Smuzhiyun #endif 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #ifdef PCBA_3399 42*4882a593Smuzhiyun //TODO: According to real DDR Capacity to setting 43*4882a593Smuzhiyun #define DDR_CAPACITY 4096 44*4882a593Smuzhiyun #endif 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #ifdef PCBA_3399PRO 47*4882a593Smuzhiyun //TODO: According to real DDR Capacity to setting 48*4882a593Smuzhiyun #define DDR_CAPACITY 4096 49*4882a593Smuzhiyun #endif 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #ifdef PCBA_1126_1109 52*4882a593Smuzhiyun //TODO: According to real DDR Capacity to setting 53*4882a593Smuzhiyun #define DDR_CAPACITY 4096 54*4882a593Smuzhiyun #endif 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #ifdef PCBA_356X 57*4882a593Smuzhiyun //TODO: According to real DDR Capacity to setting 58*4882a593Smuzhiyun #define DDR_CAPACITY 4096 59*4882a593Smuzhiyun #endif 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #ifdef PCBA_3588 62*4882a593Smuzhiyun //TODO: According to real DDR Capacity to setting 63*4882a593Smuzhiyun #define DDR_CAPACITY 8192 64*4882a593Smuzhiyun #endif 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun void *ddr_test(void *argv); 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #endif 69