1 /*
2 * Copyright 2020 Rockchip Electronics Co. LTD
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #define MODULE_TAG "mpp_soc"
18
19 #include <sys/ioctl.h>
20 #include <errno.h>
21 #include <fcntl.h>
22 #include <string.h>
23
24 #include "mpp_debug.h"
25 #include "mpp_common.h"
26
27 #include "mpp_soc.h"
28 #include "mpp_platform.h"
29
30 #define MAX_SOC_NAME_LENGTH 128
31
32 #define CODING_TO_IDX(type) \
33 ((RK_U32)(type) >= (RK_U32)MPP_VIDEO_CodingKhronosExtensions) ? \
34 ((RK_U32)(-1)) : \
35 ((RK_U32)(type) >= (RK_U32)MPP_VIDEO_CodingVC1) ? \
36 ((RK_U32)(type) - (RK_U32)MPP_VIDEO_CodingVC1 + 16) : \
37 ((RK_U32)(type) - (RK_U32)MPP_VIDEO_CodingUnused)
38
39 #define HAVE_MPEG2 ((RK_U32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingMPEG2))))
40 #define HAVE_H263 ((RK_U32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingH263))))
41 #define HAVE_MPEG4 ((RK_U32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingMPEG4))))
42 #define HAVE_AVC ((RK_U32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingAVC))))
43 #define HAVE_MJPEG ((RK_U32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingMJPEG))))
44 #define HAVE_VP8 ((RK_U32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingVP8))))
45 #define HAVE_VP9 ((RK_U32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingVP9))))
46 #define HAVE_HEVC ((RK_U32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingHEVC))))
47 #define HAVE_AVSP ((RK_U32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingAVSPLUS))))
48 #define HAVE_AVS ((RK_U32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingAVS))))
49 #define HAVE_AVS2 ((RK_U32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingAVS2))))
50 #define HAVE_AV1 ((RK_U32)(1 << (CODING_TO_IDX(MPP_VIDEO_CodingAV1))))
51
52 #define CAP_CODING_VDPU (HAVE_MPEG2|HAVE_H263|HAVE_MPEG4|HAVE_AVC|HAVE_MJPEG|HAVE_VP8|HAVE_AVS)
53 #define CAP_CODING_JPEGD_PP (HAVE_MJPEG)
54 #define CAP_CODING_AVSD (HAVE_AVS)
55 #define CAP_CODING_AVSPD (HAVE_AVSP)
56 #define CAP_CODING_AV1D (HAVE_AV1)
57 #define CAP_CODING_HEVC (HAVE_HEVC)
58 #define CAP_CODING_VDPU341 (HAVE_AVC|HAVE_HEVC|HAVE_VP9)
59 #define CAP_CODING_VDPU341_LITE (HAVE_AVC|HAVE_HEVC)
60 #define CAP_CODING_VDPU381 (HAVE_AVC|HAVE_HEVC|HAVE_VP9|HAVE_AVS2)
61
62 #define CAP_CODING_VEPU1 (HAVE_AVC|HAVE_MJPEG|HAVE_VP8)
63 #define CAP_CODING_VEPU_LITE (HAVE_AVC|HAVE_MJPEG)
64 #define CAP_CODING_VEPU22 (HAVE_HEVC)
65 #define CAP_CODING_VEPU54X (HAVE_AVC|HAVE_HEVC)
66 #define CAP_CODING_VEPU540C (HAVE_AVC|HAVE_HEVC|HAVE_MJPEG)
67
68 static const MppDecHwCap vdpu1 = {
69 .cap_coding = CAP_CODING_VDPU,
70 .type = VPU_CLIENT_VDPU1,
71 .cap_fbc = 0,
72 .cap_4k = 0,
73 .cap_8k = 0,
74 .cap_colmv_compress = 0,
75 .cap_hw_h265_rps = 0,
76 .cap_hw_vp9_prob = 0,
77 .cap_jpg_pp_out = 0,
78 .cap_10bit = 0,
79 .cap_down_scale = 0,
80 .cap_lmt_linebuf = 1,
81 .cap_core_num = 1,
82 .cap_hw_jpg_fix = 0,
83 .reserved = 0,
84 };
85
86 static const MppDecHwCap vdpu1_2160p = {
87 .cap_coding = CAP_CODING_VDPU,
88 .type = VPU_CLIENT_VDPU1,
89 .cap_fbc = 0,
90 .cap_4k = 1,
91 .cap_8k = 0,
92 .cap_colmv_compress = 0,
93 .cap_hw_h265_rps = 0,
94 .cap_hw_vp9_prob = 0,
95 .cap_jpg_pp_out = 0,
96 .cap_10bit = 0,
97 .cap_down_scale = 0,
98 .cap_lmt_linebuf = 1,
99 .cap_core_num = 1,
100 .cap_hw_jpg_fix = 0,
101 .reserved = 0,
102 };
103
104 static const MppDecHwCap vdpu1_jpeg_pp = {
105 .cap_coding = CAP_CODING_JPEGD_PP,
106 .type = VPU_CLIENT_VDPU1_PP,
107 .cap_fbc = 0,
108 .cap_4k = 1,
109 .cap_8k = 1,
110 .cap_colmv_compress = 0,
111 .cap_hw_h265_rps = 0,
112 .cap_hw_vp9_prob = 0,
113 .cap_jpg_pp_out = 1,
114 .cap_10bit = 0,
115 .cap_down_scale = 0,
116 .cap_lmt_linebuf = 1,
117 .cap_core_num = 1,
118 .cap_hw_jpg_fix = 0,
119 .reserved = 0,
120 };
121
122 static const MppDecHwCap vdpu2 = {
123 .cap_coding = CAP_CODING_VDPU,
124 .type = VPU_CLIENT_VDPU2,
125 .cap_fbc = 0,
126 .cap_4k = 0,
127 .cap_8k = 0,
128 .cap_colmv_compress = 0,
129 .cap_hw_h265_rps = 0,
130 .cap_hw_vp9_prob = 0,
131 .cap_jpg_pp_out = 0,
132 .cap_10bit = 0,
133 .cap_down_scale = 0,
134 .cap_lmt_linebuf = 1,
135 .cap_core_num = 1,
136 .cap_hw_jpg_fix = 0,
137 .reserved = 0,
138 };
139
140 static const MppDecHwCap vdpu2_jpeg = {
141 .cap_coding = HAVE_MJPEG,
142 .type = VPU_CLIENT_VDPU2,
143 .cap_fbc = 0,
144 .cap_4k = 0,
145 .cap_8k = 0,
146 .cap_colmv_compress = 0,
147 .cap_hw_h265_rps = 0,
148 .cap_hw_vp9_prob = 0,
149 .cap_jpg_pp_out = 0,
150 .cap_10bit = 0,
151 .cap_down_scale = 0,
152 .cap_lmt_linebuf = 1,
153 .cap_core_num = 1,
154 .cap_hw_jpg_fix = 0,
155 .reserved = 0,
156 };
157
158 static const MppDecHwCap vdpu2_jpeg_pp = {
159 .cap_coding = CAP_CODING_JPEGD_PP,
160 .type = VPU_CLIENT_VDPU2_PP,
161 .cap_fbc = 0,
162 .cap_4k = 0,
163 .cap_8k = 0,
164 .cap_colmv_compress = 0,
165 .cap_hw_h265_rps = 0,
166 .cap_hw_vp9_prob = 0,
167 .cap_jpg_pp_out = 1,
168 .cap_10bit = 0,
169 .cap_down_scale = 0,
170 .cap_lmt_linebuf = 1,
171 .cap_core_num = 1,
172 .cap_hw_jpg_fix = 0,
173 .reserved = 0,
174 };
175
176 static const MppDecHwCap vdpu2_jpeg_fix = {
177 .cap_coding = HAVE_MJPEG,
178 .type = VPU_CLIENT_VDPU2,
179 .cap_fbc = 0,
180 .cap_4k = 0,
181 .cap_8k = 0,
182 .cap_colmv_compress = 0,
183 .cap_hw_h265_rps = 0,
184 .cap_hw_vp9_prob = 0,
185 .cap_jpg_pp_out = 0,
186 .cap_10bit = 0,
187 .cap_down_scale = 0,
188 .cap_lmt_linebuf = 1,
189 .cap_core_num = 1,
190 .cap_hw_jpg_fix = 1,
191 .reserved = 0,
192 };
193
194 static const MppDecHwCap vdpu2_jpeg_pp_fix = {
195 .cap_coding = CAP_CODING_JPEGD_PP,
196 .type = VPU_CLIENT_VDPU2_PP,
197 .cap_fbc = 0,
198 .cap_4k = 0,
199 .cap_8k = 0,
200 .cap_colmv_compress = 0,
201 .cap_hw_h265_rps = 0,
202 .cap_hw_vp9_prob = 0,
203 .cap_jpg_pp_out = 1,
204 .cap_10bit = 0,
205 .cap_down_scale = 0,
206 .cap_lmt_linebuf = 1,
207 .cap_core_num = 1,
208 .cap_hw_jpg_fix = 1,
209 .reserved = 0,
210 };
211
212 static const MppDecHwCap rk_hevc = {
213 .cap_coding = CAP_CODING_HEVC,
214 .type = VPU_CLIENT_HEVC_DEC,
215 .cap_fbc = 0,
216 .cap_4k = 1,
217 .cap_8k = 0,
218 .cap_colmv_compress = 0,
219 .cap_hw_h265_rps = 0,
220 .cap_hw_vp9_prob = 0,
221 .cap_jpg_pp_out = 0,
222 .cap_10bit = 1,
223 .cap_down_scale = 0,
224 .cap_lmt_linebuf = 1,
225 .cap_core_num = 1,
226 .cap_hw_jpg_fix = 0,
227 .reserved = 0,
228 };
229
230 static const MppDecHwCap rk_hevc_1080p = {
231 .cap_coding = CAP_CODING_HEVC,
232 .type = VPU_CLIENT_HEVC_DEC,
233 .cap_fbc = 0,
234 .cap_4k = 0,
235 .cap_8k = 0,
236 .cap_colmv_compress = 0,
237 .cap_hw_h265_rps = 0,
238 .cap_hw_vp9_prob = 0,
239 .cap_jpg_pp_out = 0,
240 .cap_10bit = 0,
241 .cap_down_scale = 0,
242 .cap_lmt_linebuf = 1,
243 .cap_core_num = 1,
244 .cap_hw_jpg_fix = 0,
245 .reserved = 0,
246 };
247
248 static const MppDecHwCap vdpu341 = {
249 .cap_coding = CAP_CODING_VDPU341,
250 .type = VPU_CLIENT_RKVDEC,
251 .cap_fbc = 0,
252 .cap_4k = 1,
253 .cap_8k = 0,
254 .cap_colmv_compress = 1,
255 .cap_hw_h265_rps = 0,
256 .cap_hw_vp9_prob = 0,
257 .cap_jpg_pp_out = 0,
258 .cap_10bit = 1,
259 .cap_down_scale = 0,
260 .cap_lmt_linebuf = 1,
261 .cap_core_num = 1,
262 .cap_hw_jpg_fix = 0,
263 .reserved = 0,
264 };
265
266 static const MppDecHwCap vdpu341_lite = {
267 .cap_coding = CAP_CODING_VDPU341_LITE,
268 .type = VPU_CLIENT_RKVDEC,
269 .cap_fbc = 0,
270 .cap_4k = 1,
271 .cap_8k = 0,
272 .cap_colmv_compress = 1,
273 .cap_hw_h265_rps = 0,
274 .cap_hw_vp9_prob = 0,
275 .cap_jpg_pp_out = 0,
276 .cap_10bit = 1,
277 .cap_down_scale = 0,
278 .cap_lmt_linebuf = 1,
279 .cap_core_num = 1,
280 .cap_hw_jpg_fix = 0,
281 .reserved = 0,
282 };
283
284 static const MppDecHwCap vdpu341_lite_1080p = {
285 .cap_coding = CAP_CODING_VDPU341_LITE,
286 .type = VPU_CLIENT_RKVDEC,
287 .cap_fbc = 0,
288 .cap_4k = 0,
289 .cap_8k = 0,
290 .cap_colmv_compress = 1,
291 .cap_hw_h265_rps = 0,
292 .cap_hw_vp9_prob = 0,
293 .cap_jpg_pp_out = 0,
294 .cap_10bit = 0,
295 .cap_down_scale = 0,
296 .cap_lmt_linebuf = 1,
297 .cap_core_num = 1,
298 .cap_hw_jpg_fix = 0,
299 .reserved = 0,
300 };
301
302 static const MppDecHwCap vdpu341_h264 = {
303 .cap_coding = HAVE_AVC,
304 .type = VPU_CLIENT_RKVDEC,
305 .cap_fbc = 0,
306 .cap_4k = 1,
307 .cap_8k = 0,
308 .cap_colmv_compress = 1,
309 .cap_hw_h265_rps = 0,
310 .cap_hw_vp9_prob = 0,
311 .cap_jpg_pp_out = 0,
312 .cap_10bit = 0,
313 .cap_down_scale = 0,
314 .cap_lmt_linebuf = 1,
315 .cap_core_num = 1,
316 .cap_hw_jpg_fix = 0,
317 .reserved = 0,
318 };
319
320 /* vdpu34x support AFBC_V2 output */
321 static const MppDecHwCap vdpu34x = {
322 .cap_coding = CAP_CODING_VDPU341,
323 .type = VPU_CLIENT_RKVDEC,
324 .cap_fbc = 2,
325 .cap_4k = 1,
326 .cap_8k = 1,
327 .cap_colmv_compress = 1,
328 .cap_hw_h265_rps = 1,
329 .cap_hw_vp9_prob = 1,
330 .cap_jpg_pp_out = 0,
331 .cap_10bit = 1,
332 .cap_down_scale = 0,
333 .cap_lmt_linebuf = 0,
334 .cap_core_num = 1,
335 .cap_hw_jpg_fix = 0,
336 .reserved = 0,
337 };
338
339 static const MppDecHwCap vdpu38x = {
340 .cap_coding = CAP_CODING_VDPU381,
341 .type = VPU_CLIENT_RKVDEC,
342 .cap_fbc = 2,
343 .cap_4k = 1,
344 .cap_8k = 1,
345 .cap_colmv_compress = 1,
346 .cap_hw_h265_rps = 1,
347 .cap_hw_vp9_prob = 1,
348 .cap_jpg_pp_out = 0,
349 .cap_10bit = 1,
350 .cap_down_scale = 1,
351 .cap_lmt_linebuf = 0,
352 .cap_core_num = 2,
353 .cap_hw_jpg_fix = 0,
354 .reserved = 0,
355 };
356
357 static const MppDecHwCap vdpu382 = {
358 .cap_coding = CAP_CODING_VDPU381,
359 .type = VPU_CLIENT_RKVDEC,
360 .cap_fbc = 2,
361 .cap_4k = 1,
362 .cap_8k = 1,
363 .cap_colmv_compress = 1,
364 .cap_hw_h265_rps = 1,
365 .cap_hw_vp9_prob = 1,
366 .cap_jpg_pp_out = 0,
367 .cap_10bit = 1,
368 .cap_down_scale = 1,
369 .cap_lmt_linebuf = 0,
370 .cap_core_num = 1,
371 .cap_hw_jpg_fix = 0,
372 .reserved = 0,
373 };
374
375 static const MppDecHwCap vdpu382_lite = {
376 .cap_coding = CAP_CODING_VDPU341,
377 .type = VPU_CLIENT_RKVDEC,
378 .cap_fbc = 0,
379 .cap_4k = 1,
380 .cap_8k = 1,
381 .cap_colmv_compress = 0,
382 .cap_hw_h265_rps = 1,
383 .cap_hw_vp9_prob = 1,
384 .cap_jpg_pp_out = 0,
385 .cap_10bit = 0,
386 .cap_down_scale = 1,
387 .cap_lmt_linebuf = 0,
388 .cap_core_num = 1,
389 .cap_hw_jpg_fix = 0,
390 .reserved = 0,
391 };
392
393 static const MppDecHwCap avspd = {
394 .cap_coding = CAP_CODING_AVSPD,
395 .type = VPU_CLIENT_AVSPLUS_DEC,
396 .cap_fbc = 0,
397 .cap_4k = 0,
398 .cap_8k = 0,
399 .cap_colmv_compress = 0,
400 .cap_hw_h265_rps = 0,
401 .cap_hw_vp9_prob = 0,
402 .cap_jpg_pp_out = 0,
403 .cap_10bit = 0,
404 .cap_down_scale = 0,
405 .cap_lmt_linebuf = 1,
406 .cap_core_num = 1,
407 .cap_hw_jpg_fix = 0,
408 .reserved = 0,
409 };
410
411 static const MppDecHwCap rkjpegd = {
412 .cap_coding = HAVE_MJPEG,
413 .type = VPU_CLIENT_JPEG_DEC,
414 .cap_fbc = 0,
415 .cap_4k = 1,
416 .cap_8k = 0,
417 .cap_colmv_compress = 0,
418 .cap_hw_h265_rps = 0,
419 .cap_hw_vp9_prob = 0,
420 .cap_jpg_pp_out = 0,
421 .cap_10bit = 0,
422 .cap_down_scale = 0,
423 .cap_lmt_linebuf = 0,
424 .cap_core_num = 1,
425 .cap_hw_jpg_fix = 1,
426 .reserved = 0,
427 };
428
429 static const MppDecHwCap av1d = {
430 .cap_coding = CAP_CODING_AV1D,
431 .type = VPU_CLIENT_AV1DEC,
432 .cap_fbc = 0,
433 .cap_4k = 1,
434 .cap_8k = 0,
435 .cap_colmv_compress = 0,
436 .cap_hw_h265_rps = 0,
437 .cap_hw_vp9_prob = 0,
438 .cap_jpg_pp_out = 0,
439 .cap_10bit = 0,
440 .cap_down_scale = 0,
441 .cap_lmt_linebuf = 1,
442 .cap_core_num = 1,
443 .cap_hw_jpg_fix = 0,
444 .reserved = 0,
445 };
446
447 static const MppEncHwCap vepu1 = {
448 .cap_coding = CAP_CODING_VEPU1,
449 .type = VPU_CLIENT_VEPU1,
450 .cap_fbc = 0,
451 .cap_4k = 0,
452 .cap_8k = 0,
453 .cap_hw_osd = 0,
454 .cap_hw_roi = 0,
455 .reserved = 0,
456 };
457
458 static const MppEncHwCap vepu2 = {
459 .cap_coding = CAP_CODING_VEPU1,
460 .type = VPU_CLIENT_VEPU2,
461 .cap_fbc = 0,
462 .cap_4k = 0,
463 .cap_8k = 0,
464 .cap_hw_osd = 0,
465 .cap_hw_roi = 0,
466 .reserved = 0,
467 };
468
469 static const MppEncHwCap vepu2_no_jpeg = {
470 .cap_coding = HAVE_AVC | HAVE_VP8,
471 .type = VPU_CLIENT_VEPU2,
472 .cap_fbc = 0,
473 .cap_4k = 0,
474 .cap_8k = 0,
475 .cap_hw_osd = 0,
476 .cap_hw_roi = 0,
477 .reserved = 0,
478 };
479
480 static const MppEncHwCap vepu2_jpeg = {
481 .cap_coding = HAVE_MJPEG,
482 .type = VPU_CLIENT_VEPU2_JPEG,
483 .cap_fbc = 0,
484 .cap_4k = 0,
485 .cap_8k = 0,
486 .cap_hw_osd = 0,
487 .cap_hw_roi = 0,
488 .reserved = 0,
489 };
490
491 static const MppEncHwCap vepu22 = {
492 .cap_coding = CAP_CODING_HEVC,
493 .type = VPU_CLIENT_VEPU22,
494 .cap_fbc = 0,
495 .cap_4k = 0,
496 .cap_8k = 0,
497 .cap_hw_osd = 0,
498 .cap_hw_roi = 0,
499 .reserved = 0,
500 };
501
502 static const MppEncHwCap vepu540p = {
503 .cap_coding = HAVE_AVC,
504 .type = VPU_CLIENT_RKVENC,
505 .cap_fbc = 0,
506 .cap_4k = 0,
507 .cap_8k = 0,
508 .cap_hw_osd = 1,
509 .cap_hw_roi = 1,
510 .reserved = 0,
511 };
512
513 static const MppEncHwCap vepu541 = {
514 .cap_coding = CAP_CODING_VEPU54X,
515 .type = VPU_CLIENT_RKVENC,
516 .cap_fbc = 1,
517 .cap_4k = 1,
518 .cap_8k = 0,
519 .cap_hw_osd = 1,
520 .cap_hw_roi = 1,
521 .reserved = 0,
522 };
523
524 /* vepu540 support both AFBC_V1 and AFBC_V2 input */
525 static const MppEncHwCap vepu540 = {
526 .cap_coding = CAP_CODING_VEPU54X,
527 .type = VPU_CLIENT_RKVENC,
528 .cap_fbc = 0x1 | 0x2,
529 .cap_4k = 0,
530 .cap_8k = 0,
531 .cap_hw_osd = 1,
532 .cap_hw_roi = 1,
533 .reserved = 0,
534 };
535
536 /* vepu58x */
537 static const MppEncHwCap vepu58x = {
538 .cap_coding = CAP_CODING_VEPU54X,
539 .type = VPU_CLIENT_RKVENC,
540 .cap_fbc = 0x1 | 0x2,
541 .cap_4k = 1,
542 .cap_8k = 1,
543 .cap_hw_osd = 1,
544 .cap_hw_roi = 1,
545 .reserved = 0,
546 };
547
548 static const MppEncHwCap vepu540c = {
549 .cap_coding = CAP_CODING_VEPU540C,
550 .type = VPU_CLIENT_RKVENC,
551 .cap_fbc = 0x1 | 0x2,
552 .cap_4k = 0,
553 .cap_8k = 0,
554 .cap_hw_osd = 0,
555 .cap_hw_roi = 1,
556 .reserved = 0,
557 };
558
559 static const MppEncHwCap vepu540c_no_hevc = {
560 .cap_coding = (HAVE_AVC | HAVE_MJPEG),
561 .type = VPU_CLIENT_RKVENC,
562 .cap_fbc = 0,
563 .cap_4k = 1,
564 .cap_8k = 1,
565 .cap_hw_osd = 0,
566 .cap_hw_roi = 1,
567 .reserved = 0,
568 };
569
570 /*
571 * NOTE:
572 * vpu1 = vdpu1 + vepu1
573 * vpu2 = vdpu2 + vepu2
574 */
575 static const MppSocInfo mpp_soc_infos[] = {
576 { /*
577 * rk3036 has
578 * 1 - vdpu1
579 * 2 - RK hevc decoder
580 * rk3036 do NOT have encoder
581 */
582 "rk3036",
583 ROCKCHIP_SOC_RK3036,
584 HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_HEVC_DEC,
585 { &rk_hevc_1080p, &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, NULL, },
586 { NULL, NULL, NULL, NULL, },
587 },
588 { /* rk3066 has vpu1 only */
589 "rk3066",
590 ROCKCHIP_SOC_RK3066,
591 HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1,
592 { &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, NULL, NULL, },
593 { &vepu1, NULL, NULL, NULL, },
594 },
595 { /* rk3188 has vpu1 only */
596 "rk3188",
597 ROCKCHIP_SOC_RK3188,
598 HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1,
599 { &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, NULL, NULL, },
600 { &vepu1, NULL, NULL, NULL, },
601 },
602 { /*
603 * rk3288 has
604 * 1 - vpu1 with 2160p AVC decoder
605 * 2 - RK hevc 4K decoder
606 */
607 "rk3288",
608 ROCKCHIP_SOC_RK3288,
609 HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1 | HAVE_HEVC_DEC,
610 { &rk_hevc, &vdpu1_2160p, &vdpu1_jpeg_pp, NULL, NULL, NULL, },
611 { &vepu1, NULL, NULL, NULL, },
612 },
613 { /*
614 * rk3126 has
615 * 1 - vpu1
616 * 2 - RK hevc 1080p decoder
617 */
618 "rk3126",
619 ROCKCHIP_SOC_RK312X,
620 HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1 | HAVE_HEVC_DEC,
621 { &rk_hevc_1080p, &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, NULL, },
622 { &vepu1, NULL, NULL, NULL, },
623 },
624 { /*
625 * rk3128h has
626 * 1 - vpu2
627 * 2 - RK H.264/H.265 1080p@60fps decoder
628 * NOTE: rk3128H do NOT have jpeg encoder
629 */
630 "rk3128h",
631 ROCKCHIP_SOC_RK3128H,
632 HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC,
633 { &vdpu341_lite_1080p, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, NULL, },
634 { &vepu2_no_jpeg, NULL, NULL, NULL, },
635 },
636 { /*
637 * rk3128 has
638 * 1 - vpu1
639 * 2 - RK hevc 1080p decoder
640 */
641 "rk3128",
642 ROCKCHIP_SOC_RK312X,
643 HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1 | HAVE_HEVC_DEC,
644 { &rk_hevc_1080p, &vdpu1, &vdpu1_jpeg_pp, NULL, NULL, NULL, },
645 { &vepu1, NULL, NULL, NULL, },
646 },
647 { /*
648 * rk3368 has
649 * 1 - vpu1
650 * 2 - RK hevc 4K decoder
651 */
652 "rk3368",
653 ROCKCHIP_SOC_RK3368,
654 HAVE_VDPU1 | HAVE_VDPU1_PP | HAVE_VEPU1 | HAVE_HEVC_DEC,
655 { &rk_hevc, &vdpu1_2160p, &vdpu1_jpeg_pp, NULL, NULL, NULL, },
656 { &vepu1, NULL, NULL, NULL, },
657 },
658 { /*
659 * rk3399 has
660 * 1 - vpu2
661 * 2 - H.264/H.265/VP9 4K decoder
662 */
663 "rk3399",
664 ROCKCHIP_SOC_RK3399,
665 HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC,
666 { &vdpu341, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, NULL, },
667 { &vepu2, NULL, NULL, NULL, },
668 },
669 { /*
670 * rk3228h has
671 * 1 - vpu2
672 * 2 - RK H.264/H.265 4K decoder
673 * 3 - avs+ decoder
674 * 4 - H.265 1080p encoder
675 * rk3228h first for string matching
676 */
677 "rk3228h",
678 ROCKCHIP_SOC_RK3228H,
679 HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_AVSDEC | HAVE_VEPU22,
680 { &vdpu341_lite, &vdpu2, &vdpu2_jpeg_pp, &avspd, NULL, NULL, },
681 { &vepu2_no_jpeg, &vepu22, NULL, NULL, },
682 },
683 { /*
684 * rk3328 has codec:
685 * 1 - vpu2
686 * 2 - RK H.264/H.265/VP9 4K decoder
687 * 4 - H.265 encoder
688 */
689 "rk3328",
690 ROCKCHIP_SOC_RK3328,
691 HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_VEPU22,
692 { &vdpu341, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, NULL, },
693 { &vepu2, &vepu22, NULL, NULL, },
694 },
695 { /*
696 * rk3228 have codec:
697 * 1 - vpu2
698 * 2 - RK H.264/H.265 4K decoder
699 * NOTE: rk3228 do NOT have jpeg encoder
700 */
701 "rk3228",
702 ROCKCHIP_SOC_RK3228,
703 HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC,
704 { &vdpu341_lite, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, NULL, },
705 { &vepu2_no_jpeg, NULL, NULL, NULL, },
706 },
707 { /*
708 * rk3229 has
709 * 1 - vpu2
710 * 2 - H.264/H.265/VP9 4K decoder
711 */
712 "rk3229",
713 ROCKCHIP_SOC_RK3229,
714 HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC,
715 { &vdpu341, &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, NULL, },
716 { &vepu2, NULL, NULL, NULL, },
717 },
718 { /*
719 * rv1108 has codec:
720 * 1 - vpu2 for jpeg encoder and decoder
721 * 2 - RK H.264 4K decoder
722 * 3 - RK H.264 4K encoder
723 */
724 "rv1108",
725 ROCKCHIP_SOC_RV1108,
726 HAVE_VDPU2 | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC,
727 { &vdpu2_jpeg, &vdpu341_h264, NULL, NULL, NULL, NULL, },
728 { &vepu2_jpeg, &vepu540p, NULL, NULL, },
729 },
730 { /*
731 * rv1109 has codec:
732 * 1 - vpu2 for jpeg encoder and decoder
733 * 2 - RK H.264/H.265 4K decoder
734 * 3 - RK H.264/H.265 4K encoder
735 */
736 "rv1109",
737 ROCKCHIP_SOC_RV1109,
738 HAVE_VDPU2 | HAVE_VEPU2_JPEG | HAVE_RKVDEC | HAVE_RKVENC,
739 { &vdpu2_jpeg_fix, &vdpu341_lite, NULL, NULL, NULL, NULL, },
740 { &vepu2_jpeg, &vepu541, NULL, NULL, },
741 },
742 { /*
743 * rv1126 has codec:
744 * 1 - vpu2 for jpeg encoder and decoder
745 * 2 - RK H.264/H.265 4K decoder
746 * 3 - RK H.264/H.265 4K encoder
747 */
748 "rv1126",
749 ROCKCHIP_SOC_RV1126,
750 HAVE_VDPU2 | HAVE_VEPU2_JPEG | HAVE_RKVDEC | HAVE_RKVENC,
751 { &vdpu2_jpeg_fix, &vdpu341_lite, NULL, NULL, NULL, NULL, },
752 { &vepu2_jpeg, &vepu541, NULL, NULL, },
753 },
754 { /*
755 * rk3326 has
756 * 1 - vpu2
757 * 2 - RK hevc 1080p decoder
758 */
759 "rk3326",
760 ROCKCHIP_SOC_RK3326,
761 HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_HEVC_DEC,
762 { &rk_hevc_1080p, &vdpu2, &vdpu2_jpeg_pp_fix, NULL, NULL, NULL, },
763 { &vepu2, NULL, NULL, NULL, },
764 },
765 { /*
766 * px30 has
767 * 1 - vpu2
768 * 2 - RK hevc 1080p decoder
769 */
770 "px30",
771 ROCKCHIP_SOC_RK3326,
772 HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_HEVC_DEC,
773 { &rk_hevc_1080p, &vdpu2, &vdpu2_jpeg_pp_fix, NULL, NULL, NULL, },
774 { &vepu2, NULL, NULL, NULL, },
775 },
776 { /*
777 * px30 has vpu2 only
778 */
779 "rk1808",
780 ROCKCHIP_SOC_RK1808,
781 HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2,
782 { &vdpu2, &vdpu2_jpeg_pp, NULL, NULL, NULL, NULL, },
783 { &vepu2, NULL, NULL, NULL, },
784 },
785 { /*
786 * rk3566/rk3568 has codec:
787 * 1 - vpu2 for jpeg/vp8 encoder and decoder
788 * 2 - RK H.264/H.265/VP9 4K decoder
789 * 3 - RK H.264/H.265 4K encoder
790 * 3 - RK jpeg decoder
791 */
792 "rk3566",
793 ROCKCHIP_SOC_RK3566,
794 HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC | HAVE_JPEG_DEC,
795 { &vdpu34x, &rkjpegd, &vdpu2, &vdpu2_jpeg_pp_fix, NULL, NULL, },
796 { &vepu540, &vepu2, NULL, NULL, },
797 },
798 { /*
799 * rk3566/rk3568 has codec:
800 * 1 - vpu2 for jpeg/vp8 encoder and decoder
801 * 2 - RK H.264/H.265/VP9 4K decoder
802 * 3 - RK H.264/H.265 4K encoder
803 * 3 - RK jpeg decoder
804 */
805 "rk3568",
806 ROCKCHIP_SOC_RK3568,
807 HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC | HAVE_JPEG_DEC,
808 { &vdpu34x, &rkjpegd, &vdpu2, &vdpu2_jpeg_pp_fix, NULL, NULL, },
809 { &vepu540, &vepu2, NULL, NULL, },
810 },
811 { /*
812 * rk3588 has codec:
813 * 1 - vpu2 for jpeg/vp8 encoder and decoder
814 * 2 - RK H.264/H.265/VP9 8K decoder
815 * 3 - RK H.264/H.265 8K encoder
816 * 4 - RK jpeg decoder
817 */
818 "rk3588",
819 ROCKCHIP_SOC_RK3588,
820 HAVE_VDPU2 | HAVE_VDPU2_PP | HAVE_VEPU2 | HAVE_RKVDEC | HAVE_RKVENC |
821 HAVE_JPEG_DEC | HAVE_AV1DEC | HAVE_AVSDEC | HAVE_VEPU2_JPEG,
822 { &vdpu38x, &rkjpegd, &vdpu2, &vdpu2_jpeg_pp_fix, &av1d, &avspd},
823 { &vepu58x, &vepu2, &vepu2_jpeg, NULL, },
824 },
825 { /*
826 * rk3528 has codec:
827 * 1 - vpu2 for jpeg/vp8 decoder
828 * 2 - RK H.264/H.265/VP9 4K decoder
829 * 3 - RK H.264/H.265 1080P encoder
830 * 4 - RK jpeg decoder
831 */
832 "rk3528",
833 ROCKCHIP_SOC_RK3528,
834 HAVE_RKVDEC | HAVE_RKVENC | HAVE_VDPU2 | HAVE_JPEG_DEC | HAVE_AVSDEC,
835 { &vdpu382, &rkjpegd, &vdpu2, &avspd, NULL, NULL, },
836 { &vepu540c, NULL, NULL, NULL, },
837 },
838 { /*
839 * rk3562 has codec:
840 * 1 - RK H.264/H.265/VP9 4K decoder
841 * 2 - RK H.264 1080P encoder
842 * 3 - RK jpeg decoder
843 */
844 "rk3562",
845 ROCKCHIP_SOC_RK3562,
846 HAVE_RKVDEC | HAVE_RKVENC | HAVE_JPEG_DEC,
847 { &vdpu382_lite, &rkjpegd, NULL, NULL, NULL, NULL, },
848 { &vepu540c_no_hevc, NULL, NULL, NULL, },
849 },
850 };
851
852 static const MppSocInfo mpp_soc_default = {
853 "unknown",
854 ROCKCHIP_SOC_AUTO,
855 HAVE_VDPU2 | HAVE_VEPU2 | HAVE_VDPU1 | HAVE_VEPU1,
856 { &vdpu2, &vdpu1, NULL, NULL, },
857 { &vepu2, &vepu1, NULL, NULL, },
858 };
859
read_soc_name(char * name,RK_S32 size)860 static void read_soc_name(char *name, RK_S32 size)
861 {
862 const char *path = "/proc/device-tree/compatible";
863 RK_S32 fd = open(path, O_RDONLY);
864
865 if (fd < 0) {
866 mpp_err("open %s error\n", path);
867 } else {
868 ssize_t soc_name_len = 0;
869
870 snprintf(name, size - 1, "unknown");
871 soc_name_len = read(fd, name, size - 1);
872 if (soc_name_len > 0) {
873 name[soc_name_len] = '\0';
874 /* replacing the termination character to space */
875 for (char *ptr = name;; ptr = name) {
876 ptr += strnlen(name, size);
877 if (ptr >= name + soc_name_len - 1)
878 break;
879 *ptr = ' ';
880 }
881
882 mpp_dbg_platform("chip name: %s\n", name);
883 }
884
885 close(fd);
886 }
887 }
888
889
check_soc_info(const char * soc_name)890 static const MppSocInfo *check_soc_info(const char *soc_name)
891 {
892 RK_U32 i;
893
894 for (i = 0; i < MPP_ARRAY_ELEMS(mpp_soc_infos); i++) {
895 const char *compatible = mpp_soc_infos[i].compatible;
896
897 if (strstr(soc_name, compatible)) {
898 mpp_dbg_platform("match chip name: %s\n", compatible);
899 return &mpp_soc_infos[i];
900 }
901 }
902
903 return NULL;
904 }
905
906 class MppSocService
907 {
908 private:
909 // avoid any unwanted function
910 MppSocService();
~MppSocService()911 ~MppSocService() {};
912 MppSocService(const MppSocService &);
913 MppSocService &operator=(const MppSocService &);
914
915 char soc_name[MAX_SOC_NAME_LENGTH];
916 const MppSocInfo *soc_info;
917 RK_U32 dec_coding_cap;
918 RK_U32 enc_coding_cap;
919
920 public:
get()921 static MppSocService *get() {
922 static MppSocService instance;
923 return &instance;
924 }
925
get_soc_name()926 const char *get_soc_name() { return soc_name; };
get_soc_info()927 const MppSocInfo *get_soc_info() { return soc_info; };
get_dec_cap()928 RK_U32 get_dec_cap() { return dec_coding_cap; };
get_enc_cap()929 RK_U32 get_enc_cap() { return enc_coding_cap; };
930 };
931
MppSocService()932 MppSocService::MppSocService()
933 : soc_info(NULL),
934 dec_coding_cap(0),
935 enc_coding_cap(0)
936 {
937 RK_U32 i;
938 RK_U32 vcodec_type = 0;
939
940 read_soc_name(soc_name, sizeof(soc_name));
941 soc_info = check_soc_info(soc_name);
942 if (NULL == soc_info) {
943 mpp_dbg_platform("use default chip info\n");
944 soc_info = &mpp_soc_default;
945 }
946
947 for (i = 0; i < MPP_ARRAY_ELEMS(soc_info->dec_caps); i++) {
948 const MppDecHwCap *cap = soc_info->dec_caps[i];
949
950 if (cap && cap->cap_coding) {
951 dec_coding_cap |= cap->cap_coding;
952 vcodec_type |= (1 << cap->type);
953 }
954 }
955
956 for (i = 0; i < MPP_ARRAY_ELEMS(soc_info->enc_caps); i++) {
957 const MppEncHwCap *cap = soc_info->enc_caps[i];
958
959 if (cap && cap->cap_coding) {
960 enc_coding_cap |= cap->cap_coding;
961 vcodec_type |= (1 << cap->type);
962 }
963 }
964
965 mpp_dbg_platform("coding caps: dec %08x enc %08x\n",
966 dec_coding_cap, enc_coding_cap);
967 mpp_dbg_platform("vcodec type: %08x\n", soc_info->vcodec_type);
968 mpp_assert(soc_info->vcodec_type == vcodec_type);
969 }
970
mpp_get_soc_name(void)971 const char *mpp_get_soc_name(void)
972 {
973 static const char *soc_name = NULL;
974
975 if (soc_name)
976 return soc_name;
977
978 soc_name = MppSocService::get()->get_soc_name();
979 return soc_name;
980 }
981
mpp_get_soc_info(void)982 const MppSocInfo *mpp_get_soc_info(void)
983 {
984 static const MppSocInfo *soc_info = NULL;
985
986 if (soc_info)
987 return soc_info;
988
989 soc_info = MppSocService::get()->get_soc_info();
990 return soc_info;
991 }
992
mpp_get_soc_type(void)993 RockchipSocType mpp_get_soc_type(void)
994 {
995 static RockchipSocType soc_type = ROCKCHIP_SOC_AUTO;
996
997 if (soc_type)
998 return soc_type;
999
1000 soc_type = MppSocService::get()->get_soc_info()->soc_type;
1001 return soc_type;
1002 }
1003
is_valid_cap_coding(RK_U32 cap,MppCodingType coding)1004 static RK_U32 is_valid_cap_coding(RK_U32 cap, MppCodingType coding)
1005 {
1006 RK_S32 index = CODING_TO_IDX(coding);
1007 if (index > 0 && index < 32 && (cap & (RK_U32)(1 << index)))
1008 return true;
1009
1010 return false;
1011 }
1012
mpp_check_soc_cap(MppCtxType type,MppCodingType coding)1013 RK_U32 mpp_check_soc_cap(MppCtxType type, MppCodingType coding)
1014 {
1015 RK_U32 cap = 0;
1016
1017 if (type == MPP_CTX_DEC)
1018 cap = MppSocService::get()->get_dec_cap();
1019 else if (type == MPP_CTX_ENC)
1020 cap = MppSocService::get()->get_enc_cap();
1021 else
1022 return 0;
1023
1024 if (!cap)
1025 return 0;
1026
1027 return is_valid_cap_coding(cap, coding);
1028 }
1029