1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2007 Dave Airlie <airlied@linux.ie> 3*4882a593Smuzhiyun * Copyright (c) 2007 Jakob Bornecrantz <wallbraker@gmail.com> 4*4882a593Smuzhiyun * Copyright (c) 2008 Red Hat Inc. 5*4882a593Smuzhiyun * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA 6*4882a593Smuzhiyun * Copyright (c) 2007-2008 Intel Corporation 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 9*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 10*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 11*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 13*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 16*4882a593Smuzhiyun * all copies or substantial portions of the Software. 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 21*4882a593Smuzhiyun * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22*4882a593Smuzhiyun * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 23*4882a593Smuzhiyun * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 24*4882a593Smuzhiyun * IN THE SOFTWARE. 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #ifndef _DRM_MODE_H 28*4882a593Smuzhiyun #define _DRM_MODE_H 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define DRM_DISPLAY_INFO_LEN 32 31*4882a593Smuzhiyun #define DRM_CONNECTOR_NAME_LEN 32 32*4882a593Smuzhiyun #define DRM_DISPLAY_MODE_LEN 32 33*4882a593Smuzhiyun #define DRM_PROP_NAME_LEN 32 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define DRM_MODE_TYPE_BUILTIN (1<<0) 36*4882a593Smuzhiyun #define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN) 37*4882a593Smuzhiyun #define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN) 38*4882a593Smuzhiyun #define DRM_MODE_TYPE_PREFERRED (1<<3) 39*4882a593Smuzhiyun #define DRM_MODE_TYPE_DEFAULT (1<<4) 40*4882a593Smuzhiyun #define DRM_MODE_TYPE_USERDEF (1<<5) 41*4882a593Smuzhiyun #define DRM_MODE_TYPE_DRIVER (1<<6) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* Video mode flags */ 44*4882a593Smuzhiyun /* bit compatible with the xorg definitions. */ 45*4882a593Smuzhiyun #define DRM_MODE_FLAG_PHSYNC (1<<0) 46*4882a593Smuzhiyun #define DRM_MODE_FLAG_NHSYNC (1<<1) 47*4882a593Smuzhiyun #define DRM_MODE_FLAG_PVSYNC (1<<2) 48*4882a593Smuzhiyun #define DRM_MODE_FLAG_NVSYNC (1<<3) 49*4882a593Smuzhiyun #define DRM_MODE_FLAG_INTERLACE (1<<4) 50*4882a593Smuzhiyun #define DRM_MODE_FLAG_DBLSCAN (1<<5) 51*4882a593Smuzhiyun #define DRM_MODE_FLAG_CSYNC (1<<6) 52*4882a593Smuzhiyun #define DRM_MODE_FLAG_PCSYNC (1<<7) 53*4882a593Smuzhiyun #define DRM_MODE_FLAG_NCSYNC (1<<8) 54*4882a593Smuzhiyun #define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */ 55*4882a593Smuzhiyun #define DRM_MODE_FLAG_BCAST (1<<10) 56*4882a593Smuzhiyun #define DRM_MODE_FLAG_PIXMUX (1<<11) 57*4882a593Smuzhiyun #define DRM_MODE_FLAG_DBLCLK (1<<12) 58*4882a593Smuzhiyun #define DRM_MODE_FLAG_CLKDIV2 (1<<13) 59*4882a593Smuzhiyun #define DRM_MODE_FLAG_3D_MASK (0x1f<<14) 60*4882a593Smuzhiyun #define DRM_MODE_FLAG_3D_NONE (0<<14) 61*4882a593Smuzhiyun #define DRM_MODE_FLAG_3D_FRAME_PACKING (1<<14) 62*4882a593Smuzhiyun #define DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE (2<<14) 63*4882a593Smuzhiyun #define DRM_MODE_FLAG_3D_LINE_ALTERNATIVE (3<<14) 64*4882a593Smuzhiyun #define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL (4<<14) 65*4882a593Smuzhiyun #define DRM_MODE_FLAG_3D_L_DEPTH (5<<14) 66*4882a593Smuzhiyun #define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6<<14) 67*4882a593Smuzhiyun #define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7<<14) 68*4882a593Smuzhiyun #define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8<<14) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* DPMS flags */ 72*4882a593Smuzhiyun /* bit compatible with the xorg definitions. */ 73*4882a593Smuzhiyun #define DRM_MODE_DPMS_ON 0 74*4882a593Smuzhiyun #define DRM_MODE_DPMS_STANDBY 1 75*4882a593Smuzhiyun #define DRM_MODE_DPMS_SUSPEND 2 76*4882a593Smuzhiyun #define DRM_MODE_DPMS_OFF 3 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* Scaling mode options */ 79*4882a593Smuzhiyun #define DRM_MODE_SCALE_NONE 0 /* Unmodified timing (display or 80*4882a593Smuzhiyun software can still scale) */ 81*4882a593Smuzhiyun #define DRM_MODE_SCALE_FULLSCREEN 1 /* Full screen, ignore aspect */ 82*4882a593Smuzhiyun #define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */ 83*4882a593Smuzhiyun #define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */ 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* Dithering mode options */ 86*4882a593Smuzhiyun #define DRM_MODE_DITHERING_OFF 0 87*4882a593Smuzhiyun #define DRM_MODE_DITHERING_ON 1 88*4882a593Smuzhiyun #define DRM_MODE_DITHERING_AUTO 2 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* Dirty info options */ 91*4882a593Smuzhiyun #define DRM_MODE_DIRTY_OFF 0 92*4882a593Smuzhiyun #define DRM_MODE_DIRTY_ON 1 93*4882a593Smuzhiyun #define DRM_MODE_DIRTY_ANNOTATE 2 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* rotation property bits */ 96*4882a593Smuzhiyun #define DRM_ROTATE_0 0 97*4882a593Smuzhiyun #define DRM_ROTATE_90 1 98*4882a593Smuzhiyun #define DRM_ROTATE_180 2 99*4882a593Smuzhiyun #define DRM_ROTATE_270 3 100*4882a593Smuzhiyun #define DRM_REFLECT_X 4 101*4882a593Smuzhiyun #define DRM_REFLECT_Y 5 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun struct drm_mode_modeinfo { 104*4882a593Smuzhiyun __u32 clock; 105*4882a593Smuzhiyun __u16 hdisplay, hsync_start, hsync_end, htotal, hskew; 106*4882a593Smuzhiyun __u16 vdisplay, vsync_start, vsync_end, vtotal, vscan; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun __u32 vrefresh; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun __u32 flags; 111*4882a593Smuzhiyun __u32 type; 112*4882a593Smuzhiyun char name[DRM_DISPLAY_MODE_LEN]; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun struct drm_mode_card_res { 116*4882a593Smuzhiyun __u64 fb_id_ptr; 117*4882a593Smuzhiyun __u64 crtc_id_ptr; 118*4882a593Smuzhiyun __u64 connector_id_ptr; 119*4882a593Smuzhiyun __u64 encoder_id_ptr; 120*4882a593Smuzhiyun __u32 count_fbs; 121*4882a593Smuzhiyun __u32 count_crtcs; 122*4882a593Smuzhiyun __u32 count_connectors; 123*4882a593Smuzhiyun __u32 count_encoders; 124*4882a593Smuzhiyun __u32 min_width, max_width; 125*4882a593Smuzhiyun __u32 min_height, max_height; 126*4882a593Smuzhiyun }; 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun struct drm_mode_crtc { 129*4882a593Smuzhiyun __u64 set_connectors_ptr; 130*4882a593Smuzhiyun __u32 count_connectors; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun __u32 crtc_id; /**< Id */ 133*4882a593Smuzhiyun __u32 fb_id; /**< Id of framebuffer */ 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun __u32 x, y; /**< Position on the frameuffer */ 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun __u32 gamma_size; 138*4882a593Smuzhiyun __u32 mode_valid; 139*4882a593Smuzhiyun struct drm_mode_modeinfo mode; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun #define DRM_MODE_PRESENT_TOP_FIELD (1<<0) 143*4882a593Smuzhiyun #define DRM_MODE_PRESENT_BOTTOM_FIELD (1<<1) 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun /* Planes blend with or override other bits on the CRTC */ 146*4882a593Smuzhiyun struct drm_mode_set_plane { 147*4882a593Smuzhiyun __u32 plane_id; 148*4882a593Smuzhiyun __u32 crtc_id; 149*4882a593Smuzhiyun __u32 fb_id; /* fb object contains surface format type */ 150*4882a593Smuzhiyun __u32 flags; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun /* Signed dest location allows it to be partially off screen */ 153*4882a593Smuzhiyun __s32 crtc_x, crtc_y; 154*4882a593Smuzhiyun __u32 crtc_w, crtc_h; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun /* Source values are 16.16 fixed point */ 157*4882a593Smuzhiyun __u32 src_x, src_y; 158*4882a593Smuzhiyun __u32 src_h, src_w; 159*4882a593Smuzhiyun }; 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun struct drm_mode_get_plane { 162*4882a593Smuzhiyun __u32 plane_id; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun __u32 crtc_id; 165*4882a593Smuzhiyun __u32 fb_id; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun __u32 possible_crtcs; 168*4882a593Smuzhiyun __u32 gamma_size; 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun __u32 count_format_types; 171*4882a593Smuzhiyun __u64 format_type_ptr; 172*4882a593Smuzhiyun }; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun struct drm_mode_get_plane_res { 175*4882a593Smuzhiyun __u64 plane_id_ptr; 176*4882a593Smuzhiyun __u32 count_planes; 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun #define DRM_MODE_ENCODER_NONE 0 180*4882a593Smuzhiyun #define DRM_MODE_ENCODER_DAC 1 181*4882a593Smuzhiyun #define DRM_MODE_ENCODER_TMDS 2 182*4882a593Smuzhiyun #define DRM_MODE_ENCODER_LVDS 3 183*4882a593Smuzhiyun #define DRM_MODE_ENCODER_TVDAC 4 184*4882a593Smuzhiyun #define DRM_MODE_ENCODER_VIRTUAL 5 185*4882a593Smuzhiyun #define DRM_MODE_ENCODER_DSI 6 186*4882a593Smuzhiyun #define DRM_MODE_ENCODER_DPMST 7 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun struct drm_mode_get_encoder { 189*4882a593Smuzhiyun __u32 encoder_id; 190*4882a593Smuzhiyun __u32 encoder_type; 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun __u32 crtc_id; /**< Id of crtc */ 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun __u32 possible_crtcs; 195*4882a593Smuzhiyun __u32 possible_clones; 196*4882a593Smuzhiyun }; 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun /* This is for connectors with multiple signal types. */ 199*4882a593Smuzhiyun /* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */ 200*4882a593Smuzhiyun #define DRM_MODE_SUBCONNECTOR_Automatic 0 201*4882a593Smuzhiyun #define DRM_MODE_SUBCONNECTOR_Unknown 0 202*4882a593Smuzhiyun #define DRM_MODE_SUBCONNECTOR_DVID 3 203*4882a593Smuzhiyun #define DRM_MODE_SUBCONNECTOR_DVIA 4 204*4882a593Smuzhiyun #define DRM_MODE_SUBCONNECTOR_Composite 5 205*4882a593Smuzhiyun #define DRM_MODE_SUBCONNECTOR_SVIDEO 6 206*4882a593Smuzhiyun #define DRM_MODE_SUBCONNECTOR_Component 8 207*4882a593Smuzhiyun #define DRM_MODE_SUBCONNECTOR_SCART 9 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_Unknown 0 210*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_VGA 1 211*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_DVII 2 212*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_DVID 3 213*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_DVIA 4 214*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_Composite 5 215*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_SVIDEO 6 216*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_LVDS 7 217*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_Component 8 218*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_9PinDIN 9 219*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_DisplayPort 10 220*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_HDMIA 11 221*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_HDMIB 12 222*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_TV 13 223*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_eDP 14 224*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_VIRTUAL 15 225*4882a593Smuzhiyun #define DRM_MODE_CONNECTOR_DSI 16 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun struct drm_mode_get_connector { 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun __u64 encoders_ptr; 230*4882a593Smuzhiyun __u64 modes_ptr; 231*4882a593Smuzhiyun __u64 props_ptr; 232*4882a593Smuzhiyun __u64 prop_values_ptr; 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun __u32 count_modes; 235*4882a593Smuzhiyun __u32 count_props; 236*4882a593Smuzhiyun __u32 count_encoders; 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun __u32 encoder_id; /**< Current Encoder */ 239*4882a593Smuzhiyun __u32 connector_id; /**< Id */ 240*4882a593Smuzhiyun __u32 connector_type; 241*4882a593Smuzhiyun __u32 connector_type_id; 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun __u32 connection; 244*4882a593Smuzhiyun __u32 mm_width, mm_height; /**< HxW in millimeters */ 245*4882a593Smuzhiyun __u32 subpixel; 246*4882a593Smuzhiyun }; 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun #define DRM_MODE_PROP_PENDING (1<<0) 249*4882a593Smuzhiyun #define DRM_MODE_PROP_RANGE (1<<1) 250*4882a593Smuzhiyun #define DRM_MODE_PROP_IMMUTABLE (1<<2) 251*4882a593Smuzhiyun #define DRM_MODE_PROP_ENUM (1<<3) /* enumerated type with text strings */ 252*4882a593Smuzhiyun #define DRM_MODE_PROP_BLOB (1<<4) 253*4882a593Smuzhiyun #define DRM_MODE_PROP_BITMASK (1<<5) /* bitmask of enumerated types */ 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun /* non-extended types: legacy bitmask, one bit per type: */ 256*4882a593Smuzhiyun #define DRM_MODE_PROP_LEGACY_TYPE ( \ 257*4882a593Smuzhiyun DRM_MODE_PROP_RANGE | \ 258*4882a593Smuzhiyun DRM_MODE_PROP_ENUM | \ 259*4882a593Smuzhiyun DRM_MODE_PROP_BLOB | \ 260*4882a593Smuzhiyun DRM_MODE_PROP_BITMASK) 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun /* extended-types: rather than continue to consume a bit per type, 263*4882a593Smuzhiyun * grab a chunk of the bits to use as integer type id. 264*4882a593Smuzhiyun */ 265*4882a593Smuzhiyun #define DRM_MODE_PROP_EXTENDED_TYPE 0x0000ffc0 266*4882a593Smuzhiyun #define DRM_MODE_PROP_TYPE(n) ((n) << 6) 267*4882a593Smuzhiyun #define DRM_MODE_PROP_OBJECT DRM_MODE_PROP_TYPE(1) 268*4882a593Smuzhiyun #define DRM_MODE_PROP_SIGNED_RANGE DRM_MODE_PROP_TYPE(2) 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun /* the PROP_ATOMIC flag is used to hide properties from userspace that 271*4882a593Smuzhiyun * is not aware of atomic properties. This is mostly to work around 272*4882a593Smuzhiyun * older userspace (DDX drivers) that read/write each prop they find, 273*4882a593Smuzhiyun * witout being aware that this could be triggering a lengthy modeset. 274*4882a593Smuzhiyun */ 275*4882a593Smuzhiyun #define DRM_MODE_PROP_ATOMIC 0x80000000 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun struct drm_mode_property_enum { 278*4882a593Smuzhiyun __u64 value; 279*4882a593Smuzhiyun char name[DRM_PROP_NAME_LEN]; 280*4882a593Smuzhiyun }; 281*4882a593Smuzhiyun 282*4882a593Smuzhiyun struct drm_mode_get_property { 283*4882a593Smuzhiyun __u64 values_ptr; /* values and blob lengths */ 284*4882a593Smuzhiyun __u64 enum_blob_ptr; /* enum and blob id ptrs */ 285*4882a593Smuzhiyun 286*4882a593Smuzhiyun __u32 prop_id; 287*4882a593Smuzhiyun __u32 flags; 288*4882a593Smuzhiyun char name[DRM_PROP_NAME_LEN]; 289*4882a593Smuzhiyun 290*4882a593Smuzhiyun __u32 count_values; 291*4882a593Smuzhiyun __u32 count_enum_blobs; 292*4882a593Smuzhiyun }; 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun struct drm_mode_connector_set_property { 295*4882a593Smuzhiyun __u64 value; 296*4882a593Smuzhiyun __u32 prop_id; 297*4882a593Smuzhiyun __u32 connector_id; 298*4882a593Smuzhiyun }; 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun #define DRM_MODE_OBJECT_CRTC 0xcccccccc 301*4882a593Smuzhiyun #define DRM_MODE_OBJECT_CONNECTOR 0xc0c0c0c0 302*4882a593Smuzhiyun #define DRM_MODE_OBJECT_ENCODER 0xe0e0e0e0 303*4882a593Smuzhiyun #define DRM_MODE_OBJECT_MODE 0xdededede 304*4882a593Smuzhiyun #define DRM_MODE_OBJECT_PROPERTY 0xb0b0b0b0 305*4882a593Smuzhiyun #define DRM_MODE_OBJECT_FB 0xfbfbfbfb 306*4882a593Smuzhiyun #define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb 307*4882a593Smuzhiyun #define DRM_MODE_OBJECT_PLANE 0xeeeeeeee 308*4882a593Smuzhiyun 309*4882a593Smuzhiyun struct drm_mode_obj_get_properties { 310*4882a593Smuzhiyun __u64 props_ptr; 311*4882a593Smuzhiyun __u64 prop_values_ptr; 312*4882a593Smuzhiyun __u32 count_props; 313*4882a593Smuzhiyun __u32 obj_id; 314*4882a593Smuzhiyun __u32 obj_type; 315*4882a593Smuzhiyun }; 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun struct drm_mode_obj_set_property { 318*4882a593Smuzhiyun __u64 value; 319*4882a593Smuzhiyun __u32 prop_id; 320*4882a593Smuzhiyun __u32 obj_id; 321*4882a593Smuzhiyun __u32 obj_type; 322*4882a593Smuzhiyun }; 323*4882a593Smuzhiyun 324*4882a593Smuzhiyun struct drm_mode_get_blob { 325*4882a593Smuzhiyun __u32 blob_id; 326*4882a593Smuzhiyun __u32 length; 327*4882a593Smuzhiyun __u64 data; 328*4882a593Smuzhiyun }; 329*4882a593Smuzhiyun 330*4882a593Smuzhiyun struct drm_mode_fb_cmd { 331*4882a593Smuzhiyun __u32 fb_id; 332*4882a593Smuzhiyun __u32 width, height; 333*4882a593Smuzhiyun __u32 pitch; 334*4882a593Smuzhiyun __u32 bpp; 335*4882a593Smuzhiyun __u32 depth; 336*4882a593Smuzhiyun /* driver specific handle */ 337*4882a593Smuzhiyun __u32 handle; 338*4882a593Smuzhiyun }; 339*4882a593Smuzhiyun 340*4882a593Smuzhiyun #define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */ 341*4882a593Smuzhiyun 342*4882a593Smuzhiyun struct drm_mode_fb_cmd2 { 343*4882a593Smuzhiyun __u32 fb_id; 344*4882a593Smuzhiyun __u32 width, height; 345*4882a593Smuzhiyun __u32 pixel_format; /* fourcc code from drm_fourcc.h */ 346*4882a593Smuzhiyun __u32 flags; 347*4882a593Smuzhiyun 348*4882a593Smuzhiyun /* 349*4882a593Smuzhiyun * In case of planar formats, this ioctl allows up to 4 350*4882a593Smuzhiyun * buffer objects with offsets and pitches per plane. 351*4882a593Smuzhiyun * The pitch and offset order is dictated by the fourcc, 352*4882a593Smuzhiyun * e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as: 353*4882a593Smuzhiyun * 354*4882a593Smuzhiyun * YUV 4:2:0 image with a plane of 8 bit Y samples 355*4882a593Smuzhiyun * followed by an interleaved U/V plane containing 356*4882a593Smuzhiyun * 8 bit 2x2 subsampled colour difference samples. 357*4882a593Smuzhiyun * 358*4882a593Smuzhiyun * So it would consist of Y as offset[0] and UV as 359*4882a593Smuzhiyun * offset[1]. Note that offset[0] will generally 360*4882a593Smuzhiyun * be 0. 361*4882a593Smuzhiyun */ 362*4882a593Smuzhiyun __u32 handles[4]; 363*4882a593Smuzhiyun __u32 pitches[4]; /* pitch for each plane */ 364*4882a593Smuzhiyun __u32 offsets[4]; /* offset of each plane */ 365*4882a593Smuzhiyun }; 366*4882a593Smuzhiyun 367*4882a593Smuzhiyun #define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01 368*4882a593Smuzhiyun #define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02 369*4882a593Smuzhiyun #define DRM_MODE_FB_DIRTY_FLAGS 0x03 370*4882a593Smuzhiyun 371*4882a593Smuzhiyun /* 372*4882a593Smuzhiyun * Mark a region of a framebuffer as dirty. 373*4882a593Smuzhiyun * 374*4882a593Smuzhiyun * Some hardware does not automatically update display contents 375*4882a593Smuzhiyun * as a hardware or software draw to a framebuffer. This ioctl 376*4882a593Smuzhiyun * allows userspace to tell the kernel and the hardware what 377*4882a593Smuzhiyun * regions of the framebuffer have changed. 378*4882a593Smuzhiyun * 379*4882a593Smuzhiyun * The kernel or hardware is free to update more then just the 380*4882a593Smuzhiyun * region specified by the clip rects. The kernel or hardware 381*4882a593Smuzhiyun * may also delay and/or coalesce several calls to dirty into a 382*4882a593Smuzhiyun * single update. 383*4882a593Smuzhiyun * 384*4882a593Smuzhiyun * Userspace may annotate the updates, the annotates are a 385*4882a593Smuzhiyun * promise made by the caller that the change is either a copy 386*4882a593Smuzhiyun * of pixels or a fill of a single color in the region specified. 387*4882a593Smuzhiyun * 388*4882a593Smuzhiyun * If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then 389*4882a593Smuzhiyun * the number of updated regions are half of num_clips given, 390*4882a593Smuzhiyun * where the clip rects are paired in src and dst. The width and 391*4882a593Smuzhiyun * height of each one of the pairs must match. 392*4882a593Smuzhiyun * 393*4882a593Smuzhiyun * If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller 394*4882a593Smuzhiyun * promises that the region specified of the clip rects is filled 395*4882a593Smuzhiyun * completely with a single color as given in the color argument. 396*4882a593Smuzhiyun */ 397*4882a593Smuzhiyun 398*4882a593Smuzhiyun struct drm_mode_fb_dirty_cmd { 399*4882a593Smuzhiyun __u32 fb_id; 400*4882a593Smuzhiyun __u32 flags; 401*4882a593Smuzhiyun __u32 color; 402*4882a593Smuzhiyun __u32 num_clips; 403*4882a593Smuzhiyun __u64 clips_ptr; 404*4882a593Smuzhiyun }; 405*4882a593Smuzhiyun 406*4882a593Smuzhiyun struct drm_mode_mode_cmd { 407*4882a593Smuzhiyun __u32 connector_id; 408*4882a593Smuzhiyun struct drm_mode_modeinfo mode; 409*4882a593Smuzhiyun }; 410*4882a593Smuzhiyun 411*4882a593Smuzhiyun #define DRM_MODE_CURSOR_BO (1<<0) 412*4882a593Smuzhiyun #define DRM_MODE_CURSOR_MOVE (1<<1) 413*4882a593Smuzhiyun 414*4882a593Smuzhiyun /* 415*4882a593Smuzhiyun * depending on the value in flags diffrent members are used. 416*4882a593Smuzhiyun * 417*4882a593Smuzhiyun * CURSOR_BO uses 418*4882a593Smuzhiyun * crtc 419*4882a593Smuzhiyun * width 420*4882a593Smuzhiyun * height 421*4882a593Smuzhiyun * handle - if 0 turns the cursor of 422*4882a593Smuzhiyun * 423*4882a593Smuzhiyun * CURSOR_MOVE uses 424*4882a593Smuzhiyun * crtc 425*4882a593Smuzhiyun * x 426*4882a593Smuzhiyun * y 427*4882a593Smuzhiyun */ 428*4882a593Smuzhiyun struct drm_mode_cursor { 429*4882a593Smuzhiyun __u32 flags; 430*4882a593Smuzhiyun __u32 crtc_id; 431*4882a593Smuzhiyun __s32 x; 432*4882a593Smuzhiyun __s32 y; 433*4882a593Smuzhiyun __u32 width; 434*4882a593Smuzhiyun __u32 height; 435*4882a593Smuzhiyun /* driver specific handle */ 436*4882a593Smuzhiyun __u32 handle; 437*4882a593Smuzhiyun }; 438*4882a593Smuzhiyun 439*4882a593Smuzhiyun struct drm_mode_cursor2 { 440*4882a593Smuzhiyun __u32 flags; 441*4882a593Smuzhiyun __u32 crtc_id; 442*4882a593Smuzhiyun __s32 x; 443*4882a593Smuzhiyun __s32 y; 444*4882a593Smuzhiyun __u32 width; 445*4882a593Smuzhiyun __u32 height; 446*4882a593Smuzhiyun /* driver specific handle */ 447*4882a593Smuzhiyun __u32 handle; 448*4882a593Smuzhiyun __s32 hot_x; 449*4882a593Smuzhiyun __s32 hot_y; 450*4882a593Smuzhiyun }; 451*4882a593Smuzhiyun 452*4882a593Smuzhiyun struct drm_mode_crtc_lut { 453*4882a593Smuzhiyun __u32 crtc_id; 454*4882a593Smuzhiyun __u32 gamma_size; 455*4882a593Smuzhiyun 456*4882a593Smuzhiyun /* pointers to arrays */ 457*4882a593Smuzhiyun __u64 red; 458*4882a593Smuzhiyun __u64 green; 459*4882a593Smuzhiyun __u64 blue; 460*4882a593Smuzhiyun }; 461*4882a593Smuzhiyun 462*4882a593Smuzhiyun #define DRM_MODE_PAGE_FLIP_EVENT 0x01 463*4882a593Smuzhiyun #define DRM_MODE_PAGE_FLIP_ASYNC 0x02 464*4882a593Smuzhiyun #define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT|DRM_MODE_PAGE_FLIP_ASYNC) 465*4882a593Smuzhiyun 466*4882a593Smuzhiyun /* 467*4882a593Smuzhiyun * Request a page flip on the specified crtc. 468*4882a593Smuzhiyun * 469*4882a593Smuzhiyun * This ioctl will ask KMS to schedule a page flip for the specified 470*4882a593Smuzhiyun * crtc. Once any pending rendering targeting the specified fb (as of 471*4882a593Smuzhiyun * ioctl time) has completed, the crtc will be reprogrammed to display 472*4882a593Smuzhiyun * that fb after the next vertical refresh. The ioctl returns 473*4882a593Smuzhiyun * immediately, but subsequent rendering to the current fb will block 474*4882a593Smuzhiyun * in the execbuffer ioctl until the page flip happens. If a page 475*4882a593Smuzhiyun * flip is already pending as the ioctl is called, EBUSY will be 476*4882a593Smuzhiyun * returned. 477*4882a593Smuzhiyun * 478*4882a593Smuzhiyun * The ioctl supports one flag, DRM_MODE_PAGE_FLIP_EVENT, which will 479*4882a593Smuzhiyun * request that drm sends back a vblank event (see drm.h: struct 480*4882a593Smuzhiyun * drm_event_vblank) when the page flip is done. The user_data field 481*4882a593Smuzhiyun * passed in with this ioctl will be returned as the user_data field 482*4882a593Smuzhiyun * in the vblank event struct. 483*4882a593Smuzhiyun * 484*4882a593Smuzhiyun * The reserved field must be zero until we figure out something 485*4882a593Smuzhiyun * clever to use it for. 486*4882a593Smuzhiyun */ 487*4882a593Smuzhiyun 488*4882a593Smuzhiyun struct drm_mode_crtc_page_flip { 489*4882a593Smuzhiyun __u32 crtc_id; 490*4882a593Smuzhiyun __u32 fb_id; 491*4882a593Smuzhiyun __u32 flags; 492*4882a593Smuzhiyun __u32 reserved; 493*4882a593Smuzhiyun __u64 user_data; 494*4882a593Smuzhiyun }; 495*4882a593Smuzhiyun 496*4882a593Smuzhiyun /* create a dumb scanout buffer */ 497*4882a593Smuzhiyun struct drm_mode_create_dumb { 498*4882a593Smuzhiyun __u32 height; 499*4882a593Smuzhiyun __u32 width; 500*4882a593Smuzhiyun __u32 bpp; 501*4882a593Smuzhiyun __u32 flags; 502*4882a593Smuzhiyun /* handle, pitch, size will be returned */ 503*4882a593Smuzhiyun __u32 handle; 504*4882a593Smuzhiyun __u32 pitch; 505*4882a593Smuzhiyun __u64 size; 506*4882a593Smuzhiyun }; 507*4882a593Smuzhiyun 508*4882a593Smuzhiyun /* set up for mmap of a dumb scanout buffer */ 509*4882a593Smuzhiyun struct drm_mode_map_dumb { 510*4882a593Smuzhiyun /** Handle for the object being mapped. */ 511*4882a593Smuzhiyun __u32 handle; 512*4882a593Smuzhiyun __u32 pad; 513*4882a593Smuzhiyun /** 514*4882a593Smuzhiyun * Fake offset to use for subsequent mmap call 515*4882a593Smuzhiyun * 516*4882a593Smuzhiyun * This is a fixed-size type for 32/64 compatibility. 517*4882a593Smuzhiyun */ 518*4882a593Smuzhiyun __u64 offset; 519*4882a593Smuzhiyun }; 520*4882a593Smuzhiyun 521*4882a593Smuzhiyun struct drm_mode_destroy_dumb { 522*4882a593Smuzhiyun __u32 handle; 523*4882a593Smuzhiyun }; 524*4882a593Smuzhiyun 525*4882a593Smuzhiyun /* page-flip flags are valid, plus: */ 526*4882a593Smuzhiyun #define DRM_MODE_ATOMIC_TEST_ONLY 0x0100 527*4882a593Smuzhiyun #define DRM_MODE_ATOMIC_NONBLOCK 0x0200 528*4882a593Smuzhiyun #define DRM_MODE_ATOMIC_ALLOW_MODESET 0x0400 529*4882a593Smuzhiyun 530*4882a593Smuzhiyun #define DRM_MODE_ATOMIC_FLAGS (\ 531*4882a593Smuzhiyun DRM_MODE_PAGE_FLIP_EVENT |\ 532*4882a593Smuzhiyun DRM_MODE_PAGE_FLIP_ASYNC |\ 533*4882a593Smuzhiyun DRM_MODE_ATOMIC_TEST_ONLY |\ 534*4882a593Smuzhiyun DRM_MODE_ATOMIC_NONBLOCK |\ 535*4882a593Smuzhiyun DRM_MODE_ATOMIC_ALLOW_MODESET) 536*4882a593Smuzhiyun 537*4882a593Smuzhiyun struct drm_mode_atomic { 538*4882a593Smuzhiyun __u32 flags; 539*4882a593Smuzhiyun __u32 count_objs; 540*4882a593Smuzhiyun __u64 objs_ptr; 541*4882a593Smuzhiyun __u64 count_props_ptr; 542*4882a593Smuzhiyun __u64 props_ptr; 543*4882a593Smuzhiyun __u64 prop_values_ptr; 544*4882a593Smuzhiyun __u64 reserved; 545*4882a593Smuzhiyun __u64 user_data; 546*4882a593Smuzhiyun }; 547*4882a593Smuzhiyun 548*4882a593Smuzhiyun /** 549*4882a593Smuzhiyun * Create a new 'blob' data property, copying length bytes from data pointer, 550*4882a593Smuzhiyun * and returning new blob ID. 551*4882a593Smuzhiyun */ 552*4882a593Smuzhiyun struct drm_mode_create_blob { 553*4882a593Smuzhiyun /** Pointer to data to copy. */ 554*4882a593Smuzhiyun __u64 data; 555*4882a593Smuzhiyun /** Length of data to copy. */ 556*4882a593Smuzhiyun __u32 length; 557*4882a593Smuzhiyun /** Return: new property ID. */ 558*4882a593Smuzhiyun __u32 blob_id; 559*4882a593Smuzhiyun }; 560*4882a593Smuzhiyun 561*4882a593Smuzhiyun /** 562*4882a593Smuzhiyun * Destroy a user-created blob property. 563*4882a593Smuzhiyun */ 564*4882a593Smuzhiyun struct drm_mode_destroy_blob { 565*4882a593Smuzhiyun __u32 blob_id; 566*4882a593Smuzhiyun }; 567*4882a593Smuzhiyun 568*4882a593Smuzhiyun #endif 569