1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2016 Rockchip Electronics Co. LTD 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Licensed under the Apache License, Version 2.0 (the "License"); 5*4882a593Smuzhiyun * you may not use this file except in compliance with the License. 6*4882a593Smuzhiyun * You may obtain a copy of the License at 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * http://www.apache.org/licenses/LICENSE-2.0 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Unless required by applicable law or agreed to in writing, software 11*4882a593Smuzhiyun * distributed under the License is distributed on an "AS IS" BASIS, 12*4882a593Smuzhiyun * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13*4882a593Smuzhiyun * See the License for the specific language governing permissions and 14*4882a593Smuzhiyun * limitations under the License. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifndef __MPP_RC_DEFS_H__ 18*4882a593Smuzhiyun #define __MPP_RC_DEFS_H__ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #include "rk_venc_ref.h" 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define MAX_CPB_REFS (8) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun typedef enum EncFrmType_e { 25*4882a593Smuzhiyun INTER_P_FRAME = 0, 26*4882a593Smuzhiyun INTER_B_FRAME = 1, 27*4882a593Smuzhiyun INTRA_FRAME = 2, 28*4882a593Smuzhiyun INTER_VI_FRAME = 3, 29*4882a593Smuzhiyun INTRA_RFH_FRAME = 4, 30*4882a593Smuzhiyun } EncFrmType; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* 33*4882a593Smuzhiyun * EncFrmStatus controls record the encoding frame status and also control 34*4882a593Smuzhiyun * work flow of encoder. It is the communicat channel between encoder implement 35*4882a593Smuzhiyun * module, rate control module and hardware module. 36*4882a593Smuzhiyun * 37*4882a593Smuzhiyun * bit 0 ~ 31 frame status 38*4882a593Smuzhiyun * 0 ~ 15 current frame status 39*4882a593Smuzhiyun * 16 ~ 31 reference frame status 40*4882a593Smuzhiyun * bit 32 ~ 63 encoding flow control 41*4882a593Smuzhiyun */ 42*4882a593Smuzhiyun typedef union EncFrmStatus_u { 43*4882a593Smuzhiyun struct { 44*4882a593Smuzhiyun /* 45*4882a593Smuzhiyun * bit 0 ~ 31 frame status 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun /* status flag */ 48*4882a593Smuzhiyun RK_U32 valid : 1; 49*4882a593Smuzhiyun /* 50*4882a593Smuzhiyun * 0 - write the reconstructed frame pixel to memory 51*4882a593Smuzhiyun * 1 - do not write the reconstructed frame pixel to memory 52*4882a593Smuzhiyun */ 53*4882a593Smuzhiyun RK_U32 non_recn : 1; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* 56*4882a593Smuzhiyun * 0 - normal frame and normal dpb management 57*4882a593Smuzhiyun * 1 - save recon frame as first pass extra frame. Used in two pass mode 58*4882a593Smuzhiyun */ 59*4882a593Smuzhiyun RK_U32 save_pass1 : 1; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* 62*4882a593Smuzhiyun * 0 - use normal input source frame as input 63*4882a593Smuzhiyun * 1 - use the previously stored first pass recon frame as input frame 64*4882a593Smuzhiyun */ 65*4882a593Smuzhiyun RK_U32 use_pass1 : 1; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* reference status flag */ 68*4882a593Smuzhiyun /* 69*4882a593Smuzhiyun * 0 - inter frame 70*4882a593Smuzhiyun * 1 - intra frame 71*4882a593Smuzhiyun */ 72*4882a593Smuzhiyun RK_U32 is_intra : 1; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* 75*4882a593Smuzhiyun * Valid when is_intra is true 76*4882a593Smuzhiyun * 0 - normal intra frame 77*4882a593Smuzhiyun * 1 - IDR frame 78*4882a593Smuzhiyun */ 79*4882a593Smuzhiyun RK_U32 is_idr : 1; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* 82*4882a593Smuzhiyun * 0 - mark as reference frame 83*4882a593Smuzhiyun * 1 - mark as non-refernce frame 84*4882a593Smuzhiyun */ 85*4882a593Smuzhiyun RK_U32 is_non_ref : 1; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* 88*4882a593Smuzhiyun * Valid when is_non_ref is false 89*4882a593Smuzhiyun * 0 - mark as short-term reference frame 90*4882a593Smuzhiyun * 1 - mark as long-term refernce frame 91*4882a593Smuzhiyun */ 92*4882a593Smuzhiyun RK_U32 is_lt_ref : 1; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* bit 8 - 15 */ 95*4882a593Smuzhiyun RK_U32 lt_idx : 4; 96*4882a593Smuzhiyun RK_U32 temporal_id : 4; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* distance between current frame and reference frame */ 99*4882a593Smuzhiyun MppEncRefMode ref_mode : 6; 100*4882a593Smuzhiyun RK_S32 ref_arg : 8; 101*4882a593Smuzhiyun RK_S32 ref_dist : 2; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* 104*4882a593Smuzhiyun * bit 32 ~ 63 encoder flow control flags 105*4882a593Smuzhiyun */ 106*4882a593Smuzhiyun /* 107*4882a593Smuzhiyun * 0 - normal frame encoding 108*4882a593Smuzhiyun * 1 - current frame will be dropped 109*4882a593Smuzhiyun */ 110*4882a593Smuzhiyun RK_U32 drop : 1; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* 113*4882a593Smuzhiyun * 0 - rate control module does not change frame type parameter 114*4882a593Smuzhiyun * 1 - rate control module changes frame type parameter reencode is needed 115*4882a593Smuzhiyun * to reprocess the dpb process. Also this means dpb module will follow 116*4882a593Smuzhiyun * the frame status parameter provided by rate control module. 117*4882a593Smuzhiyun */ 118*4882a593Smuzhiyun RK_U32 re_dpb_proc : 1; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* 121*4882a593Smuzhiyun * 0 - current frame encoding is in normal flow 122*4882a593Smuzhiyun * 1 - current frame encoding is in reencode flow 123*4882a593Smuzhiyun */ 124*4882a593Smuzhiyun RK_U32 reencode : 1; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun /* 127*4882a593Smuzhiyun * When true current frame size is super large then the frame should be reencoded. 128*4882a593Smuzhiyun */ 129*4882a593Smuzhiyun RK_U32 super_frame : 1; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun /* 132*4882a593Smuzhiyun * When true currnet frame is force to encoded as software skip frame 133*4882a593Smuzhiyun */ 134*4882a593Smuzhiyun RK_U32 force_pskip : 1; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun /* 137*4882a593Smuzhiyun * Current frame is intra refresh frame 138*4882a593Smuzhiyun */ 139*4882a593Smuzhiyun RK_U32 is_i_refresh : 1; 140*4882a593Smuzhiyun /* 141*4882a593Smuzhiyun * Current frame needs add recovery point prefix 142*4882a593Smuzhiyun */ 143*4882a593Smuzhiyun RK_U32 is_i_recovery : 1; 144*4882a593Smuzhiyun RK_U32 reserved1 : 1; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun /* reencode times */ 147*4882a593Smuzhiyun RK_U32 reencode_times : 8; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun /* sequential index for each frame */ 150*4882a593Smuzhiyun RK_U32 seq_idx : 16; 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun RK_U64 val; 153*4882a593Smuzhiyun } EncFrmStatus; 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun typedef struct EncCpbStatus_t { 156*4882a593Smuzhiyun RK_S32 seq_idx; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun EncFrmStatus curr; 159*4882a593Smuzhiyun EncFrmStatus refr; 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun /* initial cpb status for current frame encoding */ 162*4882a593Smuzhiyun EncFrmStatus init[MAX_CPB_REFS]; 163*4882a593Smuzhiyun /* final cpb status after current frame encoding */ 164*4882a593Smuzhiyun EncFrmStatus final[MAX_CPB_REFS]; 165*4882a593Smuzhiyun } EncCpbStatus; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun #define ENC_RC_FORCE_QP (0x00000001) 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun typedef struct EncRcForceCfg_t { 170*4882a593Smuzhiyun RK_U32 force_flag; 171*4882a593Smuzhiyun RK_S32 force_qp; 172*4882a593Smuzhiyun RK_U32 reserve[6]; 173*4882a593Smuzhiyun } EncRcForceCfg; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun /* 176*4882a593Smuzhiyun * communication channel between rc / hal / hardware 177*4882a593Smuzhiyun * 178*4882a593Smuzhiyun * rc -> hal bit_target / bit_max / bit_min 179*4882a593Smuzhiyun * hal -> hw quality_target / quality_max / quality_min 180*4882a593Smuzhiyun * hw -> rc / hal bit_real / quality_real / madi / madp 181*4882a593Smuzhiyun */ 182*4882a593Smuzhiyun typedef struct EncRcCommonInfo_t { 183*4882a593Smuzhiyun EncFrmType frame_type; 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun /* rc to hal */ 186*4882a593Smuzhiyun RK_S32 bit_target; 187*4882a593Smuzhiyun RK_S32 bit_max; 188*4882a593Smuzhiyun RK_S32 bit_min; 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun RK_S32 quality_target; 191*4882a593Smuzhiyun RK_S32 quality_max; 192*4882a593Smuzhiyun RK_S32 quality_min; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun /* rc from hardware */ 195*4882a593Smuzhiyun RK_S32 bit_real; 196*4882a593Smuzhiyun RK_S32 quality_real; 197*4882a593Smuzhiyun RK_S32 madi; 198*4882a593Smuzhiyun RK_S32 madp; 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun RK_U32 iblk4_prop; // scale 256 201*4882a593Smuzhiyun RK_S32 reserve[15]; 202*4882a593Smuzhiyun } EncRcTaskInfo; 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun typedef struct EncRcTask_s { 205*4882a593Smuzhiyun EncCpbStatus cpb; 206*4882a593Smuzhiyun EncFrmStatus frm; 207*4882a593Smuzhiyun EncRcTaskInfo info; 208*4882a593Smuzhiyun EncRcForceCfg force; 209*4882a593Smuzhiyun MppFrame frame; 210*4882a593Smuzhiyun } EncRcTask; 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun #endif /* __MPP_RC_DEFS_H__ */ 213