1*4882a593Smuzhiyun /******************************************************************************* 2*4882a593Smuzhiyun * Copyright (c) 2008-2017 The Khronos Group Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and/or associated documentation files (the 6*4882a593Smuzhiyun * "Materials"), to deal in the Materials without restriction, including 7*4882a593Smuzhiyun * without limitation the rights to use, copy, modify, merge, publish, 8*4882a593Smuzhiyun * distribute, sublicense, and/or sell copies of the Materials, and to 9*4882a593Smuzhiyun * permit persons to whom the Materials are furnished to do so, subject to 10*4882a593Smuzhiyun * the following conditions: 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included 13*4882a593Smuzhiyun * in all copies or substantial portions of the Materials. 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * MODIFICATIONS TO THIS FILE MAY MEAN IT NO LONGER ACCURATELY REFLECTS 16*4882a593Smuzhiyun * KHRONOS STANDARDS. THE UNMODIFIED, NORMATIVE VERSIONS OF KHRONOS 17*4882a593Smuzhiyun * SPECIFICATIONS AND HEADER INFORMATION ARE LOCATED AT 18*4882a593Smuzhiyun * https://www.khronos.org/registry/ 19*4882a593Smuzhiyun * 20*4882a593Smuzhiyun * THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23*4882a593Smuzhiyun * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 24*4882a593Smuzhiyun * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25*4882a593Smuzhiyun * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26*4882a593Smuzhiyun * MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS. 27*4882a593Smuzhiyun ******************************************************************************/ 28*4882a593Smuzhiyun /*****************************************************************************\ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun Copyright (c) 2013-2017 Intel Corporation All Rights Reserved. 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun THESE MATERIALS ARE PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33*4882a593Smuzhiyun "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34*4882a593Smuzhiyun LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 35*4882a593Smuzhiyun A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR ITS 36*4882a593Smuzhiyun CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 37*4882a593Smuzhiyun EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 38*4882a593Smuzhiyun PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 39*4882a593Smuzhiyun PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 40*4882a593Smuzhiyun OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR TORT (INCLUDING 41*4882a593Smuzhiyun NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THESE 42*4882a593Smuzhiyun MATERIALS, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun File Name: cl_ext_intel.h 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun Abstract: 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun Notes: 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun \*****************************************************************************/ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #ifndef __CL_EXT_INTEL_H 53*4882a593Smuzhiyun #define __CL_EXT_INTEL_H 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #ifdef __APPLE__ 56*4882a593Smuzhiyun #include <OpenCL/cl.h> 57*4882a593Smuzhiyun #include <OpenCL/cl_platform.h> 58*4882a593Smuzhiyun #else 59*4882a593Smuzhiyun #include <CL/cl.h> 60*4882a593Smuzhiyun #include <CL/cl_platform.h> 61*4882a593Smuzhiyun #endif 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #ifdef __cplusplus 64*4882a593Smuzhiyun extern "C" { 65*4882a593Smuzhiyun #endif 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /*************************************** 68*4882a593Smuzhiyun * cl_intel_thread_local_exec extension * 69*4882a593Smuzhiyun ****************************************/ 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define cl_intel_thread_local_exec 1 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define CL_QUEUE_THREAD_LOCAL_EXEC_ENABLE_INTEL (((cl_bitfield)1) << 31) 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /*********************************************** 76*4882a593Smuzhiyun * cl_intel_device_partition_by_names extension * 77*4882a593Smuzhiyun ************************************************/ 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define cl_intel_device_partition_by_names 1 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define CL_DEVICE_PARTITION_BY_NAMES_INTEL 0x4052 82*4882a593Smuzhiyun #define CL_PARTITION_BY_NAMES_LIST_END_INTEL -1 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /************************************************ 85*4882a593Smuzhiyun * cl_intel_accelerator extension * 86*4882a593Smuzhiyun * cl_intel_motion_estimation extension * 87*4882a593Smuzhiyun * cl_intel_advanced_motion_estimation extension * 88*4882a593Smuzhiyun *************************************************/ 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define cl_intel_accelerator 1 91*4882a593Smuzhiyun #define cl_intel_motion_estimation 1 92*4882a593Smuzhiyun #define cl_intel_advanced_motion_estimation 1 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun typedef struct _cl_accelerator_intel* cl_accelerator_intel; 95*4882a593Smuzhiyun typedef cl_uint cl_accelerator_type_intel; 96*4882a593Smuzhiyun typedef cl_uint cl_accelerator_info_intel; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun typedef struct _cl_motion_estimation_desc_intel { 99*4882a593Smuzhiyun cl_uint mb_block_type; 100*4882a593Smuzhiyun cl_uint subpixel_mode; 101*4882a593Smuzhiyun cl_uint sad_adjust_mode; 102*4882a593Smuzhiyun cl_uint search_path_type; 103*4882a593Smuzhiyun } cl_motion_estimation_desc_intel; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* error codes */ 106*4882a593Smuzhiyun #define CL_INVALID_ACCELERATOR_INTEL -1094 107*4882a593Smuzhiyun #define CL_INVALID_ACCELERATOR_TYPE_INTEL -1095 108*4882a593Smuzhiyun #define CL_INVALID_ACCELERATOR_DESCRIPTOR_INTEL -1096 109*4882a593Smuzhiyun #define CL_ACCELERATOR_TYPE_NOT_SUPPORTED_INTEL -1097 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /* cl_accelerator_type_intel */ 112*4882a593Smuzhiyun #define CL_ACCELERATOR_TYPE_MOTION_ESTIMATION_INTEL 0x0 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /* cl_accelerator_info_intel */ 115*4882a593Smuzhiyun #define CL_ACCELERATOR_DESCRIPTOR_INTEL 0x4090 116*4882a593Smuzhiyun #define CL_ACCELERATOR_REFERENCE_COUNT_INTEL 0x4091 117*4882a593Smuzhiyun #define CL_ACCELERATOR_CONTEXT_INTEL 0x4092 118*4882a593Smuzhiyun #define CL_ACCELERATOR_TYPE_INTEL 0x4093 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* cl_motion_detect_desc_intel flags */ 121*4882a593Smuzhiyun #define CL_ME_MB_TYPE_16x16_INTEL 0x0 122*4882a593Smuzhiyun #define CL_ME_MB_TYPE_8x8_INTEL 0x1 123*4882a593Smuzhiyun #define CL_ME_MB_TYPE_4x4_INTEL 0x2 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun #define CL_ME_SUBPIXEL_MODE_INTEGER_INTEL 0x0 126*4882a593Smuzhiyun #define CL_ME_SUBPIXEL_MODE_HPEL_INTEL 0x1 127*4882a593Smuzhiyun #define CL_ME_SUBPIXEL_MODE_QPEL_INTEL 0x2 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #define CL_ME_SAD_ADJUST_MODE_NONE_INTEL 0x0 130*4882a593Smuzhiyun #define CL_ME_SAD_ADJUST_MODE_HAAR_INTEL 0x1 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #define CL_ME_SEARCH_PATH_RADIUS_2_2_INTEL 0x0 133*4882a593Smuzhiyun #define CL_ME_SEARCH_PATH_RADIUS_4_4_INTEL 0x1 134*4882a593Smuzhiyun #define CL_ME_SEARCH_PATH_RADIUS_16_12_INTEL 0x5 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #define CL_ME_SKIP_BLOCK_TYPE_16x16_INTEL 0x0 137*4882a593Smuzhiyun #define CL_ME_CHROMA_INTRA_PREDICT_ENABLED_INTEL 0x1 138*4882a593Smuzhiyun #define CL_ME_LUMA_INTRA_PREDICT_ENABLED_INTEL 0x2 139*4882a593Smuzhiyun #define CL_ME_SKIP_BLOCK_TYPE_8x8_INTEL 0x4 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #define CL_ME_FORWARD_INPUT_MODE_INTEL 0x1 142*4882a593Smuzhiyun #define CL_ME_BACKWARD_INPUT_MODE_INTEL 0x2 143*4882a593Smuzhiyun #define CL_ME_BIDIRECTION_INPUT_MODE_INTEL 0x3 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun #define CL_ME_BIDIR_WEIGHT_QUARTER_INTEL 16 146*4882a593Smuzhiyun #define CL_ME_BIDIR_WEIGHT_THIRD_INTEL 21 147*4882a593Smuzhiyun #define CL_ME_BIDIR_WEIGHT_HALF_INTEL 32 148*4882a593Smuzhiyun #define CL_ME_BIDIR_WEIGHT_TWO_THIRD_INTEL 43 149*4882a593Smuzhiyun #define CL_ME_BIDIR_WEIGHT_THREE_QUARTER_INTEL 48 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun #define CL_ME_COST_PENALTY_NONE_INTEL 0x0 152*4882a593Smuzhiyun #define CL_ME_COST_PENALTY_LOW_INTEL 0x1 153*4882a593Smuzhiyun #define CL_ME_COST_PENALTY_NORMAL_INTEL 0x2 154*4882a593Smuzhiyun #define CL_ME_COST_PENALTY_HIGH_INTEL 0x3 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun #define CL_ME_COST_PRECISION_QPEL_INTEL 0x0 157*4882a593Smuzhiyun #define CL_ME_COST_PRECISION_HPEL_INTEL 0x1 158*4882a593Smuzhiyun #define CL_ME_COST_PRECISION_PEL_INTEL 0x2 159*4882a593Smuzhiyun #define CL_ME_COST_PRECISION_DPEL_INTEL 0x3 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun #define CL_ME_LUMA_PREDICTOR_MODE_VERTICAL_INTEL 0x0 162*4882a593Smuzhiyun #define CL_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_INTEL 0x1 163*4882a593Smuzhiyun #define CL_ME_LUMA_PREDICTOR_MODE_DC_INTEL 0x2 164*4882a593Smuzhiyun #define CL_ME_LUMA_PREDICTOR_MODE_DIAGONAL_DOWN_LEFT_INTEL 0x3 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun #define CL_ME_LUMA_PREDICTOR_MODE_DIAGONAL_DOWN_RIGHT_INTEL 0x4 167*4882a593Smuzhiyun #define CL_ME_LUMA_PREDICTOR_MODE_PLANE_INTEL 0x4 168*4882a593Smuzhiyun #define CL_ME_LUMA_PREDICTOR_MODE_VERTICAL_RIGHT_INTEL 0x5 169*4882a593Smuzhiyun #define CL_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_DOWN_INTEL 0x6 170*4882a593Smuzhiyun #define CL_ME_LUMA_PREDICTOR_MODE_VERTICAL_LEFT_INTEL 0x7 171*4882a593Smuzhiyun #define CL_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_UP_INTEL 0x8 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun #define CL_ME_CHROMA_PREDICTOR_MODE_DC_INTEL 0x0 174*4882a593Smuzhiyun #define CL_ME_CHROMA_PREDICTOR_MODE_HORIZONTAL_INTEL 0x1 175*4882a593Smuzhiyun #define CL_ME_CHROMA_PREDICTOR_MODE_VERTICAL_INTEL 0x2 176*4882a593Smuzhiyun #define CL_ME_CHROMA_PREDICTOR_MODE_PLANE_INTEL 0x3 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun /* cl_device_info */ 179*4882a593Smuzhiyun #define CL_DEVICE_ME_VERSION_INTEL 0x407E 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun #define CL_ME_VERSION_LEGACY_INTEL 0x0 182*4882a593Smuzhiyun #define CL_ME_VERSION_ADVANCED_VER_1_INTEL 0x1 183*4882a593Smuzhiyun #define CL_ME_VERSION_ADVANCED_VER_2_INTEL 0x2 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun extern CL_API_ENTRY cl_accelerator_intel CL_API_CALL 186*4882a593Smuzhiyun clCreateAcceleratorINTEL( 187*4882a593Smuzhiyun cl_context /* context */, 188*4882a593Smuzhiyun cl_accelerator_type_intel /* accelerator_type */, 189*4882a593Smuzhiyun size_t /* descriptor_size */, 190*4882a593Smuzhiyun const void* /* descriptor */, 191*4882a593Smuzhiyun cl_int* /* errcode_ret */) CL_EXT_SUFFIX__VERSION_1_2; 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun typedef CL_API_ENTRY cl_accelerator_intel (CL_API_CALL *clCreateAcceleratorINTEL_fn)( 194*4882a593Smuzhiyun cl_context /* context */, 195*4882a593Smuzhiyun cl_accelerator_type_intel /* accelerator_type */, 196*4882a593Smuzhiyun size_t /* descriptor_size */, 197*4882a593Smuzhiyun const void* /* descriptor */, 198*4882a593Smuzhiyun cl_int* /* errcode_ret */) CL_EXT_SUFFIX__VERSION_1_2; 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun extern CL_API_ENTRY cl_int CL_API_CALL 201*4882a593Smuzhiyun clGetAcceleratorInfoINTEL( 202*4882a593Smuzhiyun cl_accelerator_intel /* accelerator */, 203*4882a593Smuzhiyun cl_accelerator_info_intel /* param_name */, 204*4882a593Smuzhiyun size_t /* param_value_size */, 205*4882a593Smuzhiyun void* /* param_value */, 206*4882a593Smuzhiyun size_t* /* param_value_size_ret */) CL_EXT_SUFFIX__VERSION_1_2; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun typedef CL_API_ENTRY cl_int (CL_API_CALL *clGetAcceleratorInfoINTEL_fn)( 209*4882a593Smuzhiyun cl_accelerator_intel /* accelerator */, 210*4882a593Smuzhiyun cl_accelerator_info_intel /* param_name */, 211*4882a593Smuzhiyun size_t /* param_value_size */, 212*4882a593Smuzhiyun void* /* param_value */, 213*4882a593Smuzhiyun size_t* /* param_value_size_ret */) CL_EXT_SUFFIX__VERSION_1_2; 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun extern CL_API_ENTRY cl_int CL_API_CALL 216*4882a593Smuzhiyun clRetainAcceleratorINTEL( 217*4882a593Smuzhiyun cl_accelerator_intel /* accelerator */) CL_EXT_SUFFIX__VERSION_1_2; 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun typedef CL_API_ENTRY cl_int (CL_API_CALL *clRetainAcceleratorINTEL_fn)( 220*4882a593Smuzhiyun cl_accelerator_intel /* accelerator */) CL_EXT_SUFFIX__VERSION_1_2; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun extern CL_API_ENTRY cl_int CL_API_CALL 223*4882a593Smuzhiyun clReleaseAcceleratorINTEL( 224*4882a593Smuzhiyun cl_accelerator_intel /* accelerator */) CL_EXT_SUFFIX__VERSION_1_2; 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun typedef CL_API_ENTRY cl_int (CL_API_CALL *clReleaseAcceleratorINTEL_fn)( 227*4882a593Smuzhiyun cl_accelerator_intel /* accelerator */) CL_EXT_SUFFIX__VERSION_1_2; 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun /****************************************** 230*4882a593Smuzhiyun * cl_intel_simultaneous_sharing extension * 231*4882a593Smuzhiyun *******************************************/ 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun #define cl_intel_simultaneous_sharing 1 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun #define CL_DEVICE_SIMULTANEOUS_INTEROPS_INTEL 0x4104 236*4882a593Smuzhiyun #define CL_DEVICE_NUM_SIMULTANEOUS_INTEROPS_INTEL 0x4105 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun /*********************************** 239*4882a593Smuzhiyun * cl_intel_egl_image_yuv extension * 240*4882a593Smuzhiyun ************************************/ 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun #define cl_intel_egl_image_yuv 1 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun #define CL_EGL_YUV_PLANE_INTEL 0x4107 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun /******************************** 247*4882a593Smuzhiyun * cl_intel_packed_yuv extension * 248*4882a593Smuzhiyun *********************************/ 249*4882a593Smuzhiyun 250*4882a593Smuzhiyun #define cl_intel_packed_yuv 1 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun #define CL_YUYV_INTEL 0x4076 253*4882a593Smuzhiyun #define CL_UYVY_INTEL 0x4077 254*4882a593Smuzhiyun #define CL_YVYU_INTEL 0x4078 255*4882a593Smuzhiyun #define CL_VYUY_INTEL 0x4079 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun /******************************************** 258*4882a593Smuzhiyun * cl_intel_required_subgroup_size extension * 259*4882a593Smuzhiyun *********************************************/ 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun #define cl_intel_required_subgroup_size 1 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun #define CL_DEVICE_SUB_GROUP_SIZES_INTEL 0x4108 264*4882a593Smuzhiyun #define CL_KERNEL_SPILL_MEM_SIZE_INTEL 0x4109 265*4882a593Smuzhiyun #define CL_KERNEL_COMPILE_SUB_GROUP_SIZE_INTEL 0x410A 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun /**************************************** 268*4882a593Smuzhiyun * cl_intel_driver_diagnostics extension * 269*4882a593Smuzhiyun *****************************************/ 270*4882a593Smuzhiyun 271*4882a593Smuzhiyun #define cl_intel_driver_diagnostics 1 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun typedef cl_uint cl_diagnostics_verbose_level; 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun #define CL_CONTEXT_SHOW_DIAGNOSTICS_INTEL 0x4106 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun #define CL_CONTEXT_DIAGNOSTICS_LEVEL_ALL_INTEL ( 0xff ) 278*4882a593Smuzhiyun #define CL_CONTEXT_DIAGNOSTICS_LEVEL_GOOD_INTEL ( 1 ) 279*4882a593Smuzhiyun #define CL_CONTEXT_DIAGNOSTICS_LEVEL_BAD_INTEL ( 1 << 1 ) 280*4882a593Smuzhiyun #define CL_CONTEXT_DIAGNOSTICS_LEVEL_NEUTRAL_INTEL ( 1 << 2 ) 281*4882a593Smuzhiyun 282*4882a593Smuzhiyun /******************************** 283*4882a593Smuzhiyun * cl_intel_planar_yuv extension * 284*4882a593Smuzhiyun *********************************/ 285*4882a593Smuzhiyun 286*4882a593Smuzhiyun #define CL_NV12_INTEL 0x410E 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun #define CL_MEM_NO_ACCESS_INTEL ( 1 << 24 ) 289*4882a593Smuzhiyun #define CL_MEM_ACCESS_FLAGS_UNRESTRICTED_INTEL ( 1 << 25 ) 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun #define CL_DEVICE_PLANAR_YUV_MAX_WIDTH_INTEL 0x417E 292*4882a593Smuzhiyun #define CL_DEVICE_PLANAR_YUV_MAX_HEIGHT_INTEL 0x417F 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun /******************************************************* 295*4882a593Smuzhiyun * cl_intel_device_side_avc_motion_estimation extension * 296*4882a593Smuzhiyun ********************************************************/ 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun #define CL_DEVICE_AVC_ME_VERSION_INTEL 0x410B 299*4882a593Smuzhiyun #define CL_DEVICE_AVC_ME_SUPPORTS_TEXTURE_SAMPLER_USE_INTEL 0x410C 300*4882a593Smuzhiyun #define CL_DEVICE_AVC_ME_SUPPORTS_PREEMPTION_INTEL 0x410D 301*4882a593Smuzhiyun 302*4882a593Smuzhiyun #define CL_AVC_ME_VERSION_0_INTEL 0x0; // No support. 303*4882a593Smuzhiyun #define CL_AVC_ME_VERSION_1_INTEL 0x1; // First supported version. 304*4882a593Smuzhiyun 305*4882a593Smuzhiyun #define CL_AVC_ME_MAJOR_16x16_INTEL 0x0 306*4882a593Smuzhiyun #define CL_AVC_ME_MAJOR_16x8_INTEL 0x1 307*4882a593Smuzhiyun #define CL_AVC_ME_MAJOR_8x16_INTEL 0x2 308*4882a593Smuzhiyun #define CL_AVC_ME_MAJOR_8x8_INTEL 0x3 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun #define CL_AVC_ME_MINOR_8x8_INTEL 0x0 311*4882a593Smuzhiyun #define CL_AVC_ME_MINOR_8x4_INTEL 0x1 312*4882a593Smuzhiyun #define CL_AVC_ME_MINOR_4x8_INTEL 0x2 313*4882a593Smuzhiyun #define CL_AVC_ME_MINOR_4x4_INTEL 0x3 314*4882a593Smuzhiyun 315*4882a593Smuzhiyun #define CL_AVC_ME_MAJOR_FORWARD_INTEL 0x0 316*4882a593Smuzhiyun #define CL_AVC_ME_MAJOR_BACKWARD_INTEL 0x1 317*4882a593Smuzhiyun #define CL_AVC_ME_MAJOR_BIDIRECTIONAL_INTEL 0x2 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun #define CL_AVC_ME_PARTITION_MASK_ALL_INTEL 0x0 320*4882a593Smuzhiyun #define CL_AVC_ME_PARTITION_MASK_16x16_INTEL 0x7E 321*4882a593Smuzhiyun #define CL_AVC_ME_PARTITION_MASK_16x8_INTEL 0x7D 322*4882a593Smuzhiyun #define CL_AVC_ME_PARTITION_MASK_8x16_INTEL 0x7B 323*4882a593Smuzhiyun #define CL_AVC_ME_PARTITION_MASK_8x8_INTEL 0x77 324*4882a593Smuzhiyun #define CL_AVC_ME_PARTITION_MASK_8x4_INTEL 0x6F 325*4882a593Smuzhiyun #define CL_AVC_ME_PARTITION_MASK_4x8_INTEL 0x5F 326*4882a593Smuzhiyun #define CL_AVC_ME_PARTITION_MASK_4x4_INTEL 0x3F 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun #define CL_AVC_ME_SEARCH_WINDOW_EXHAUSTIVE_INTEL 0x0 329*4882a593Smuzhiyun #define CL_AVC_ME_SEARCH_WINDOW_SMALL_INTEL 0x1 330*4882a593Smuzhiyun #define CL_AVC_ME_SEARCH_WINDOW_TINY_INTEL 0x2 331*4882a593Smuzhiyun #define CL_AVC_ME_SEARCH_WINDOW_EXTRA_TINY_INTEL 0x3 332*4882a593Smuzhiyun #define CL_AVC_ME_SEARCH_WINDOW_DIAMOND_INTEL 0x4 333*4882a593Smuzhiyun #define CL_AVC_ME_SEARCH_WINDOW_LARGE_DIAMOND_INTEL 0x5 334*4882a593Smuzhiyun #define CL_AVC_ME_SEARCH_WINDOW_RESERVED0_INTEL 0x6 335*4882a593Smuzhiyun #define CL_AVC_ME_SEARCH_WINDOW_RESERVED1_INTEL 0x7 336*4882a593Smuzhiyun #define CL_AVC_ME_SEARCH_WINDOW_CUSTOM_INTEL 0x8 337*4882a593Smuzhiyun #define CL_AVC_ME_SEARCH_WINDOW_16x12_RADIUS_INTEL 0x9 338*4882a593Smuzhiyun #define CL_AVC_ME_SEARCH_WINDOW_4x4_RADIUS_INTEL 0x2 339*4882a593Smuzhiyun #define CL_AVC_ME_SEARCH_WINDOW_2x2_RADIUS_INTEL 0xa 340*4882a593Smuzhiyun 341*4882a593Smuzhiyun #define CL_AVC_ME_SAD_ADJUST_MODE_NONE_INTEL 0x0 342*4882a593Smuzhiyun #define CL_AVC_ME_SAD_ADJUST_MODE_HAAR_INTEL 0x2 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun #define CL_AVC_ME_SUBPIXEL_MODE_INTEGER_INTEL 0x0 345*4882a593Smuzhiyun #define CL_AVC_ME_SUBPIXEL_MODE_HPEL_INTEL 0x1 346*4882a593Smuzhiyun #define CL_AVC_ME_SUBPIXEL_MODE_QPEL_INTEL 0x3 347*4882a593Smuzhiyun 348*4882a593Smuzhiyun #define CL_AVC_ME_COST_PRECISION_QPEL_INTEL 0x0 349*4882a593Smuzhiyun #define CL_AVC_ME_COST_PRECISION_HPEL_INTEL 0x1 350*4882a593Smuzhiyun #define CL_AVC_ME_COST_PRECISION_PEL_INTEL 0x2 351*4882a593Smuzhiyun #define CL_AVC_ME_COST_PRECISION_DPEL_INTEL 0x3 352*4882a593Smuzhiyun 353*4882a593Smuzhiyun #define CL_AVC_ME_BIDIR_WEIGHT_QUARTER_INTEL 0x10 354*4882a593Smuzhiyun #define CL_AVC_ME_BIDIR_WEIGHT_THIRD_INTEL 0x15 355*4882a593Smuzhiyun #define CL_AVC_ME_BIDIR_WEIGHT_HALF_INTEL 0x20 356*4882a593Smuzhiyun #define CL_AVC_ME_BIDIR_WEIGHT_TWO_THIRD_INTEL 0x2B 357*4882a593Smuzhiyun #define CL_AVC_ME_BIDIR_WEIGHT_THREE_QUARTER_INTEL 0x30 358*4882a593Smuzhiyun 359*4882a593Smuzhiyun #define CL_AVC_ME_BORDER_REACHED_LEFT_INTEL 0x0 360*4882a593Smuzhiyun #define CL_AVC_ME_BORDER_REACHED_RIGHT_INTEL 0x2 361*4882a593Smuzhiyun #define CL_AVC_ME_BORDER_REACHED_TOP_INTEL 0x4 362*4882a593Smuzhiyun #define CL_AVC_ME_BORDER_REACHED_BOTTOM_INTEL 0x8 363*4882a593Smuzhiyun 364*4882a593Smuzhiyun #define CL_AVC_ME_SKIP_BLOCK_PARTITION_16x16_INTEL 0x0 365*4882a593Smuzhiyun #define CL_AVC_ME_SKIP_BLOCK_PARTITION_8x8_INTEL 0x4000 366*4882a593Smuzhiyun 367*4882a593Smuzhiyun #define CL_AVC_ME_SKIP_BLOCK_16x16_FORWARD_ENABLE_INTEL ( 0x1 << 24 ) 368*4882a593Smuzhiyun #define CL_AVC_ME_SKIP_BLOCK_16x16_BACKWARD_ENABLE_INTEL ( 0x2 << 24 ) 369*4882a593Smuzhiyun #define CL_AVC_ME_SKIP_BLOCK_16x16_DUAL_ENABLE_INTEL ( 0x3 << 24 ) 370*4882a593Smuzhiyun #define CL_AVC_ME_SKIP_BLOCK_8x8_FORWARD_ENABLE_INTEL ( 0x55 << 24 ) 371*4882a593Smuzhiyun #define CL_AVC_ME_SKIP_BLOCK_8x8_BACKWARD_ENABLE_INTEL ( 0xAA << 24 ) 372*4882a593Smuzhiyun #define CL_AVC_ME_SKIP_BLOCK_8x8_DUAL_ENABLE_INTEL ( 0xFF << 24 ) 373*4882a593Smuzhiyun #define CL_AVC_ME_SKIP_BLOCK_8x8_0_FORWARD_ENABLE_INTEL ( 0x1 << 24 ) 374*4882a593Smuzhiyun #define CL_AVC_ME_SKIP_BLOCK_8x8_0_BACKWARD_ENABLE_INTEL ( 0x2 << 24 ) 375*4882a593Smuzhiyun #define CL_AVC_ME_SKIP_BLOCK_8x8_1_FORWARD_ENABLE_INTEL ( 0x1 << 26 ) 376*4882a593Smuzhiyun #define CL_AVC_ME_SKIP_BLOCK_8x8_1_BACKWARD_ENABLE_INTEL ( 0x2 << 26 ) 377*4882a593Smuzhiyun #define CL_AVC_ME_SKIP_BLOCK_8x8_2_FORWARD_ENABLE_INTEL ( 0x1 << 28 ) 378*4882a593Smuzhiyun #define CL_AVC_ME_SKIP_BLOCK_8x8_2_BACKWARD_ENABLE_INTEL ( 0x2 << 28 ) 379*4882a593Smuzhiyun #define CL_AVC_ME_SKIP_BLOCK_8x8_3_FORWARD_ENABLE_INTEL ( 0x1 << 30 ) 380*4882a593Smuzhiyun #define CL_AVC_ME_SKIP_BLOCK_8x8_3_BACKWARD_ENABLE_INTEL ( 0x2 << 30 ) 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun #define CL_AVC_ME_BLOCK_BASED_SKIP_4x4_INTEL 0x00 383*4882a593Smuzhiyun #define CL_AVC_ME_BLOCK_BASED_SKIP_8x8_INTEL 0x80 384*4882a593Smuzhiyun 385*4882a593Smuzhiyun #define CL_AVC_ME_INTRA_16x16_INTEL 0x0 386*4882a593Smuzhiyun #define CL_AVC_ME_INTRA_8x8_INTEL 0x1 387*4882a593Smuzhiyun #define CL_AVC_ME_INTRA_4x4_INTEL 0x2 388*4882a593Smuzhiyun 389*4882a593Smuzhiyun #define CL_AVC_ME_INTRA_LUMA_PARTITION_MASK_16x16_INTEL 0x6 390*4882a593Smuzhiyun #define CL_AVC_ME_INTRA_LUMA_PARTITION_MASK_8x8_INTEL 0x5 391*4882a593Smuzhiyun #define CL_AVC_ME_INTRA_LUMA_PARTITION_MASK_4x4_INTEL 0x3 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun #define CL_AVC_ME_INTRA_NEIGHBOR_LEFT_MASK_ENABLE_INTEL 0x60 394*4882a593Smuzhiyun #define CL_AVC_ME_INTRA_NEIGHBOR_UPPER_MASK_ENABLE_INTEL 0x10 395*4882a593Smuzhiyun #define CL_AVC_ME_INTRA_NEIGHBOR_UPPER_RIGHT_MASK_ENABLE_INTEL 0x8 396*4882a593Smuzhiyun #define CL_AVC_ME_INTRA_NEIGHBOR_UPPER_LEFT_MASK_ENABLE_INTEL 0x4 397*4882a593Smuzhiyun 398*4882a593Smuzhiyun #define CL_AVC_ME_LUMA_PREDICTOR_MODE_VERTICAL_INTEL 0x0 399*4882a593Smuzhiyun #define CL_AVC_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_INTEL 0x1 400*4882a593Smuzhiyun #define CL_AVC_ME_LUMA_PREDICTOR_MODE_DC_INTEL 0x2 401*4882a593Smuzhiyun #define CL_AVC_ME_LUMA_PREDICTOR_MODE_DIAGONAL_DOWN_LEFT_INTEL 0x3 402*4882a593Smuzhiyun #define CL_AVC_ME_LUMA_PREDICTOR_MODE_DIAGONAL_DOWN_RIGHT_INTEL 0x4 403*4882a593Smuzhiyun #define CL_AVC_ME_LUMA_PREDICTOR_MODE_PLANE_INTEL 0x4 404*4882a593Smuzhiyun #define CL_AVC_ME_LUMA_PREDICTOR_MODE_VERTICAL_RIGHT_INTEL 0x5 405*4882a593Smuzhiyun #define CL_AVC_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_DOWN_INTEL 0x6 406*4882a593Smuzhiyun #define CL_AVC_ME_LUMA_PREDICTOR_MODE_VERTICAL_LEFT_INTEL 0x7 407*4882a593Smuzhiyun #define CL_AVC_ME_LUMA_PREDICTOR_MODE_HORIZONTAL_UP_INTEL 0x8 408*4882a593Smuzhiyun #define CL_AVC_ME_CHROMA_PREDICTOR_MODE_DC_INTEL 0x0 409*4882a593Smuzhiyun #define CL_AVC_ME_CHROMA_PREDICTOR_MODE_HORIZONTAL_INTEL 0x1 410*4882a593Smuzhiyun #define CL_AVC_ME_CHROMA_PREDICTOR_MODE_VERTICAL_INTEL 0x2 411*4882a593Smuzhiyun #define CL_AVC_ME_CHROMA_PREDICTOR_MODE_PLANE_INTEL 0x3 412*4882a593Smuzhiyun 413*4882a593Smuzhiyun #define CL_AVC_ME_FRAME_FORWARD_INTEL 0x1 414*4882a593Smuzhiyun #define CL_AVC_ME_FRAME_BACKWARD_INTEL 0x2 415*4882a593Smuzhiyun #define CL_AVC_ME_FRAME_DUAL_INTEL 0x3 416*4882a593Smuzhiyun 417*4882a593Smuzhiyun #define CL_AVC_ME_SLICE_TYPE_PRED_INTEL 0x0 418*4882a593Smuzhiyun #define CL_AVC_ME_SLICE_TYPE_BPRED_INTEL 0x1 419*4882a593Smuzhiyun #define CL_AVC_ME_SLICE_TYPE_INTRA_INTEL 0x2 420*4882a593Smuzhiyun 421*4882a593Smuzhiyun #define CL_AVC_ME_INTERLACED_SCAN_TOP_FIELD_INTEL 0x0 422*4882a593Smuzhiyun #define CL_AVC_ME_INTERLACED_SCAN_BOTTOM_FIELD_INTEL 0x1 423*4882a593Smuzhiyun 424*4882a593Smuzhiyun #ifdef __cplusplus 425*4882a593Smuzhiyun } 426*4882a593Smuzhiyun #endif 427*4882a593Smuzhiyun 428*4882a593Smuzhiyun #endif /* __CL_EXT_INTEL_H */ 429*4882a593Smuzhiyun 430