1*4882a593Smuzhiyun /* SPDX-License-Identifier: ((GPL-2.0+ WITH Linux-syscall-note) OR MIT) 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright (C) 2019 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _UAPI_RKCIF_CONFIG_H 7*4882a593Smuzhiyun #define _UAPI_RKCIF_CONFIG_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/types.h> 10*4882a593Smuzhiyun #include <linux/v4l2-controls.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define RKCIF_API_VERSION KERNEL_VERSION(0, 1, 0xa) 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define V4L2_EVENT_RESET_DEV 0X1001 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define RKCIF_CMD_GET_CSI_MEMORY_MODE \ 17*4882a593Smuzhiyun _IOR('V', BASE_VIDIOC_PRIVATE + 0, int) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define RKCIF_CMD_SET_CSI_MEMORY_MODE \ 20*4882a593Smuzhiyun _IOW('V', BASE_VIDIOC_PRIVATE + 1, int) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define RKCIF_CMD_GET_SCALE_BLC \ 23*4882a593Smuzhiyun _IOR('V', BASE_VIDIOC_PRIVATE + 2, struct bayer_blc) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define RKCIF_CMD_SET_SCALE_BLC \ 26*4882a593Smuzhiyun _IOW('V', BASE_VIDIOC_PRIVATE + 3, struct bayer_blc) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define RKCIF_CMD_SET_FPS \ 29*4882a593Smuzhiyun _IOW('V', BASE_VIDIOC_PRIVATE + 4, struct rkcif_fps) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define RKCIF_CMD_SET_RESET \ 32*4882a593Smuzhiyun _IOW('V', BASE_VIDIOC_PRIVATE + 6, int) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define RKCIF_CMD_SET_CSI_IDX \ 35*4882a593Smuzhiyun _IOW('V', BASE_VIDIOC_PRIVATE + 7, unsigned int) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* cif memory mode 38*4882a593Smuzhiyun * 0: raw12/raw10/raw8 8bit memory compact 39*4882a593Smuzhiyun * 1: raw12/raw10 16bit memory one pixel 40*4882a593Smuzhiyun * low align for rv1126/rv1109/rk356x 41*4882a593Smuzhiyun * |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| 42*4882a593Smuzhiyun * | -| -| -| -|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| 43*4882a593Smuzhiyun * 2: raw12/raw10 16bit memory one pixel 44*4882a593Smuzhiyun * high align for rv1126/rv1109/rk356x 45*4882a593Smuzhiyun * |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| 46*4882a593Smuzhiyun * |11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| -| -| -| -| 47*4882a593Smuzhiyun * 48*4882a593Smuzhiyun * note: rv1109/rv1126/rk356x dvp only support uncompact mode, 49*4882a593Smuzhiyun * and can be set low align or high align 50*4882a593Smuzhiyun */ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun enum cif_csi_lvds_memory { 53*4882a593Smuzhiyun CSI_LVDS_MEM_COMPACT = 0, 54*4882a593Smuzhiyun CSI_LVDS_MEM_WORD_LOW_ALIGN = 1, 55*4882a593Smuzhiyun CSI_LVDS_MEM_WORD_HIGH_ALIGN = 2, 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* black level for scale image 59*4882a593Smuzhiyun * The sequence of pattern00~03 is the same as the output of sensor bayer 60*4882a593Smuzhiyun */ 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun struct bayer_blc { 63*4882a593Smuzhiyun u8 pattern00; 64*4882a593Smuzhiyun u8 pattern01; 65*4882a593Smuzhiyun u8 pattern02; 66*4882a593Smuzhiyun u8 pattern03; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun struct rkcif_fps { 70*4882a593Smuzhiyun int ch_num; 71*4882a593Smuzhiyun int fps; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #endif 75