1From b92c22b144d063c4436a6693045ceb57d344c495 Mon Sep 17 00:00:00 2001 2From: Claudiu Zissulescu <claziss@synopsys.com> 3Date: Wed, 11 Nov 2020 12:31:10 +0200 4Subject: [PATCH] arc: Refurbish adc/sbc patterns 5 6The adc/sbc patterns were unecessary spliting, remove that and 7associated functions. 8 9gcc/ChangeLog: 10 112020-10-11 Claudiu Zissulescu <claziss@synopsys.com> 12 13 * config/arc/arc-protos.h (arc_scheduling_not_expected): Remove 14 it. 15 (arc_sets_cc_p): Likewise. 16 (arc_need_delay): Likewise. 17 * config/arc/arc.c (arc_sets_cc_p): Likewise. 18 (arc_need_delay): Likewise. 19 (arc_scheduling_not_expected): Likewise. 20 * config/arc/arc.md: Convert adc/sbc patterns to simple 21 instruction definitions. 22 23Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com> 24 25Downloaded from upstream commit 26https://github.com/foss-for-synopsys-dwc-arc-processors/gcc/commit/b92c22b144d063c4436a6693045ceb57d344c495 27 28Signed-off-by: Bernd Kuhls <bernd.kuhls@t-online.de> 29--- 30 gcc/config/arc/arc-protos.h | 3 -- 31 gcc/config/arc/arc.c | 53 --------------------- 32 gcc/config/arc/arc.md | 95 +++++++++++-------------------------- 33 3 files changed, 29 insertions(+), 122 deletions(-) 34 35diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h 36index c72d78e3b9e..de4cf47c818 100644 37--- a/gcc/config/arc/arc-protos.h 38+++ b/gcc/config/arc/arc-protos.h 39@@ -90,10 +90,7 @@ extern void split_subsi (rtx *); 40 extern void arc_split_move (rtx *); 41 extern const char *arc_short_long (rtx_insn *insn, const char *, const char *); 42 extern rtx arc_regno_use_in (unsigned int, rtx); 43-extern bool arc_scheduling_not_expected (void); 44-extern bool arc_sets_cc_p (rtx_insn *insn); 45 extern int arc_label_align (rtx_insn *label); 46-extern bool arc_need_delay (rtx_insn *insn); 47 extern bool arc_text_label (rtx_insn *insn); 48 49 extern bool arc_short_comparison_p (rtx, int); 50diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c 51index 5a7b0cb6696..c3ee9181f93 100644 52--- a/gcc/config/arc/arc.c 53+++ b/gcc/config/arc/arc.c 54@@ -10341,59 +10341,6 @@ arc_attr_type (rtx_insn *insn) 55 return get_attr_type (insn); 56 } 57 58-/* Return true if insn sets the condition codes. */ 59- 60-bool 61-arc_sets_cc_p (rtx_insn *insn) 62-{ 63- if (NONJUMP_INSN_P (insn)) 64- if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (PATTERN (insn))) 65- insn = seq->insn (seq->len () - 1); 66- return arc_attr_type (insn) == TYPE_COMPARE; 67-} 68- 69-/* Return true if INSN is an instruction with a delay slot we may want 70- to fill. */ 71- 72-bool 73-arc_need_delay (rtx_insn *insn) 74-{ 75- rtx_insn *next; 76- 77- if (!flag_delayed_branch) 78- return false; 79- /* The return at the end of a function needs a delay slot. */ 80- if (NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE 81- && (!(next = next_active_insn (insn)) 82- || ((!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) != SEQUENCE) 83- && arc_attr_type (next) == TYPE_RETURN)) 84- && (!TARGET_PAD_RETURN 85- || (prev_active_insn (insn) 86- && prev_active_insn (prev_active_insn (insn)) 87- && prev_active_insn (prev_active_insn (prev_active_insn (insn)))))) 88- return true; 89- if (NONJUMP_INSN_P (insn) 90- ? (GET_CODE (PATTERN (insn)) == USE 91- || GET_CODE (PATTERN (insn)) == CLOBBER 92- || GET_CODE (PATTERN (insn)) == SEQUENCE) 93- : JUMP_P (insn) 94- ? (GET_CODE (PATTERN (insn)) == ADDR_VEC 95- || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC) 96- : !CALL_P (insn)) 97- return false; 98- return num_delay_slots (insn) != 0; 99-} 100- 101-/* Return true if the scheduling pass(es) has/have already run, 102- i.e. where possible, we should try to mitigate high latencies 103- by different instruction selection. */ 104- 105-bool 106-arc_scheduling_not_expected (void) 107-{ 108- return cfun->machine->arc_reorg_started; 109-} 110- 111 /* Code has a minimum p2 alignment of 1, which we must restore after 112 an ADDR_DIFF_VEC. */ 113 114diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md 115index f91adbc0d94..c635b69ddd5 100644 116--- a/gcc/config/arc/arc.md 117+++ b/gcc/config/arc/arc.md 118@@ -2847,43 +2847,25 @@ archs4x, archs4xd" 119 (set_attr "type" "compare") 120 (set_attr "length" "4,4,8")]) 121 122-; w/c/c comes first (rather than w/0/C_0) to prevent the middle-end 123-; needlessly prioritizing the matching constraint. 124-; Rcw/0/C_0 comes before w/c/L so that the lower latency conditional 125-; execution is used where possible. 126-(define_insn_and_split "adc" 127- [(set (match_operand:SI 0 "dest_reg_operand" "=w,Rcw,w,Rcw,w") 128- (plus:SI (plus:SI (ltu:SI (reg:CC_C CC_REG) (const_int 0)) 129- (match_operand:SI 1 "nonmemory_operand" 130- "%c,0,c,0,cCal")) 131- (match_operand:SI 2 "nonmemory_operand" "c,C_0,L,I,cCal")))] 132+(define_insn "adc" 133+ [(set (match_operand:SI 0 "register_operand" "=r, r,r,r, r,r") 134+ (plus:SI 135+ (plus:SI 136+ (ltu:SI (reg:CC_C CC_REG) (const_int 0)) 137+ (match_operand:SI 1 "nonmemory_operand" "%r, 0,r,0,Cal,r")) 138+ (match_operand:SI 2 "nonmemory_operand" "r,C_0,L,I, r,Cal")))] 139 "register_operand (operands[1], SImode) 140 || register_operand (operands[2], SImode)" 141 "@ 142- adc %0,%1,%2 143- add.cs %0,%1,1 144- adc %0,%1,%2 145- adc %0,%1,%2 146- adc %0,%1,%2" 147- ; if we have a bad schedule after sched2, split. 148- "reload_completed 149- && !optimize_size && (!TARGET_ARC600_FAMILY) 150- && arc_scheduling_not_expected () 151- && arc_sets_cc_p (prev_nonnote_insn (insn)) 152- /* If next comes a return or other insn that needs a delay slot, 153- expect the adc to get into the delay slot. */ 154- && next_nonnote_insn (insn) 155- && !arc_need_delay (next_nonnote_insn (insn)) 156- /* Restore operands before emitting. */ 157- && (extract_insn_cached (insn), 1)" 158- [(set (match_dup 0) (match_dup 3)) 159- (cond_exec 160- (ltu (reg:CC_C CC_REG) (const_int 0)) 161- (set (match_dup 0) (plus:SI (match_dup 0) (const_int 1))))] 162- "operands[3] = simplify_gen_binary (PLUS, SImode, operands[1], operands[2]);" 163+ adc\\t%0,%1,%2 164+ add.cs\\t%0,%1,1 165+ adc\\t%0,%1,%2 166+ adc\\t%0,%1,%2 167+ adc\\t%0,%1,%2 168+ adc\\t%0,%1,%2" 169 [(set_attr "cond" "use") 170 (set_attr "type" "cc_arith") 171- (set_attr "length" "4,4,4,4,8")]) 172+ (set_attr "length" "4,4,4,4,8,8")]) 173 174 ; combiner-splitter cmp / scc -> cmp / adc 175 (define_split 176@@ -3015,7 +2997,7 @@ archs4x, archs4xd" 177 DONE; 178 } 179 emit_insn (gen_sub_f (l0, l1, l2)); 180- emit_insn (gen_sbc (h0, h1, h2, gen_rtx_REG (CCmode, CC_REG))); 181+ emit_insn (gen_sbc (h0, h1, h2)); 182 DONE; 183 ") 184 185@@ -3030,44 +3012,25 @@ archs4x, archs4xd" 186 (set_attr "type" "cc_arith") 187 (set_attr "length" "4")]) 188 189-; w/c/c comes first (rather than Rcw/0/C_0) to prevent the middle-end 190-; needlessly prioritizing the matching constraint. 191-; Rcw/0/C_0 comes before w/c/L so that the lower latency conditional execution 192-; is used where possible. 193-(define_insn_and_split "sbc" 194- [(set (match_operand:SI 0 "dest_reg_operand" "=w,Rcw,w,Rcw,w") 195- (minus:SI (minus:SI (match_operand:SI 1 "nonmemory_operand" 196- "c,0,c,0,cCal") 197- (ltu:SI (match_operand:CC_C 3 "cc_use_register") 198- (const_int 0))) 199- (match_operand:SI 2 "nonmemory_operand" "c,C_0,L,I,cCal")))] 200+(define_insn "sbc" 201+ [(set (match_operand:SI 0 "dest_reg_operand" "=r,r,r,r,r,r") 202+ (minus:SI 203+ (minus:SI 204+ (match_operand:SI 1 "nonmemory_operand" "r, 0,r,0, r,Cal") 205+ (ltu:SI (reg:CC_C CC_REG) (const_int 0))) 206+ (match_operand:SI 2 "nonmemory_operand" "r,C_0,L,I,Cal,r")))] 207 "register_operand (operands[1], SImode) 208 || register_operand (operands[2], SImode)" 209 "@ 210- sbc %0,%1,%2 211- sub.cs %0,%1,1 212- sbc %0,%1,%2 213- sbc %0,%1,%2 214- sbc %0,%1,%2" 215- ; if we have a bad schedule after sched2, split. 216- "reload_completed 217- && !optimize_size && (!TARGET_ARC600_FAMILY) 218- && arc_scheduling_not_expected () 219- && arc_sets_cc_p (prev_nonnote_insn (insn)) 220- /* If next comes a return or other insn that needs a delay slot, 221- expect the adc to get into the delay slot. */ 222- && next_nonnote_insn (insn) 223- && !arc_need_delay (next_nonnote_insn (insn)) 224- /* Restore operands before emitting. */ 225- && (extract_insn_cached (insn), 1)" 226- [(set (match_dup 0) (match_dup 4)) 227- (cond_exec 228- (ltu (reg:CC_C CC_REG) (const_int 0)) 229- (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1))))] 230- "operands[4] = simplify_gen_binary (MINUS, SImode, operands[1], operands[2]);" 231+ sbc\\t%0,%1,%2 232+ sub.cs\\t%0,%1,1 233+ sbc\\t%0,%1,%2 234+ sbc\\t%0,%1,%2 235+ sbc\\t%0,%1,%2 236+ sbc\\t%0,%1,%2" 237 [(set_attr "cond" "use") 238 (set_attr "type" "cc_arith") 239- (set_attr "length" "4,4,4,4,8")]) 240+ (set_attr "length" "4,4,4,4,8,8")]) 241 242 (define_insn "sub_f" 243 [(set (reg:CC CC_REG) 244