1From 22d955122ac0f7ac74ab74aadebf6b8edaf0bbbd Mon Sep 17 00:00:00 2001
2From: Julien Olivain <juju@cotds.org>
3Date: Sun, 15 Dec 2019 18:45:40 +0100
4Subject: [PATCH] DTS for QMTech Zynq starter kit
5
6Signed-off-by: Martin Chabot <martin.chabot@gmail.com>
7Signed-off-by: Julien Olivain <juju@cotds.org>
8---
9 arch/arm/boot/dts/zynq-qmtech.dts | 397 ++++++++++++++++++++++++++++++
10 1 file changed, 397 insertions(+)
11 create mode 100644 arch/arm/boot/dts/zynq-qmtech.dts
12
13diff --git a/arch/arm/boot/dts/zynq-qmtech.dts b/arch/arm/boot/dts/zynq-qmtech.dts
14new file mode 100644
15index 000000000000..c6081dc0080e
16--- /dev/null
17+++ b/arch/arm/boot/dts/zynq-qmtech.dts
18@@ -0,0 +1,397 @@
19+// SPDX-License-Identifier: GPL-2.0+
20+/*
21+ *  Copyright (C) 2011 - 2015 Xilinx
22+ *  Copyright (C) 2012 National Instruments Corp.
23+ *  Copyright (C) 2019 Martin Chabot <martin.chabot@gmail.com>
24+ */
25+
26+/* Derived from:
27+ * https://github.com/Xilinx/linux-xlnx/blob/xilinx-v2019.2.01/arch/arm/boot/dts/zynq-zc702.dts
28+ */
29+
30+/dts-v1/;
31+#include "zynq-7000.dtsi"
32+
33+/ {
34+	model = "QMTECH XC7Z010 Starter Kit";
35+	compatible = "xlnx,zynq-qmtech", "xlnx,zynq-zc702", "xlnx,zynq-7000";
36+
37+	aliases {
38+		ethernet0 = &gem0;
39+		i2c0 = &i2c0;
40+		serial0 = &uart1;
41+		spi0 = &qspi;
42+		mmc0 = &sdhci0;
43+	};
44+
45+	memory@0 {
46+		device_type = "memory";
47+		reg = <0x0 0x20000000>;
48+	};
49+
50+	chosen {
51+		bootargs = "";
52+		stdout-path = "serial0:115200n8";
53+	};
54+
55+	leds {
56+		compatible = "gpio-leds";
57+
58+		ds23 {
59+			label = "ds23";
60+			gpios = <&gpio0 10 0>;
61+			linux,default-trigger = "heartbeat";
62+		};
63+	};
64+
65+};
66+
67+&amba {
68+	ocm: sram@fffc0000 {
69+		compatible = "mmio-sram";
70+		reg = <0xfffc0000 0x10000>;
71+	};
72+};
73+
74+&clkc {
75+	ps-clk-frequency = <33333333>;
76+};
77+
78+&gem0 {
79+	status = "okay";
80+	phy-mode = "rgmii-id";
81+	phy-handle = <&ethernet_phy>;
82+
83+	ethernet_phy: ethernet-phy@0 {
84+		reg = <0>;
85+		device_type = "ethernet-phy";
86+	};
87+};
88+
89+&gpio0 {
90+	pinctrl-names = "default";
91+	pinctrl-0 = <&pinctrl_gpio0_default>;
92+};
93+
94+&i2c0 {
95+	status = "disabled";
96+	clock-frequency = <400000>;
97+	pinctrl-names = "default", "gpio";
98+	pinctrl-0 = <&pinctrl_i2c0_default>;
99+	pinctrl-1 = <&pinctrl_i2c0_gpio>;
100+	scl-gpios = <&gpio0 50 0>;
101+	sda-gpios = <&gpio0 51 0>;
102+
103+	i2c-mux@74 {
104+		compatible = "nxp,pca9548";
105+		#address-cells = <1>;
106+		#size-cells = <0>;
107+		reg = <0x74>;
108+
109+		i2c@0 {
110+			#address-cells = <1>;
111+			#size-cells = <0>;
112+			reg = <0>;
113+			si570: clock-generator@5d {
114+				#clock-cells = <0>;
115+				compatible = "silabs,si570";
116+				temperature-stability = <50>;
117+				reg = <0x5d>;
118+				factory-fout = <156250000>;
119+				clock-frequency = <148500000>;
120+			};
121+		};
122+
123+		i2c@1 {
124+			#address-cells = <1>;
125+			#size-cells = <0>;
126+			reg = <1>;
127+			adv7511: hdmi-tx@39 {
128+				compatible = "adi,adv7511";
129+				reg = <0x39>;
130+				adi,input-depth = <8>;
131+				adi,input-colorspace = "yuv422";
132+				adi,input-clock = "1x";
133+				adi,input-style = <3>;
134+				adi,input-justification = "right";
135+			};
136+		};
137+
138+		i2c@2 {
139+			#address-cells = <1>;
140+			#size-cells = <0>;
141+			reg = <2>;
142+			eeprom@54 {
143+				compatible = "atmel,24c08";
144+				reg = <0x54>;
145+			};
146+		};
147+
148+		i2c@3 {
149+			#address-cells = <1>;
150+			#size-cells = <0>;
151+			reg = <3>;
152+			gpio@21 {
153+				compatible = "ti,tca6416";
154+				reg = <0x21>;
155+				gpio-controller;
156+				#gpio-cells = <2>;
157+			};
158+		};
159+
160+		i2c@4 {
161+			#address-cells = <1>;
162+			#size-cells = <0>;
163+			reg = <4>;
164+			rtc@51 {
165+				compatible = "nxp,pcf8563";
166+				reg = <0x51>;
167+			};
168+		};
169+
170+		i2c@7 {
171+			#address-cells = <1>;
172+			#size-cells = <0>;
173+			reg = <7>;
174+			hwmon@52 {
175+				compatible = "ti,ucd9248";
176+				reg = <52>;
177+			};
178+			hwmon@53 {
179+				compatible = "ti,ucd9248";
180+				reg = <53>;
181+			};
182+			hwmon@54 {
183+				compatible = "ti,ucd9248";
184+				reg = <54>;
185+			};
186+		};
187+	};
188+};
189+
190+&pinctrl0 {
191+	pinctrl_can0_default: can0-default {
192+		mux {
193+			function = "can0";
194+			groups = "can0_9_grp";
195+		};
196+
197+		conf {
198+			groups = "can0_9_grp";
199+			slew-rate = <0>;
200+			io-standard = <1>;
201+		};
202+
203+		conf-rx {
204+			pins = "MIO46";
205+			bias-high-impedance;
206+		};
207+
208+		conf-tx {
209+			pins = "MIO47";
210+			bias-disable;
211+		};
212+	};
213+
214+	pinctrl_gem0_default: gem0-default {
215+		mux {
216+			function = "ethernet0";
217+			groups = "ethernet0_0_grp";
218+		};
219+
220+		conf {
221+			groups = "ethernet0_0_grp";
222+			slew-rate = <0>;
223+			io-standard = <4>;
224+		};
225+
226+		conf-rx {
227+			pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
228+			bias-high-impedance;
229+			low-power-disable;
230+		};
231+
232+		conf-tx {
233+			pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
234+			bias-disable;
235+			low-power-enable;
236+		};
237+
238+		mux-mdio {
239+			function = "mdio0";
240+			groups = "mdio0_0_grp";
241+		};
242+
243+		conf-mdio {
244+			groups = "mdio0_0_grp";
245+			slew-rate = <0>;
246+			io-standard = <1>;
247+			bias-disable;
248+		};
249+	};
250+
251+	pinctrl_gpio0_default: gpio0-default {
252+		mux {
253+			function = "gpio0";
254+			groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
255+				 "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
256+				 "gpio0_13_grp", "gpio0_14_grp";
257+		};
258+
259+		conf {
260+			groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
261+				 "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
262+				 "gpio0_13_grp", "gpio0_14_grp";
263+			slew-rate = <0>;
264+			io-standard = <1>;
265+		};
266+
267+		conf-pull-up {
268+			pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14";
269+			bias-pull-up;
270+		};
271+
272+		conf-pull-none {
273+			pins = "MIO7", "MIO8";
274+			bias-disable;
275+		};
276+	};
277+
278+	pinctrl_i2c0_default: i2c0-default {
279+		mux {
280+			groups = "i2c0_10_grp";
281+			function = "i2c0";
282+		};
283+
284+		conf {
285+			groups = "i2c0_10_grp";
286+			bias-pull-up;
287+			slew-rate = <0>;
288+			io-standard = <1>;
289+		};
290+	};
291+
292+	pinctrl_i2c0_gpio: i2c0-gpio {
293+		mux {
294+			groups = "gpio0_50_grp", "gpio0_51_grp";
295+			function = "gpio0";
296+		};
297+
298+		conf {
299+			groups = "gpio0_50_grp", "gpio0_51_grp";
300+			slew-rate = <0>;
301+			io-standard = <1>;
302+		};
303+	};
304+
305+	pinctrl_sdhci0_default: sdhci0-default {
306+		mux {
307+			groups = "sdio0_2_grp";
308+			function = "sdio0";
309+		};
310+
311+		conf {
312+			groups = "sdio0_2_grp";
313+			slew-rate = <0>;
314+			io-standard = <1>;
315+			bias-disable;
316+		};
317+
318+		mux-cd {
319+			groups = "gpio0_0_grp";
320+			function = "sdio0_cd";
321+		};
322+
323+		conf-cd {
324+			groups = "gpio0_0_grp";
325+			bias-high-impedance;
326+			bias-pull-up;
327+			slew-rate = <0>;
328+			io-standard = <1>;
329+		};
330+
331+		mux-wp {
332+			groups = "gpio0_15_grp";
333+			function = "sdio0_wp";
334+		};
335+
336+		conf-wp {
337+			groups = "gpio0_15_grp";
338+			bias-high-impedance;
339+			bias-pull-up;
340+			slew-rate = <0>;
341+			io-standard = <1>;
342+		};
343+	};
344+
345+	pinctrl_uart1_default: uart1-default {
346+		mux {
347+			groups = "uart1_10_grp";
348+			function = "uart1";
349+		};
350+
351+		conf {
352+			groups = "uart1_10_grp";
353+			slew-rate = <0>;
354+			io-standard = <1>;
355+		};
356+
357+		conf-rx {
358+			pins = "MIO25";
359+			bias-high-impedance;
360+		};
361+
362+		conf-tx {
363+			pins = "MIO24";
364+			bias-disable;
365+		};
366+	};
367+};
368+
369+&qspi {
370+	u-boot,dm-pre-reloc;
371+	status = "disabled";
372+	is-dual = <0>;
373+	num-cs = <1>;
374+	flash@0 {
375+		compatible = "n25q128a11";
376+		reg = <0x0>;
377+		spi-tx-bus-width = <1>;
378+		spi-rx-bus-width = <4>;
379+		spi-max-frequency = <50000000>;
380+		#address-cells = <1>;
381+		#size-cells = <1>;
382+		partition@qspi-fsbl-uboot {
383+			label = "qspi-fsbl-uboot";
384+			reg = <0x0 0x100000>;
385+		};
386+		partition@qspi-linux {
387+			label = "qspi-linux";
388+			reg = <0x100000 0x500000>;
389+		};
390+		partition@qspi-device-tree {
391+			label = "qspi-device-tree";
392+			reg = <0x600000 0x20000>;
393+		};
394+		partition@qspi-rootfs {
395+			label = "qspi-rootfs";
396+			reg = <0x620000 0x5E0000>;
397+		};
398+		partition@qspi-bitstream {
399+			label = "qspi-bitstream";
400+			reg = <0xC00000 0x400000>;
401+		};
402+	};
403+};
404+
405+&sdhci0 {
406+	u-boot,dm-pre-reloc;
407+	status = "okay";
408+};
409+
410+&uart1 {
411+	u-boot,dm-pre-reloc;
412+	status = "okay";
413+	pinctrl-names = "default";
414+	pinctrl-0 = <&pinctrl_uart1_default>;
415+};
416--
4172.23.0
418
419