1Intro 2===== 3 4Andestech(nds32) AE3XX Platform 5 6The AE3XX prototype demonstrates the AE3XX example platform on the FPGA. 7It is composed of one Andestech(nds32) processor and AE3XX. 8 9How to build it 10=============== 11 12Configure Buildroot 13------------------- 14 15The andes_ae3xx_defconfig configuration is a sample configuration with 16all that is required to bring the FPGA Development Board: 17 18 $ make andes_ae3xx_defconfig 19 20Build everything 21---------------- 22Note: you will need to have access to the network, since Buildroot will 23download the packages' sources. 24 25 $ make 26 27Result of the build 28------------------- 29 30After building, you should obtain this tree: 31 32output/images/ 33 +-- vmlinux 34 +-- rootfs.cpio 35 +-- rootfs.tar 36 37How to run it 38============= 39 40Run 41--- 42 43 Setup the Console with the rate 38400/8-N-1. 44 45 $ cd output/images 46 $ ../host/bin/nds32le-linux-gdb vmlinux 47 $ target remote [your host] 48 $ lo 49 $ c 50