1*4882a593Smuzhiyun# 2*4882a593Smuzhiyun# Configure the GCC_TARGET_ARCH variable and append the 3*4882a593Smuzhiyun# appropriate RISC-V ISA extensions. 4*4882a593Smuzhiyun# 5*4882a593Smuzhiyun 6*4882a593Smuzhiyunifeq ($(BR2_riscv),y) 7*4882a593Smuzhiyun 8*4882a593Smuzhiyunifeq ($(BR2_RISCV_64),y) 9*4882a593SmuzhiyunGCC_TARGET_ARCH := rv64i 10*4882a593Smuzhiyunelse 11*4882a593SmuzhiyunGCC_TARGET_ARCH := rv32i 12*4882a593Smuzhiyunendif 13*4882a593Smuzhiyun 14*4882a593Smuzhiyunifeq ($(BR2_RISCV_ISA_RVM),y) 15*4882a593SmuzhiyunGCC_TARGET_ARCH := $(GCC_TARGET_ARCH)m 16*4882a593Smuzhiyunendif 17*4882a593Smuzhiyunifeq ($(BR2_RISCV_ISA_RVA),y) 18*4882a593SmuzhiyunGCC_TARGET_ARCH := $(GCC_TARGET_ARCH)a 19*4882a593Smuzhiyunendif 20*4882a593Smuzhiyunifeq ($(BR2_RISCV_ISA_RVF),y) 21*4882a593SmuzhiyunGCC_TARGET_ARCH := $(GCC_TARGET_ARCH)f 22*4882a593Smuzhiyunendif 23*4882a593Smuzhiyunifeq ($(BR2_RISCV_ISA_RVD),y) 24*4882a593SmuzhiyunGCC_TARGET_ARCH := $(GCC_TARGET_ARCH)d 25*4882a593Smuzhiyunendif 26*4882a593Smuzhiyunifeq ($(BR2_RISCV_ISA_RVC),y) 27*4882a593SmuzhiyunGCC_TARGET_ARCH := $(GCC_TARGET_ARCH)c 28*4882a593Smuzhiyunendif 29*4882a593Smuzhiyun 30*4882a593Smuzhiyunendif 31