1*4882a593Smuzhiyun# RISC-V CPU ISA extensions. 2*4882a593Smuzhiyun 3*4882a593Smuzhiyunconfig BR2_RISCV_ISA_RVI 4*4882a593Smuzhiyun bool 5*4882a593Smuzhiyun 6*4882a593Smuzhiyunconfig BR2_RISCV_ISA_RVM 7*4882a593Smuzhiyun bool 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunconfig BR2_RISCV_ISA_RVA 10*4882a593Smuzhiyun bool 11*4882a593Smuzhiyun 12*4882a593Smuzhiyunconfig BR2_RISCV_ISA_RVF 13*4882a593Smuzhiyun bool 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunconfig BR2_RISCV_ISA_RVD 16*4882a593Smuzhiyun bool 17*4882a593Smuzhiyun 18*4882a593Smuzhiyunconfig BR2_RISCV_ISA_RVC 19*4882a593Smuzhiyun bool 20*4882a593Smuzhiyun 21*4882a593Smuzhiyunchoice 22*4882a593Smuzhiyun prompt "Target Architecture Variant" 23*4882a593Smuzhiyun default BR2_riscv_g 24*4882a593Smuzhiyun 25*4882a593Smuzhiyunconfig BR2_riscv_g 26*4882a593Smuzhiyun bool "General purpose (G)" 27*4882a593Smuzhiyun select BR2_RISCV_ISA_RVI 28*4882a593Smuzhiyun select BR2_RISCV_ISA_RVM 29*4882a593Smuzhiyun select BR2_RISCV_ISA_RVA 30*4882a593Smuzhiyun select BR2_RISCV_ISA_RVF 31*4882a593Smuzhiyun select BR2_RISCV_ISA_RVD 32*4882a593Smuzhiyun help 33*4882a593Smuzhiyun General purpose (G) is equivalent to IMAFD. 34*4882a593Smuzhiyun 35*4882a593Smuzhiyunconfig BR2_riscv_custom 36*4882a593Smuzhiyun bool "Custom architecture" 37*4882a593Smuzhiyun select BR2_RISCV_ISA_RVI 38*4882a593Smuzhiyun select BR2_RISCV_ISA_CUSTOM_RVA 39*4882a593Smuzhiyun 40*4882a593Smuzhiyunendchoice 41*4882a593Smuzhiyun 42*4882a593Smuzhiyunif BR2_riscv_custom 43*4882a593Smuzhiyun 44*4882a593Smuzhiyuncomment "Instruction Set Extensions" 45*4882a593Smuzhiyun 46*4882a593Smuzhiyunconfig BR2_RISCV_ISA_CUSTOM_RVM 47*4882a593Smuzhiyun bool "Integer Multiplication and Division (M)" 48*4882a593Smuzhiyun select BR2_RISCV_ISA_RVM 49*4882a593Smuzhiyun 50*4882a593Smuzhiyunconfig BR2_RISCV_ISA_CUSTOM_RVA 51*4882a593Smuzhiyun bool "Atomic Instructions (A)" 52*4882a593Smuzhiyun select BR2_RISCV_ISA_RVA 53*4882a593Smuzhiyun 54*4882a593Smuzhiyunconfig BR2_RISCV_ISA_CUSTOM_RVF 55*4882a593Smuzhiyun bool "Single-precision Floating-point (F)" 56*4882a593Smuzhiyun select BR2_RISCV_ISA_RVF 57*4882a593Smuzhiyun 58*4882a593Smuzhiyunconfig BR2_RISCV_ISA_CUSTOM_RVD 59*4882a593Smuzhiyun bool "Double-precision Floating-point (D)" 60*4882a593Smuzhiyun depends on BR2_RISCV_ISA_RVF 61*4882a593Smuzhiyun select BR2_RISCV_ISA_RVD 62*4882a593Smuzhiyun 63*4882a593Smuzhiyunconfig BR2_RISCV_ISA_CUSTOM_RVC 64*4882a593Smuzhiyun bool "Compressed Instructions (C)" 65*4882a593Smuzhiyun select BR2_RISCV_ISA_RVC 66*4882a593Smuzhiyunendif 67*4882a593Smuzhiyun 68*4882a593Smuzhiyunchoice 69*4882a593Smuzhiyun prompt "Target Architecture Size" 70*4882a593Smuzhiyun default BR2_RISCV_64 71*4882a593Smuzhiyun 72*4882a593Smuzhiyunconfig BR2_RISCV_32 73*4882a593Smuzhiyun bool "32-bit" 74*4882a593Smuzhiyun select BR2_ARCH_HAS_MMU_MANDATORY 75*4882a593Smuzhiyun 76*4882a593Smuzhiyunconfig BR2_RISCV_64 77*4882a593Smuzhiyun bool "64-bit" 78*4882a593Smuzhiyun select BR2_ARCH_IS_64 79*4882a593Smuzhiyun select BR2_ARCH_HAS_MMU_OPTIONAL 80*4882a593Smuzhiyun 81*4882a593Smuzhiyunendchoice 82*4882a593Smuzhiyun 83*4882a593Smuzhiyunchoice 84*4882a593Smuzhiyun prompt "Target ABI" 85*4882a593Smuzhiyun default BR2_RISCV_ABI_ILP32D if !BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVD 86*4882a593Smuzhiyun default BR2_RISCV_ABI_ILP32F if !BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVF 87*4882a593Smuzhiyun default BR2_RISCV_ABI_ILP32 if !BR2_ARCH_IS_64 88*4882a593Smuzhiyun default BR2_RISCV_ABI_LP64D if BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVD 89*4882a593Smuzhiyun default BR2_RISCV_ABI_LP64F if BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVF 90*4882a593Smuzhiyun default BR2_RISCV_ABI_LP64 if BR2_ARCH_IS_64 91*4882a593Smuzhiyun 92*4882a593Smuzhiyunconfig BR2_RISCV_ABI_ILP32 93*4882a593Smuzhiyun bool "ilp32" 94*4882a593Smuzhiyun depends on !BR2_ARCH_IS_64 95*4882a593Smuzhiyun 96*4882a593Smuzhiyunconfig BR2_RISCV_ABI_ILP32F 97*4882a593Smuzhiyun bool "ilp32f" 98*4882a593Smuzhiyun depends on !BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVF 99*4882a593Smuzhiyun 100*4882a593Smuzhiyunconfig BR2_RISCV_ABI_ILP32D 101*4882a593Smuzhiyun bool "ilp32d" 102*4882a593Smuzhiyun depends on !BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVD 103*4882a593Smuzhiyun 104*4882a593Smuzhiyunconfig BR2_RISCV_ABI_LP64 105*4882a593Smuzhiyun bool "lp64" 106*4882a593Smuzhiyun depends on BR2_ARCH_IS_64 107*4882a593Smuzhiyun 108*4882a593Smuzhiyunconfig BR2_RISCV_ABI_LP64F 109*4882a593Smuzhiyun bool "lp64f" 110*4882a593Smuzhiyun depends on BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVF 111*4882a593Smuzhiyun 112*4882a593Smuzhiyunconfig BR2_RISCV_ABI_LP64D 113*4882a593Smuzhiyun bool "lp64d" 114*4882a593Smuzhiyun depends on BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVD 115*4882a593Smuzhiyunendchoice 116*4882a593Smuzhiyun 117*4882a593Smuzhiyunconfig BR2_ARCH 118*4882a593Smuzhiyun default "riscv32" if !BR2_ARCH_IS_64 119*4882a593Smuzhiyun default "riscv64" if BR2_ARCH_IS_64 120*4882a593Smuzhiyun 121*4882a593Smuzhiyunconfig BR2_NORMALIZED_ARCH 122*4882a593Smuzhiyun default "riscv" 123*4882a593Smuzhiyun 124*4882a593Smuzhiyunconfig BR2_ENDIAN 125*4882a593Smuzhiyun default "LITTLE" 126*4882a593Smuzhiyun 127*4882a593Smuzhiyunconfig BR2_GCC_TARGET_ABI 128*4882a593Smuzhiyun default "ilp32" if BR2_RISCV_ABI_ILP32 129*4882a593Smuzhiyun default "ilp32f" if BR2_RISCV_ABI_ILP32F 130*4882a593Smuzhiyun default "ilp32d" if BR2_RISCV_ABI_ILP32D 131*4882a593Smuzhiyun default "lp64" if BR2_RISCV_ABI_LP64 132*4882a593Smuzhiyun default "lp64f" if BR2_RISCV_ABI_LP64F 133*4882a593Smuzhiyun default "lp64d" if BR2_RISCV_ABI_LP64D 134*4882a593Smuzhiyun 135*4882a593Smuzhiyunconfig BR2_READELF_ARCH_NAME 136*4882a593Smuzhiyun default "RISC-V" 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun# vim: ft=kconfig 139*4882a593Smuzhiyun# -*- mode:kconfig; -*- 140