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Searched refs:nRegWriteCount (Results 1 – 8 of 8) sorted by relevance

/utopia/UTPA2-700.0.x/modules/mfe/drv/mfe_ex/cModel/
H A Dmfe_reg_264e.c490 MS_S32 nRegWriteCount; in OutputSwCfg1_H264() local
997 nRegWriteCount = 0; in OutputSwCfg1_H264()
1004 …WriteRegMFE(0x3, mfe_reg->reg03, (MS_S8*)("[%d] reg03"), nRegWriteCount++, (MS_S8*)("tbc_mode=0")); in OutputSwCfg1_H264()
1007 …WriteRegMFE(0x3, mfe_reg->reg03, (MS_S8*)("[%d] reg03"), nRegWriteCount++, (MS_S8*)("tbc_mode=1")); in OutputSwCfg1_H264()
1008 MS_ASSERT(nRegWriteCount==nTarWriteCount); in OutputSwCfg1_H264()
1011 nRegWriteCount = 0; in OutputSwCfg1_H264()
1039 …WriteRegMFE(0x0, mfe_reg->reg00, (MS_S8*)("[%d] reg00"), nRegWriteCount++, (MS_S8*)("SW reset 0")); in OutputSwCfg1_H264()
1041 …WriteRegMFE(0x0, mfe_reg->reg00, (MS_S8*)("[%d] reg00"), nRegWriteCount++, (MS_S8*)("SW reset 1")); in OutputSwCfg1_H264()
1042 …WriteRegMFE(0x1, mfe_reg->reg01, (MS_S8*)("[%d] reg01"), nRegWriteCount++, (MS_S8*)("picture width… in OutputSwCfg1_H264()
1043 …WriteRegMFE(0x2, mfe_reg->reg02, (MS_S8*)("[%d] reg02"), nRegWriteCount++, (MS_S8*)("picture heigh… in OutputSwCfg1_H264()
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H A Dmfe_common.c204 MS_S32 nRegWriteCount = 0; in SetObufAddr() local
211 …WriteRegMFE(0x3e, mfe_reg->reg3e, (MS_S8*)("[%d] reg3e"), nRegWriteCount++, (MS_S8*)("write_id_adr… in SetObufAddr()
212 …WriteRegMFE(0x3e, mfe_reg->reg3e, (MS_S8*)("[%d] reg3e"), nRegWriteCount++, (MS_S8*)("write_id_adr… in SetObufAddr()
217 …WriteRegMFE(0x3c, mfe_reg->reg3c, (MS_S8*)("[%d] reg3c"), nRegWriteCount++, (MS_S8*)("bsp obuf add… in SetObufAddr()
218 …WriteRegMFE(0x3d, mfe_reg->reg3d, (MS_S8*)("[%d] reg3d"), nRegWriteCount++, (MS_S8*)("bsp obuf add… in SetObufAddr()
220 …WriteRegMFE(0x3e, mfe_reg->reg3e, (MS_S8*)("[%d] reg3e"), nRegWriteCount++, (MS_S8*)("write_id_adr… in SetObufAddr()
225 …WriteRegMFE(0x3e, mfe_reg->reg3e, (MS_S8*)("[%d] reg3e"), nRegWriteCount++, (MS_S8*)("write_id_adr… in SetObufAddr()
226 …WriteRegMFE(0x3e, mfe_reg->reg3e, (MS_S8*)("[%d] reg3e"), nRegWriteCount++, (MS_S8*)("write_id_adr… in SetObufAddr()
231 …WriteRegMFE(0x3c, mfe_reg->reg3c, (MS_S8*)("[%d] reg3c"), nRegWriteCount++, (MS_S8*)("bsp obuf add… in SetObufAddr()
232 …WriteRegMFE(0x3d, mfe_reg->reg3d, (MS_S8*)("[%d] reg3d"), nRegWriteCount++, (MS_S8*)("bsp obuf add… in SetObufAddr()
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H A Dmfe_reg_m4ve.c525 MS_S32 nRegWriteCount; in OutputSwCfg1_Mp4() local
712 … WriteRegMFE(0x68, mfe_reg->reg68, (MS_S8*)("[%d] reg68"), nRegWriteCount, (MS_S8*)("IMI enable")); in OutputSwCfg1_Mp4()
904 nRegWriteCount = 0; in OutputSwCfg1_Mp4()
910 nRegWriteCount = 0; in OutputSwCfg1_Mp4()
935 WriteRegMFE(0x0, mfe_reg->reg00, (MS_S8*)("[%d] reg00"), nRegWriteCount++, (MS_S8*)("SW reset 0")); in OutputSwCfg1_Mp4()
937 WriteRegMFE(0x0, mfe_reg->reg00, (MS_S8*)("[%d] reg00"), nRegWriteCount++, (MS_S8*)("SW reset 1")); in OutputSwCfg1_Mp4()
938 …WriteRegMFE(0x1, mfe_reg->reg01, (MS_S8*)("[%d] reg01"), nRegWriteCount++, (MS_S8*)("picture width… in OutputSwCfg1_Mp4()
939 …WriteRegMFE(0x2, mfe_reg->reg02, (MS_S8*)("[%d] reg02"), nRegWriteCount++, (MS_S8*)("picture heigh… in OutputSwCfg1_Mp4()
940 WriteRegMFE(0x3, mfe_reg->reg03, (MS_S8*)("[%d] reg03"), nRegWriteCount++, (MS_S8*)("value")); in OutputSwCfg1_Mp4()
941 …WriteRegMFE(0x4, mfe_reg->reg04, (MS_S8*)("[%d] reg04"), nRegWriteCount++, (MS_S8*)("er_bs mode th… in OutputSwCfg1_Mp4()
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H A Dmfe_reg_jpge.c_137 int nRegWriteCount;
252 nRegWriteCount = 0;
277 WriteRegMFE(0x0, mfe_reg->reg00, "[%d] reg00", nRegWriteCount++, "SW reset 0");
279 WriteRegMFE(0x0, mfe_reg->reg00, "[%d] reg00", nRegWriteCount++, "SW reset 1");
281 WriteRegMFE(0x1, mfe_reg->reg01, "[%d] reg01", nRegWriteCount++, "picture width");
282 WriteRegMFE(0x2, mfe_reg->reg02, "[%d] reg02", nRegWriteCount++, "picture height");
283 WriteRegMFE(0x3, mfe_reg->reg03, "[%d] reg03", nRegWriteCount++, "value");
285 WriteRegMFE(0x16, mfe_reg->reg16, "[%d] reg16", nRegWriteCount++, "Clock gating");
288 WriteRegMFE(0x06, mfe_reg->reg06, "[%d] reg06", nRegWriteCount++, "current luma base address");
289 …WriteRegMFE(0x07, mfe_reg->reg07, "[%d] reg07", nRegWriteCount++, "current luma base address high"…
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/utopia/UTPA2-700.0.x/modules/mfe/drv/mfe/cModel/
H A Dmfe_reg_264e.c317 int nRegWriteCount; in OutputSwCfg1_H264() local
567 nRegWriteCount = 0; in OutputSwCfg1_H264()
577 WriteRegMFE(0x3, mfe_reg.reg03, "[%d] reg03", nRegWriteCount++, "tbc_mode=0"); in OutputSwCfg1_H264()
580 WriteRegMFE(0x3, mfe_reg.reg03, "[%d] reg03", nRegWriteCount++, "tbc_mode=1"); in OutputSwCfg1_H264()
581 MFE_ASSERT(nRegWriteCount==nTarWriteCount); in OutputSwCfg1_H264()
584 nRegWriteCount = 0; in OutputSwCfg1_H264()
607 WriteRegMFE(0x0, mfe_reg.reg00, "[%d] reg00", nRegWriteCount++, "SW reset 0"); in OutputSwCfg1_H264()
609 WriteRegMFE(0x0, mfe_reg.reg00, "[%d] reg00", nRegWriteCount++, "SW reset 1"); in OutputSwCfg1_H264()
610 WriteRegMFE(0x1, mfe_reg.reg01, "[%d] reg01", nRegWriteCount++, "picture width"); in OutputSwCfg1_H264()
611 WriteRegMFE(0x2, mfe_reg.reg02, "[%d] reg02", nRegWriteCount++, "picture height"); in OutputSwCfg1_H264()
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H A Dmfe_reg_m4ve.c457 int nRegWriteCount; in OutputSwCfg1_Mp4() local
742 nRegWriteCount = 0; in OutputSwCfg1_Mp4()
748 nRegWriteCount = 0; in OutputSwCfg1_Mp4()
777 WriteRegMFE(0x0, mfe_reg.reg00, "[%d] reg00", nRegWriteCount++, "SW reset 0"); in OutputSwCfg1_Mp4()
779 WriteRegMFE(0x0, mfe_reg.reg00, "[%d] reg00", nRegWriteCount++, "SW reset 1"); in OutputSwCfg1_Mp4()
780 WriteRegMFE(0x1, mfe_reg.reg01, "[%d] reg01", nRegWriteCount++, "picture width"); in OutputSwCfg1_Mp4()
781 WriteRegMFE(0x2, mfe_reg.reg02, "[%d] reg02", nRegWriteCount++, "picture height"); in OutputSwCfg1_Mp4()
782 WriteRegMFE(0x3, mfe_reg.reg03, "[%d] reg03", nRegWriteCount++, "value"); in OutputSwCfg1_Mp4()
783 WriteRegMFE(0x4, mfe_reg.reg04, "[%d] reg04", nRegWriteCount++, "er_bs mode threshold"); in OutputSwCfg1_Mp4()
784 WriteRegMFE(0x5, mfe_reg.reg05, "[%d] reg05", nRegWriteCount++, "inter prediction preference"); in OutputSwCfg1_Mp4()
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H A Dmfe_common.c214 int nRegWriteCount = 0; in ResetAllRegs() local
218 WriteRegMFE(0x0, mfe_reg.reg00, "[%d] reg00", nRegWriteCount++, "SW reset 1"); in ResetAllRegs()
220 WriteRegMFE(0x3, mfe_reg.reg03, "[%d] reg03", nRegWriteCount++, "tbc_mode=0"); in ResetAllRegs()
221 WriteRegMFE(0x4, mfe_reg.reg04, "[%d] reg04", nRegWriteCount++, "er_bs mode threshold"); in ResetAllRegs()
223 WriteRegMFE(0x5, mfe_reg.reg05, "[%d] reg05", nRegWriteCount++, "inter prediction preference"); in ResetAllRegs()
225 WriteRegMFE(0x16, mfe_reg.reg16, "[%d] reg16", nRegWriteCount++, "clock gating=0"); in ResetAllRegs()
230 WriteRegMFE(0x18, mfe_reg.reg18, "[%d] reg18", nRegWriteCount++, "JPE encode mode"); in ResetAllRegs()
233 WriteRegMFE(0x19, mfe_reg.reg19, "[%d] reg19", nRegWriteCount++, "value"); in ResetAllRegs()
234 WriteRegMFE(0x1a, mfe_reg.reg1a, "[%d] reg1a", nRegWriteCount++, "value"); in ResetAllRegs()
235 WriteRegMFE(0x1b, mfe_reg.reg1b, "[%d] reg1b", nRegWriteCount++, "value"); in ResetAllRegs()
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H A Dmfe_reg_jpge.c94 int nRegWriteCount; in OutputSwCfg1_Jpg() local
177 nRegWriteCount = 0; in OutputSwCfg1_Jpg()
208 WriteRegMFE(0x0, mfe_reg.reg00, "[%d] reg00", nRegWriteCount++, "SW reset 0"); in OutputSwCfg1_Jpg()
210 WriteRegMFE(0x0, mfe_reg.reg00, "[%d] reg00", nRegWriteCount++, "SW reset 1"); in OutputSwCfg1_Jpg()
213 WriteRegMFE(0x18, mfe_reg.reg18, "[%d] reg18", nRegWriteCount++, "VIU reset 0"); in OutputSwCfg1_Jpg()
215 WriteRegMFE(0x18, mfe_reg.reg18, "[%d] reg18", nRegWriteCount++, "VIU reset 1"); in OutputSwCfg1_Jpg()
218 WriteRegMFE(0x1, mfe_reg.reg01, "[%d] reg01", nRegWriteCount++, "picture width"); in OutputSwCfg1_Jpg()
219 WriteRegMFE(0x2, mfe_reg.reg02, "[%d] reg02", nRegWriteCount++, "picture height"); in OutputSwCfg1_Jpg()
220 WriteRegMFE(0x3, mfe_reg.reg03, "[%d] reg03", nRegWriteCount++, "value"); in OutputSwCfg1_Jpg()
222 WriteRegMFE(0x16, mfe_reg.reg16, "[%d] reg16", nRegWriteCount++, "Clock gating"); in OutputSwCfg1_Jpg()
[all …]