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Searched refs:enableFPLL (Results 1 – 25 of 36) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/mfc/hal/maserati/mfc/
H A Dmdrv_mfc_scalerop.c487 void msSetOutDClk(U8 u8Inputfreq, U8 ucVHzFrmT2/*Set panel frequence from T2*/, BOOL enableFPLL) in msSetOutDClk() argument
570 if(enableFPLL) MDrv_MFC_WriteBit(0x2A18, 1, _BIT3); // PLL set chnage Toggle in msSetOutDClk()
636 void msSetFPLLOutDClk(U8 ucVfreq, U8 ucVHzFrmT2/*Set panel frequence from T2*/, BOOL enableFPLL) in msSetFPLLOutDClk() argument
647 if(enableFPLL&&OPMReset) in msSetFPLLOutDClk()
739 if(enableFPLL) MDrv_MFC_WriteBitINT(0x2A18, 1, _BIT3); // PLL set chnage Toggle in msSetFPLLOutDClk()
750 void MDrv_MFC_SetOutDClk(U16 u16InputfreqX100, BOOL enableFPLL) in MDrv_MFC_SetOutDClk() argument
757 if(enableFPLL&&u8OPMReset) in MDrv_MFC_SetOutDClk()
838 if(enableFPLL) MDrv_MFC_WriteBit(0x2A18, 1, _BIT3); // PLL set chnage Toggle in MDrv_MFC_SetOutDClk()
H A Dmdrv_mfc_scalerop.h95 void msSetFPLLOutDClk(U8 ucVfreq, U8 ucVHzFrmT2, BOOL enableFPLL);
96 void msSetOutDClk(U8 ucVfreq, U8 ucVHzFrmT2, BOOL enableFPLL);
98 void MDrv_MFC_SetOutDClk(U16 u16InputfreqX100, BOOL enableFPLL);
H A Dmadp_mfc.c830 void MAdp_MFC_SetVFreq(U16 u16Inputfreq, BOOL enableFPLL) in MAdp_MFC_SetVFreq() argument
833 MDrv_MFC_SetVFreq(u16Inputfreq, enableFPLL); in MAdp_MFC_SetVFreq()
H A Dmdrv_mfc.c521 void MDrv_MFC_SetVFreq(U16 u16InputfreqX100, BOOL enableFPLL) in MDrv_MFC_SetVFreq() argument
528 MDrv_MFC_SetOutDClk(gPreInputVFreq, enableFPLL); in MDrv_MFC_SetVFreq()
/utopia/UTPA2-700.0.x/modules/mfc/hal/macan/mfc/
H A Dmdrv_mfc_scalerop.c487 void msSetOutDClk(U8 u8Inputfreq, U8 ucVHzFrmT2/*Set panel frequence from T2*/, BOOL enableFPLL) in msSetOutDClk() argument
570 if(enableFPLL) MDrv_MFC_WriteBit(0x2A18, 1, _BIT3); // PLL set chnage Toggle in msSetOutDClk()
636 void msSetFPLLOutDClk(U8 ucVfreq, U8 ucVHzFrmT2/*Set panel frequence from T2*/, BOOL enableFPLL) in msSetFPLLOutDClk() argument
647 if(enableFPLL&&OPMReset) in msSetFPLLOutDClk()
739 if(enableFPLL) MDrv_MFC_WriteBitINT(0x2A18, 1, _BIT3); // PLL set chnage Toggle in msSetFPLLOutDClk()
750 void MDrv_MFC_SetOutDClk(U16 u16InputfreqX100, BOOL enableFPLL) in MDrv_MFC_SetOutDClk() argument
757 if(enableFPLL&&u8OPMReset) in MDrv_MFC_SetOutDClk()
838 if(enableFPLL) MDrv_MFC_WriteBit(0x2A18, 1, _BIT3); // PLL set chnage Toggle in MDrv_MFC_SetOutDClk()
H A Dmdrv_mfc_scalerop.h95 void msSetFPLLOutDClk(U8 ucVfreq, U8 ucVHzFrmT2, BOOL enableFPLL);
96 void msSetOutDClk(U8 ucVfreq, U8 ucVHzFrmT2, BOOL enableFPLL);
98 void MDrv_MFC_SetOutDClk(U16 u16InputfreqX100, BOOL enableFPLL);
H A Dmadp_mfc.c830 void MAdp_MFC_SetVFreq(U16 u16Inputfreq, BOOL enableFPLL) in MAdp_MFC_SetVFreq() argument
833 MDrv_MFC_SetVFreq(u16Inputfreq, enableFPLL); in MAdp_MFC_SetVFreq()
H A Dmdrv_mfc.c521 void MDrv_MFC_SetVFreq(U16 u16InputfreqX100, BOOL enableFPLL) in MDrv_MFC_SetVFreq() argument
528 MDrv_MFC_SetOutDClk(gPreInputVFreq, enableFPLL); in MDrv_MFC_SetVFreq()
/utopia/UTPA2-700.0.x/modules/mfc/hal/M7821/mfc/
H A Dmdrv_mfc_scalerop.c487 void msSetOutDClk(U8 u8Inputfreq, U8 ucVHzFrmT2/*Set panel frequence from T2*/, BOOL enableFPLL) in msSetOutDClk() argument
570 if(enableFPLL) MDrv_MFC_WriteBit(0x2A18, 1, _BIT3); // PLL set chnage Toggle in msSetOutDClk()
636 void msSetFPLLOutDClk(U8 ucVfreq, U8 ucVHzFrmT2/*Set panel frequence from T2*/, BOOL enableFPLL) in msSetFPLLOutDClk() argument
647 if(enableFPLL&&OPMReset) in msSetFPLLOutDClk()
739 if(enableFPLL) MDrv_MFC_WriteBitINT(0x2A18, 1, _BIT3); // PLL set chnage Toggle in msSetFPLLOutDClk()
750 void MDrv_MFC_SetOutDClk(U16 u16InputfreqX100, BOOL enableFPLL) in MDrv_MFC_SetOutDClk() argument
757 if(enableFPLL&&u8OPMReset) in MDrv_MFC_SetOutDClk()
838 if(enableFPLL) MDrv_MFC_WriteBit(0x2A18, 1, _BIT3); // PLL set chnage Toggle in MDrv_MFC_SetOutDClk()
H A Dmdrv_mfc_scalerop.h95 void msSetFPLLOutDClk(U8 ucVfreq, U8 ucVHzFrmT2, BOOL enableFPLL);
96 void msSetOutDClk(U8 ucVfreq, U8 ucVHzFrmT2, BOOL enableFPLL);
98 void MDrv_MFC_SetOutDClk(U16 u16InputfreqX100, BOOL enableFPLL);
H A Dmadp_mfc.c830 void MAdp_MFC_SetVFreq(U16 u16Inputfreq, BOOL enableFPLL) in MAdp_MFC_SetVFreq() argument
833 MDrv_MFC_SetVFreq(u16Inputfreq, enableFPLL); in MAdp_MFC_SetVFreq()
H A Dmdrv_mfc.c521 void MDrv_MFC_SetVFreq(U16 u16InputfreqX100, BOOL enableFPLL) in MDrv_MFC_SetVFreq() argument
528 MDrv_MFC_SetOutDClk(gPreInputVFreq, enableFPLL); in MDrv_MFC_SetVFreq()
/utopia/UTPA2-700.0.x/modules/mfc/hal/maxim/mfc/
H A Dmdrv_mfc_scalerop.c487 void msSetOutDClk(U8 u8Inputfreq, U8 ucVHzFrmT2/*Set panel frequence from T2*/, BOOL enableFPLL) in msSetOutDClk() argument
570 if(enableFPLL) MDrv_MFC_WriteBit(0x2A18, 1, _BIT3); // PLL set chnage Toggle in msSetOutDClk()
636 void msSetFPLLOutDClk(U8 ucVfreq, U8 ucVHzFrmT2/*Set panel frequence from T2*/, BOOL enableFPLL) in msSetFPLLOutDClk() argument
647 if(enableFPLL&&OPMReset) in msSetFPLLOutDClk()
739 if(enableFPLL) MDrv_MFC_WriteBitINT(0x2A18, 1, _BIT3); // PLL set chnage Toggle in msSetFPLLOutDClk()
750 void MDrv_MFC_SetOutDClk(U16 u16InputfreqX100, BOOL enableFPLL) in MDrv_MFC_SetOutDClk() argument
757 if(enableFPLL&&u8OPMReset) in MDrv_MFC_SetOutDClk()
838 if(enableFPLL) MDrv_MFC_WriteBit(0x2A18, 1, _BIT3); // PLL set chnage Toggle in MDrv_MFC_SetOutDClk()
H A Dmdrv_mfc_scalerop.h95 void msSetFPLLOutDClk(U8 ucVfreq, U8 ucVHzFrmT2, BOOL enableFPLL);
96 void msSetOutDClk(U8 ucVfreq, U8 ucVHzFrmT2, BOOL enableFPLL);
98 void MDrv_MFC_SetOutDClk(U16 u16InputfreqX100, BOOL enableFPLL);
H A Dmadp_mfc.c830 void MAdp_MFC_SetVFreq(U16 u16Inputfreq, BOOL enableFPLL) in MAdp_MFC_SetVFreq() argument
833 MDrv_MFC_SetVFreq(u16Inputfreq, enableFPLL); in MAdp_MFC_SetVFreq()
H A Dmdrv_mfc.c521 void MDrv_MFC_SetVFreq(U16 u16InputfreqX100, BOOL enableFPLL) in MDrv_MFC_SetVFreq() argument
528 MDrv_MFC_SetOutDClk(gPreInputVFreq, enableFPLL); in MDrv_MFC_SetVFreq()
/utopia/UTPA2-700.0.x/modules/mfc/hal/manhattan/mfc/
H A Dmdrv_mfc_scalerop.c487 void msSetOutDClk(U8 u8Inputfreq, U8 ucVHzFrmT2/*Set panel frequence from T2*/, BOOL enableFPLL) in msSetOutDClk() argument
570 if(enableFPLL) MDrv_MFC_WriteBit(0x2A18, 1, _BIT3); // PLL set chnage Toggle in msSetOutDClk()
636 void msSetFPLLOutDClk(U8 ucVfreq, U8 ucVHzFrmT2/*Set panel frequence from T2*/, BOOL enableFPLL) in msSetFPLLOutDClk() argument
647 if(enableFPLL&&OPMReset) in msSetFPLLOutDClk()
739 if(enableFPLL) MDrv_MFC_WriteBitINT(0x2A18, 1, _BIT3); // PLL set chnage Toggle in msSetFPLLOutDClk()
750 void MDrv_MFC_SetOutDClk(U16 u16InputfreqX100, BOOL enableFPLL) in MDrv_MFC_SetOutDClk() argument
757 if(enableFPLL&&u8OPMReset) in MDrv_MFC_SetOutDClk()
838 if(enableFPLL) MDrv_MFC_WriteBit(0x2A18, 1, _BIT3); // PLL set chnage Toggle in MDrv_MFC_SetOutDClk()
H A Dmdrv_mfc_scalerop.h95 void msSetFPLLOutDClk(U8 ucVfreq, U8 ucVHzFrmT2, BOOL enableFPLL);
96 void msSetOutDClk(U8 ucVfreq, U8 ucVHzFrmT2, BOOL enableFPLL);
98 void MDrv_MFC_SetOutDClk(U16 u16InputfreqX100, BOOL enableFPLL);
H A Dmadp_mfc.c830 void MAdp_MFC_SetVFreq(U16 u16Inputfreq, BOOL enableFPLL) in MAdp_MFC_SetVFreq() argument
833 MDrv_MFC_SetVFreq(u16Inputfreq, enableFPLL); in MAdp_MFC_SetVFreq()
H A Dmdrv_mfc.c521 void MDrv_MFC_SetVFreq(U16 u16InputfreqX100, BOOL enableFPLL) in MDrv_MFC_SetVFreq() argument
528 MDrv_MFC_SetOutDClk(gPreInputVFreq, enableFPLL); in MDrv_MFC_SetVFreq()
/utopia/UTPA2-700.0.x/modules/mfc/hal/M7621/mfc/
H A Dmdrv_mfc_scalerop.c487 void msSetOutDClk(U8 u8Inputfreq, U8 ucVHzFrmT2/*Set panel frequence from T2*/, BOOL enableFPLL) in msSetOutDClk() argument
570 if(enableFPLL) MDrv_MFC_WriteBit(0x2A18, 1, _BIT3); // PLL set chnage Toggle in msSetOutDClk()
636 void msSetFPLLOutDClk(U8 ucVfreq, U8 ucVHzFrmT2/*Set panel frequence from T2*/, BOOL enableFPLL) in msSetFPLLOutDClk() argument
647 if(enableFPLL&&OPMReset) in msSetFPLLOutDClk()
739 if(enableFPLL) MDrv_MFC_WriteBitINT(0x2A18, 1, _BIT3); // PLL set chnage Toggle in msSetFPLLOutDClk()
750 void MDrv_MFC_SetOutDClk(U16 u16InputfreqX100, BOOL enableFPLL) in MDrv_MFC_SetOutDClk() argument
757 if(enableFPLL&&u8OPMReset) in MDrv_MFC_SetOutDClk()
838 if(enableFPLL) MDrv_MFC_WriteBit(0x2A18, 1, _BIT3); // PLL set chnage Toggle in MDrv_MFC_SetOutDClk()
H A Dmdrv_mfc_scalerop.h95 void msSetFPLLOutDClk(U8 ucVfreq, U8 ucVHzFrmT2, BOOL enableFPLL);
96 void msSetOutDClk(U8 ucVfreq, U8 ucVHzFrmT2, BOOL enableFPLL);
98 void MDrv_MFC_SetOutDClk(U16 u16InputfreqX100, BOOL enableFPLL);
H A Dmadp_mfc.c830 void MAdp_MFC_SetVFreq(U16 u16Inputfreq, BOOL enableFPLL) in MAdp_MFC_SetVFreq() argument
833 MDrv_MFC_SetVFreq(u16Inputfreq, enableFPLL); in MAdp_MFC_SetVFreq()
H A Dmdrv_mfc.c521 void MDrv_MFC_SetVFreq(U16 u16InputfreqX100, BOOL enableFPLL) in MDrv_MFC_SetVFreq() argument
528 MDrv_MFC_SetOutDClk(gPreInputVFreq, enableFPLL); in MDrv_MFC_SetVFreq()
H A Dmadp_mfc.h149 void MAdp_MFC_SetVFreq(U16 u16Inputfreq, BOOL enableFPLL);

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