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Searched refs:cont1 (Results 1 – 11 of 11) sorted by relevance

/utopia/UTPA2-700.0.x/modules/pq/hal/k6lite/pq/
H A Dmhal_pq.c659 MS_U16 cont1=0, cont2=0, cont3=0, cont4=0; in Hal_PQ_set_sram_ihc_crd_table() local
670 SRAM1_IHC[cont1++] = u32Addr[u16Index]; in Hal_PQ_set_sram_ihc_crd_table()
700 MS_U16 cont1, cont2, cont3, cont4; in Hal_PQ_set_sram_ihc_crd_table()
713 cont1 = cont2 = cont3 = cont4 = 0; in Hal_PQ_set_sram_ihc_crd_table()
725 SRAM1_IHC[cont1]=data; in Hal_PQ_set_sram_ihc_crd_table()
726 cont1 = cont1 < MAX_SRAM_SIZE-1 ? cont1+1 : MAX_SRAM_SIZE-1; in Hal_PQ_set_sram_ihc_crd_table()
758 SRAM1_IHC[cont1]=data; in Hal_PQ_set_sram_ihc_crd_table()
759 cont1 = cont1 < MAX_SRAM_SIZE-1 ? cont1+1 : MAX_SRAM_SIZE-1; in Hal_PQ_set_sram_ihc_crd_table()
768 _Hal_PQ_set_sram_ihc_crd_table(&SRAM1_IHC[0], 0, cont1); in Hal_PQ_set_sram_ihc_crd_table()
/utopia/UTPA2-700.0.x/modules/pq/hal/kano/pq/
H A Dmhal_pq.c661 MS_U16 cont1=0, cont2=0, cont3=0, cont4=0; in Hal_PQ_set_sram_ihc_crd_table() local
672 SRAM1_IHC[cont1++] = u32Addr[u16Index]; in Hal_PQ_set_sram_ihc_crd_table()
702 MS_U16 cont1, cont2, cont3, cont4; in Hal_PQ_set_sram_ihc_crd_table()
715 cont1 = cont2 = cont3 = cont4 = 0; in Hal_PQ_set_sram_ihc_crd_table()
727 SRAM1_IHC[cont1]=data; in Hal_PQ_set_sram_ihc_crd_table()
728 cont1 = cont1 < MAX_SRAM_SIZE-1 ? cont1+1 : MAX_SRAM_SIZE-1; in Hal_PQ_set_sram_ihc_crd_table()
760 SRAM1_IHC[cont1]=data; in Hal_PQ_set_sram_ihc_crd_table()
761 cont1 = cont1 < MAX_SRAM_SIZE-1 ? cont1+1 : MAX_SRAM_SIZE-1; in Hal_PQ_set_sram_ihc_crd_table()
770 _Hal_PQ_set_sram_ihc_crd_table(&SRAM1_IHC[0], 0, cont1); in Hal_PQ_set_sram_ihc_crd_table()
/utopia/UTPA2-700.0.x/modules/pq/hal/k6/pq/
H A Dmhal_pq.c659 MS_U16 cont1=0, cont2=0, cont3=0, cont4=0; in Hal_PQ_set_sram_ihc_crd_table() local
670 SRAM1_IHC[cont1++] = u32Addr[u16Index]; in Hal_PQ_set_sram_ihc_crd_table()
700 MS_U16 cont1, cont2, cont3, cont4; in Hal_PQ_set_sram_ihc_crd_table()
713 cont1 = cont2 = cont3 = cont4 = 0; in Hal_PQ_set_sram_ihc_crd_table()
725 SRAM1_IHC[cont1]=data; in Hal_PQ_set_sram_ihc_crd_table()
726 cont1 = cont1 < MAX_SRAM_SIZE-1 ? cont1+1 : MAX_SRAM_SIZE-1; in Hal_PQ_set_sram_ihc_crd_table()
758 SRAM1_IHC[cont1]=data; in Hal_PQ_set_sram_ihc_crd_table()
759 cont1 = cont1 < MAX_SRAM_SIZE-1 ? cont1+1 : MAX_SRAM_SIZE-1; in Hal_PQ_set_sram_ihc_crd_table()
768 _Hal_PQ_set_sram_ihc_crd_table(&SRAM1_IHC[0], 0, cont1); in Hal_PQ_set_sram_ihc_crd_table()
/utopia/UTPA2-700.0.x/modules/pq/hal/curry/pq/
H A Dmhal_pq.c659 MS_U16 cont1=0, cont2=0, cont3=0, cont4=0; in Hal_PQ_set_sram_ihc_crd_table() local
670 SRAM1_IHC[cont1++] = u32Addr[u16Index]; in Hal_PQ_set_sram_ihc_crd_table()
700 MS_U16 cont1, cont2, cont3, cont4; in Hal_PQ_set_sram_ihc_crd_table()
713 cont1 = cont2 = cont3 = cont4 = 0; in Hal_PQ_set_sram_ihc_crd_table()
725 SRAM1_IHC[cont1]=data; in Hal_PQ_set_sram_ihc_crd_table()
726 cont1 = cont1 < MAX_SRAM_SIZE-1 ? cont1+1 : MAX_SRAM_SIZE-1; in Hal_PQ_set_sram_ihc_crd_table()
758 SRAM1_IHC[cont1]=data; in Hal_PQ_set_sram_ihc_crd_table()
759 cont1 = cont1 < MAX_SRAM_SIZE-1 ? cont1+1 : MAX_SRAM_SIZE-1; in Hal_PQ_set_sram_ihc_crd_table()
768 _Hal_PQ_set_sram_ihc_crd_table(&SRAM1_IHC[0], 0, cont1); in Hal_PQ_set_sram_ihc_crd_table()
/utopia/UTPA2-700.0.x/modules/xc/drv/ace/
H A DdrvACE.c954 MS_U16 cont1, cont2, cont3, cont4; in MDrv_XC_ACE_Set_IHC_SRAM() local
968 cont1 = cont2 = cont3 = cont4 = 0; in MDrv_XC_ACE_Set_IHC_SRAM()
980 SRAM1_IHC[cont1]=data; in MDrv_XC_ACE_Set_IHC_SRAM()
981 cont1 = cont1 < MAX_SRAM_SIZE-1 ? cont1+1 : MAX_SRAM_SIZE-1; in MDrv_XC_ACE_Set_IHC_SRAM()
1012 SRAM1_IHC[cont1]=data; in MDrv_XC_ACE_Set_IHC_SRAM()
1013 cont1 = cont1 < MAX_SRAM_SIZE-1 ? cont1+1 : MAX_SRAM_SIZE-1; in MDrv_XC_ACE_Set_IHC_SRAM()
1022 Hal_ACE_Set_IHC_SRAM(pInstance, &SRAM1_IHC[0], 0, cont1); in MDrv_XC_ACE_Set_IHC_SRAM()
/utopia/UTPA2-700.0.x/modules/pq/hal/manhattan/pq/
H A Dmhal_pq.c594 MS_U16 cont1=0, cont2=0, cont3=0, cont4=0; in Hal_PQ_set_sram_icc_crd_table() local
607 SRAM1_ICC[cont1] = (u32Addr[u16Index]); in Hal_PQ_set_sram_icc_crd_table()
609 cont1++; in Hal_PQ_set_sram_icc_crd_table()
730 MS_U16 cont1=0, cont2=0, cont3=0, cont4=0; in Hal_PQ_set_sram_ihc_crd_table() local
743 SRAM1_IHC[cont1] = (u32Addr[u16Index]); in Hal_PQ_set_sram_ihc_crd_table()
745 cont1++; in Hal_PQ_set_sram_ihc_crd_table()
1360 MS_U16 cont1=0, cont2=0, cont3=0, cont4=0; in Hal_PQ_set_UFSC_sram_icc_crd_table() local
1373 UFSC_SRAM1_ICC[cont1] = (u32Addr[u16Index]); in Hal_PQ_set_UFSC_sram_icc_crd_table()
1375 cont1++; in Hal_PQ_set_UFSC_sram_icc_crd_table()
1453 MS_U16 cont1=0, cont2=0, cont3=0, cont4=0; in Hal_PQ_set_UFSC_sram_ihc_crd_table() local
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/utopia/UTPA2-700.0.x/modules/pq/hal/M7821/pq/
H A Dmhal_pq.c1029 MS_U16 cont1=0, cont2=0, cont3=0, cont4=0; in Hal_PQ_set_sram_icc_crd_table() local
1042 SRAM1_ICC[cont1] = (u32Addr[u16Index]); in Hal_PQ_set_sram_icc_crd_table()
1044 cont1++; in Hal_PQ_set_sram_icc_crd_table()
1165 MS_U16 cont1=0, cont2=0, cont3=0, cont4=0; in Hal_PQ_set_sram_ihc_crd_table() local
1178 SRAM1_IHC[cont1] = (u32Addr[u16Index]); in Hal_PQ_set_sram_ihc_crd_table()
1180 cont1++; in Hal_PQ_set_sram_ihc_crd_table()
1796 MS_U16 cont1=0, cont2=0, cont3=0, cont4=0; in Hal_PQ_set_UFSC_sram_icc_crd_table() local
1809 UFSC_SRAM1_ICC[cont1] = (u32Addr[u16Index]); in Hal_PQ_set_UFSC_sram_icc_crd_table()
1811 cont1++; in Hal_PQ_set_UFSC_sram_icc_crd_table()
1889 MS_U16 cont1=0, cont2=0, cont3=0, cont4=0; in Hal_PQ_set_UFSC_sram_ihc_crd_table() local
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/utopia/UTPA2-700.0.x/modules/pq/hal/M7621/pq/
H A Dmhal_pq.c1029 MS_U16 cont1=0, cont2=0, cont3=0, cont4=0; in Hal_PQ_set_sram_icc_crd_table() local
1042 SRAM1_ICC[cont1] = (u32Addr[u16Index]); in Hal_PQ_set_sram_icc_crd_table()
1044 cont1++; in Hal_PQ_set_sram_icc_crd_table()
1165 MS_U16 cont1=0, cont2=0, cont3=0, cont4=0; in Hal_PQ_set_sram_ihc_crd_table() local
1178 SRAM1_IHC[cont1] = (u32Addr[u16Index]); in Hal_PQ_set_sram_ihc_crd_table()
1180 cont1++; in Hal_PQ_set_sram_ihc_crd_table()
1796 MS_U16 cont1=0, cont2=0, cont3=0, cont4=0; in Hal_PQ_set_UFSC_sram_icc_crd_table() local
1809 UFSC_SRAM1_ICC[cont1] = (u32Addr[u16Index]); in Hal_PQ_set_UFSC_sram_icc_crd_table()
1811 cont1++; in Hal_PQ_set_UFSC_sram_icc_crd_table()
1889 MS_U16 cont1=0, cont2=0, cont3=0, cont4=0; in Hal_PQ_set_UFSC_sram_ihc_crd_table() local
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/utopia/UTPA2-700.0.x/modules/pq/hal/maserati/pq/
H A Dmhal_pq.c1029 MS_U16 cont1=0, cont2=0, cont3=0, cont4=0; in Hal_PQ_set_sram_icc_crd_table() local
1042 SRAM1_ICC[cont1] = (u32Addr[u16Index]); in Hal_PQ_set_sram_icc_crd_table()
1044 cont1++; in Hal_PQ_set_sram_icc_crd_table()
1165 MS_U16 cont1=0, cont2=0, cont3=0, cont4=0; in Hal_PQ_set_sram_ihc_crd_table() local
1178 SRAM1_IHC[cont1] = (u32Addr[u16Index]); in Hal_PQ_set_sram_ihc_crd_table()
1180 cont1++; in Hal_PQ_set_sram_ihc_crd_table()
1796 MS_U16 cont1=0, cont2=0, cont3=0, cont4=0; in Hal_PQ_set_UFSC_sram_icc_crd_table() local
1809 UFSC_SRAM1_ICC[cont1] = (u32Addr[u16Index]); in Hal_PQ_set_UFSC_sram_icc_crd_table()
1811 cont1++; in Hal_PQ_set_UFSC_sram_icc_crd_table()
1889 MS_U16 cont1=0, cont2=0, cont3=0, cont4=0; in Hal_PQ_set_UFSC_sram_ihc_crd_table() local
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/utopia/UTPA2-700.0.x/modules/pq/hal/maxim/pq/
H A Dmhal_pq.c1029 MS_U16 cont1=0, cont2=0, cont3=0, cont4=0; in Hal_PQ_set_sram_icc_crd_table() local
1042 SRAM1_ICC[cont1] = (u32Addr[u16Index]); in Hal_PQ_set_sram_icc_crd_table()
1044 cont1++; in Hal_PQ_set_sram_icc_crd_table()
1165 MS_U16 cont1=0, cont2=0, cont3=0, cont4=0; in Hal_PQ_set_sram_ihc_crd_table() local
1178 SRAM1_IHC[cont1] = (u32Addr[u16Index]); in Hal_PQ_set_sram_ihc_crd_table()
1180 cont1++; in Hal_PQ_set_sram_ihc_crd_table()
1796 MS_U16 cont1=0, cont2=0, cont3=0, cont4=0; in Hal_PQ_set_UFSC_sram_icc_crd_table() local
1809 UFSC_SRAM1_ICC[cont1] = (u32Addr[u16Index]); in Hal_PQ_set_UFSC_sram_icc_crd_table()
1811 cont1++; in Hal_PQ_set_UFSC_sram_icc_crd_table()
1889 MS_U16 cont1=0, cont2=0, cont3=0, cont4=0; in Hal_PQ_set_UFSC_sram_ihc_crd_table() local
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/utopia/UTPA2-700.0.x/modules/pq/hal/mooney/pq/
H A Dmhal_pq.c846 MS_U16 cont1=0, cont2=0, cont3=0, cont4=0; in Hal_PQ_set_sram_ihc_crd_table() local
859 SRAM1_IHC[cont1] = (u32Addr[u16Index]); in Hal_PQ_set_sram_ihc_crd_table()
861 cont1++; in Hal_PQ_set_sram_ihc_crd_table()