Searched refs:_RegCtrl0 (Results 1 – 1 of 1) sorted by relevance
38 static REG_Ctrl0* _RegCtrl0 = NULL; // PVR_IframeLUT LUT variable128 _RegCtrl0 = (REG_Ctrl0*)(u32BankAddr + 0xE6C00UL); // PVR_IframeLUT LUT 0x1736 in _HAL_PVR_IframeLUT_SetBank()142 _HAL_REG32_PVR_IframeLUT_W(&_RegCtrl0->CFG0_10_11, u32StartAddr0 >> MIU_BUS); in _HAL_PVR_IframeLUT_SetBuf()144 _HAL_REG32_PVR_IframeLUT_W(&(_RegCtrl0->CFG0_14_15), u32EndAddr0 >> MIU_BUS); in _HAL_PVR_IframeLUT_SetBuf()146 _HAL_REG32_PVR_IframeLUT_W(&(_RegCtrl0->CFG0_12_13), u32EndAddr0 >> (MIU_BUS + 1)); in _HAL_PVR_IframeLUT_SetBuf()150 _HAL_REG32_PVR_IframeLUT_W(&_RegCtrl0->CFG0_16_17, u32StartAddr0 >> MIU_BUS); in _HAL_PVR_IframeLUT_SetBuf()152 _HAL_REG32_PVR_IframeLUT_W(&_RegCtrl0->CFG0_1A_1B, u32EndAddr0 >> MIU_BUS); in _HAL_PVR_IframeLUT_SetBuf()154 _HAL_REG32_PVR_IframeLUT_W(&(_RegCtrl0->CFG0_18_19), u32EndAddr0 >> (MIU_BUS + 1)); in _HAL_PVR_IframeLUT_SetBuf()159 _HAL_REG32_PVR_IframeLUT_W(&(_RegCtrl0->CFG0_1C_1D), u32StartAddr0 >> MIU_BUS); in _HAL_PVR_IframeLUT_SetBuf()161 _HAL_REG32_PVR_IframeLUT_W(&(_RegCtrl0->CFG0_20_21), u32EndAddr0 >> MIU_BUS); in _HAL_PVR_IframeLUT_SetBuf()[all …]