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Searched refs:UART_LSR (Results 1 – 25 of 48) sorted by relevance

12

/utopia/UTPA2-700.0.x/modules/uart/hal/k6lite/uart/
H A DhalUART.c566 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
583 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
639 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
683 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
700 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
767 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr()
799 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr()
833 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr_HalReg()
865 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr_HalReg()
1016 while (!(UART_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_PIU_Write()
[all …]
H A DregUART.h179 #define UART_LSR 5 // In: Line Status Register macro
193 #define UART_LSR (5 * 2) // In: Line Status Register macro
/utopia/UTPA2-700.0.x/modules/uart/hal/curry/uart/
H A DhalUART.c566 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
583 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
639 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
683 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
700 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
767 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr()
799 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr()
833 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr_HalReg()
865 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr_HalReg()
1016 while (!(UART_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_PIU_Write()
[all …]
H A DregUART.h179 #define UART_LSR 5 // In: Line Status Register macro
193 #define UART_LSR (5 * 2) // In: Line Status Register macro
/utopia/UTPA2-700.0.x/modules/uart/hal/kano/uart/
H A DhalUART.c566 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
583 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
639 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
683 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
700 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
767 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr()
799 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr()
833 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr_HalReg()
865 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr_HalReg()
1016 while (!(UART_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_PIU_Write()
[all …]
H A DregUART.h179 #define UART_LSR 5 // In: Line Status Register macro
193 #define UART_LSR (5 * 2) // In: Line Status Register macro
/utopia/UTPA2-700.0.x/modules/uart/hal/k6/uart/
H A DhalUART.c566 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
583 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
639 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
683 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
700 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
767 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr()
799 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr()
833 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr_HalReg()
865 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr_HalReg()
1016 while (!(UART_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_PIU_Write()
[all …]
/utopia/UTPA2-700.0.x/modules/uart/hal/mooney/uart/
H A DhalUART.c587 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
604 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
660 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
704 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
721 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
788 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr()
820 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr()
854 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr_HalReg()
886 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr_HalReg()
1037 while (!(UART_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_PIU_Write()
[all …]
H A DregUART.h178 #define UART_LSR 5 // In: Line Status Register macro
192 #define UART_LSR (5 * 2) // In: Line Status Register macro
/utopia/UTPA2-700.0.x/modules/uart/hal/mustang/uart/
H A DhalUART.c582 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
599 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
655 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
699 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
716 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
784 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr()
816 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr()
850 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr_HalReg()
882 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr_HalReg()
1035 while ((!(UART_REG8(UART_LSR) & UART_LSR_THRE)) && (timeout_count++ < UART_TIMEOUT)); in HAL_UART_PIU_Write()
[all …]
H A DregUART.h185 #define UART_LSR 5 // In: Line Status Register macro
199 #define UART_LSR (5 * 2) // In: Line Status Register macro
/utopia/UTPA2-700.0.x/modules/uart/hal/maldives/uart/
H A DhalUART.c582 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
599 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
655 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
699 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
716 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
784 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr()
816 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr()
850 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr_HalReg()
882 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr_HalReg()
1035 while ((!(UART_REG8(UART_LSR) & UART_LSR_THRE)) && (timeout_count++ < UART_TIMEOUT)); in HAL_UART_PIU_Write()
[all …]
H A DregUART.h180 #define UART_LSR 5 // In: Line Status Register macro
194 #define UART_LSR (5 * 2) // In: Line Status Register macro
/utopia/UTPA2-700.0.x/modules/uart/hal/macan/uart/
H A DhalUART.c612 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
629 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
685 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
729 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
746 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
813 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr()
845 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr()
879 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr_HalReg()
911 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr_HalReg()
1062 while (!(UART_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_PIU_Write()
[all …]
H A DregUART.h200 #define UART_LSR 5 // In: Line Status Register macro
214 #define UART_LSR (5 * 2) // In: Line Status Register macro
/utopia/UTPA2-700.0.x/modules/uart/hal/messi/uart/
H A DhalUART.c611 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
628 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
684 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
728 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
745 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
812 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr()
844 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr()
878 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr_HalReg()
910 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr_HalReg()
1061 while (!(UART_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_PIU_Write()
[all …]
H A DregUART.h178 #define UART_LSR 5 // In: Line Status Register macro
192 #define UART_LSR (5 * 2) // In: Line Status Register macro
/utopia/UTPA2-700.0.x/modules/uart/hal/M7621/uart/
H A DhalUART.c615 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
632 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
688 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
732 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
749 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
816 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr()
848 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr()
882 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr_HalReg()
914 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr_HalReg()
1065 while (!(UART_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_PIU_Write()
[all …]
/utopia/UTPA2-700.0.x/modules/uart/hal/maserati/uart/
H A DhalUART.c615 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
632 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
688 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
732 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
749 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
816 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr()
848 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr()
882 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr_HalReg()
914 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr_HalReg()
1065 while (!(UART_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_PIU_Write()
[all …]
H A DregUART.h216 #define UART_LSR 5 // In: Line Status Register macro
230 #define UART_LSR (5 * 2) // In: Line Status Register macro
/utopia/UTPA2-700.0.x/modules/uart/hal/maxim/uart/
H A DhalUART.c615 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
632 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
688 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
732 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
749 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
816 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr()
848 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr()
882 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr_HalReg()
914 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr_HalReg()
1065 while (!(UART_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_PIU_Write()
[all …]
/utopia/UTPA2-700.0.x/modules/uart/hal/manhattan/uart/
H A DhalUART.c614 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
631 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
687 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
731 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
748 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
815 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr()
847 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr()
881 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr_HalReg()
913 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr_HalReg()
1064 while (!(UART_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_PIU_Write()
[all …]
/utopia/UTPA2-700.0.x/modules/uart/hal/M7821/uart/
H A DhalUART.c615 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
632 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
688 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
732 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
749 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
816 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr()
848 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr()
882 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr_HalReg()
914 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr_HalReg()
1065 while (!(UART_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_PIU_Write()
[all …]
H A DregUART.h220 #define UART_LSR 5 // In: Line Status Register macro
234 #define UART_LSR (5 * 2) // In: Line Status Register macro
/utopia/UTPA2-700.0.x/modules/uart/hal/mainz/uart/
H A DhalUART.c657 while (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_Aeon_Write()
674 if (!(AEON_REG8(UART_LSR) & UART_LSR_THRE)) in HAL_UART_Aeon_Write()
730 while (!(AEON_REG8(UART_LSR) & UART_LSR_DR)); in HAL_UART_Aeon_Read()
774 if (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Poll()
791 if (AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Poll()
858 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr()
890 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr()
924 while (AEON_REG8(UART_LSR) & UART_LSR_DR) in HAL_UART_Aeon_Isr_HalReg()
956 while ((AEON_REG8(UART_LSR) & UART_LSR_THRE) in HAL_UART_Aeon_Isr_HalReg()
1107 while (!(UART_REG8(UART_LSR) & UART_LSR_THRE)); in HAL_UART_PIU_Write()
[all …]

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