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Searched refs:REG_VPU_BASE (Results 1 – 25 of 31) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/vpu_v3/
H A DregVPU_EX.h231 #define REG_VPU_BASE (0x63300) macro
237 #define REG_VPU_BASE (0x0300) macro
245 #define VPU_REG_EXPC_L (REG_VPU_BASE+(0x000a<<1))
246 #define VPU_REG_EXPC_H (REG_VPU_BASE+(0x000b<<1))
248 #define VPU_REG_CPU_STATUS (REG_VPU_BASE+( 0x000f<<1))
252 #define VPU_REG_MIU_LAST (REG_VPU_BASE+( 0x0020<<1))
255 #define VPU_REG_ICU_STATUS (REG_VPU_BASE+( 0x001f<<1))
259 #define VPU_REG_ICU_DBG_SEL (REG_VPU_BASE+( 0x0010<<1))
260 #define VPU_REG_ICU_DBG_DAT0 (REG_VPU_BASE+( 0x0014<<1))
263 #define VPU_REG_DCU_DBG_SEL (REG_VPU_BASE+( 0x0028<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/vpu_v3/
H A DregVPU_EX.h231 #define REG_VPU_BASE (0x63300) macro
237 #define REG_VPU_BASE (0x0300) macro
245 #define VPU_REG_EXPC_L (REG_VPU_BASE+(0x000a<<1))
246 #define VPU_REG_EXPC_H (REG_VPU_BASE+(0x000b<<1))
248 #define VPU_REG_CPU_STATUS (REG_VPU_BASE+( 0x000f<<1))
252 #define VPU_REG_MIU_LAST (REG_VPU_BASE+( 0x0020<<1))
255 #define VPU_REG_ICU_STATUS (REG_VPU_BASE+( 0x001f<<1))
259 #define VPU_REG_ICU_DBG_SEL (REG_VPU_BASE+( 0x0010<<1))
260 #define VPU_REG_ICU_DBG_DAT0 (REG_VPU_BASE+( 0x0014<<1))
263 #define VPU_REG_DCU_DBG_SEL (REG_VPU_BASE+( 0x0028<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/vpu_v3/
H A DregVPU_EX.h231 #define REG_VPU_BASE (0x63300) macro
237 #define REG_VPU_BASE (0x0300) macro
245 #define VPU_REG_EXPC_L (REG_VPU_BASE+(0x000a<<1))
246 #define VPU_REG_EXPC_H (REG_VPU_BASE+(0x000b<<1))
248 #define VPU_REG_CPU_STATUS (REG_VPU_BASE+( 0x000f<<1))
252 #define VPU_REG_MIU_LAST (REG_VPU_BASE+( 0x0020<<1))
255 #define VPU_REG_ICU_STATUS (REG_VPU_BASE+( 0x001f<<1))
259 #define VPU_REG_ICU_DBG_SEL (REG_VPU_BASE+( 0x0010<<1))
260 #define VPU_REG_ICU_DBG_DAT0 (REG_VPU_BASE+( 0x0014<<1))
263 #define VPU_REG_DCU_DBG_SEL (REG_VPU_BASE+( 0x0028<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/vpu_v3/
H A DregVPU_EX.h231 #define REG_VPU_BASE (0x63300) macro
237 #define REG_VPU_BASE (0x0300) macro
245 #define VPU_REG_EXPC_L (REG_VPU_BASE+(0x000a<<1))
246 #define VPU_REG_EXPC_H (REG_VPU_BASE+(0x000b<<1))
248 #define VPU_REG_CPU_STATUS (REG_VPU_BASE+( 0x000f<<1))
252 #define VPU_REG_MIU_LAST (REG_VPU_BASE+( 0x0020<<1))
255 #define VPU_REG_ICU_STATUS (REG_VPU_BASE+( 0x001f<<1))
259 #define VPU_REG_ICU_DBG_SEL (REG_VPU_BASE+( 0x0010<<1))
260 #define VPU_REG_ICU_DBG_DAT0 (REG_VPU_BASE+( 0x0014<<1))
263 #define VPU_REG_DCU_DBG_SEL (REG_VPU_BASE+( 0x0028<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/vpu_v3/
H A DregVPU_EX.h231 #define REG_VPU_BASE (0x63300) macro
237 #define REG_VPU_BASE (0x0300) macro
245 #define VPU_REG_EXPC_L (REG_VPU_BASE+(0x000a<<1))
246 #define VPU_REG_EXPC_H (REG_VPU_BASE+(0x000b<<1))
248 #define VPU_REG_CPU_STATUS (REG_VPU_BASE+( 0x000f<<1))
252 #define VPU_REG_MIU_LAST (REG_VPU_BASE+( 0x0020<<1))
255 #define VPU_REG_ICU_STATUS (REG_VPU_BASE+( 0x001f<<1))
259 #define VPU_REG_ICU_DBG_SEL (REG_VPU_BASE+( 0x0010<<1))
260 #define VPU_REG_ICU_DBG_DAT0 (REG_VPU_BASE+( 0x0014<<1))
263 #define VPU_REG_DCU_DBG_SEL (REG_VPU_BASE+( 0x0028<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/vpu_v3/
H A DregVPU_EX.h231 #define REG_VPU_BASE (0x63300) macro
237 #define REG_VPU_BASE (0x0300) macro
245 #define VPU_REG_EXPC_L (REG_VPU_BASE+(0x000a<<1))
246 #define VPU_REG_EXPC_H (REG_VPU_BASE+(0x000b<<1))
248 #define VPU_REG_CPU_STATUS (REG_VPU_BASE+( 0x000f<<1))
252 #define VPU_REG_MIU_LAST (REG_VPU_BASE+( 0x0020<<1))
255 #define VPU_REG_ICU_STATUS (REG_VPU_BASE+( 0x001f<<1))
259 #define VPU_REG_ICU_DBG_SEL (REG_VPU_BASE+( 0x0010<<1))
260 #define VPU_REG_ICU_DBG_DAT0 (REG_VPU_BASE+( 0x0014<<1))
263 #define VPU_REG_DCU_DBG_SEL (REG_VPU_BASE+( 0x0028<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/vpu_v3/
H A DregVPU_EX.h231 #define REG_VPU_BASE (0x63300) macro
237 #define REG_VPU_BASE (0x0300) macro
245 #define VPU_REG_EXPC_L (REG_VPU_BASE+(0x000a<<1))
246 #define VPU_REG_EXPC_H (REG_VPU_BASE+(0x000b<<1))
248 #define VPU_REG_CPU_STATUS (REG_VPU_BASE+( 0x000f<<1))
252 #define VPU_REG_MIU_LAST (REG_VPU_BASE+( 0x0020<<1))
255 #define VPU_REG_ICU_STATUS (REG_VPU_BASE+( 0x001f<<1))
259 #define VPU_REG_ICU_DBG_SEL (REG_VPU_BASE+( 0x0010<<1))
260 #define VPU_REG_ICU_DBG_DAT0 (REG_VPU_BASE+( 0x0014<<1))
263 #define VPU_REG_DCU_DBG_SEL (REG_VPU_BASE+( 0x0028<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/vpu_v3/
H A DregVPU_EX.h231 #define REG_VPU_BASE (0x63300) macro
237 #define REG_VPU_BASE (0x0300) macro
245 #define VPU_REG_EXPC_L (REG_VPU_BASE+(0x000a<<1))
246 #define VPU_REG_EXPC_H (REG_VPU_BASE+(0x000b<<1))
248 #define VPU_REG_CPU_STATUS (REG_VPU_BASE+( 0x000f<<1))
252 #define VPU_REG_MIU_LAST (REG_VPU_BASE+( 0x0020<<1))
255 #define VPU_REG_ICU_STATUS (REG_VPU_BASE+( 0x001f<<1))
259 #define VPU_REG_ICU_DBG_SEL (REG_VPU_BASE+( 0x0010<<1))
260 #define VPU_REG_ICU_DBG_DAT0 (REG_VPU_BASE+( 0x0014<<1))
263 #define VPU_REG_DCU_DBG_SEL (REG_VPU_BASE+( 0x0028<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/vpu_v3/
H A DregVPU_EX.h231 #define REG_VPU_BASE (0x63300) macro
237 #define REG_VPU_BASE (0x0300) macro
245 #define VPU_REG_EXPC_L (REG_VPU_BASE+(0x000a<<1))
246 #define VPU_REG_EXPC_H (REG_VPU_BASE+(0x000b<<1))
248 #define VPU_REG_MIU_LAST (REG_VPU_BASE+( 0x0020<<1))
251 #define VPU_REG_ICU_STATUS (REG_VPU_BASE+( 0x001f<<1))
255 #define VPU_REG_DCU_DBG_SEL (REG_VPU_BASE+( 0x0028<<1))
258 #define VPU_REG_DCU_STATUS (REG_VPU_BASE+( 0x0029<<1))
261 #define VPU_REG_CPU_SETTING (REG_VPU_BASE+( 0x0040<<1))
274 #define VPU_REG_ICU_SDR_BASE_L (REG_VPU_BASE+(0x0041<<1)) //byte address
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/vpu_v3/
H A DregVPU_EX.h231 #define REG_VPU_BASE (0x63300) macro
237 #define REG_VPU_BASE (0x0300) macro
245 #define VPU_REG_EXPC_L (REG_VPU_BASE+(0x000a<<1))
246 #define VPU_REG_EXPC_H (REG_VPU_BASE+(0x000b<<1))
248 #define VPU_REG_CPU_STATUS (REG_VPU_BASE+( 0x000f<<1))
252 #define VPU_REG_MIU_LAST (REG_VPU_BASE+( 0x0020<<1))
255 #define VPU_REG_ICU_STATUS (REG_VPU_BASE+( 0x001f<<1))
259 #define VPU_REG_ICU_DBG_SEL (REG_VPU_BASE+( 0x0010<<1))
260 #define VPU_REG_ICU_DBG_DAT0 (REG_VPU_BASE+( 0x0014<<1))
263 #define VPU_REG_DCU_DBG_SEL (REG_VPU_BASE+( 0x0028<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/curry/vpu_v3/
H A DregVPU_EX.h231 #define REG_VPU_BASE (0x63300) macro
237 #define REG_VPU_BASE (0x0300) macro
245 #define VPU_REG_EXPC_L (REG_VPU_BASE+(0x000a<<1))
246 #define VPU_REG_EXPC_H (REG_VPU_BASE+(0x000b<<1))
248 #define VPU_REG_CPU_STATUS (REG_VPU_BASE+( 0x000f<<1))
252 #define VPU_REG_MIU_LAST (REG_VPU_BASE+( 0x0020<<1))
255 #define VPU_REG_ICU_STATUS (REG_VPU_BASE+( 0x001f<<1))
259 #define VPU_REG_ICU_DBG_SEL (REG_VPU_BASE+( 0x0010<<1))
260 #define VPU_REG_ICU_DBG_DAT0 (REG_VPU_BASE+( 0x0014<<1))
263 #define VPU_REG_DCU_DBG_SEL (REG_VPU_BASE+( 0x0028<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6lite/vpu_v3/
H A DregVPU_EX.h231 #define REG_VPU_BASE (0x63300) macro
237 #define REG_VPU_BASE (0x0300) macro
245 #define VPU_REG_EXPC_L (REG_VPU_BASE+(0x000a<<1))
246 #define VPU_REG_EXPC_H (REG_VPU_BASE+(0x000b<<1))
248 #define VPU_REG_CPU_STATUS (REG_VPU_BASE+( 0x000f<<1))
252 #define VPU_REG_MIU_LAST (REG_VPU_BASE+( 0x0020<<1))
255 #define VPU_REG_ICU_STATUS (REG_VPU_BASE+( 0x001f<<1))
259 #define VPU_REG_ICU_DBG_SEL (REG_VPU_BASE+( 0x0010<<1))
260 #define VPU_REG_ICU_DBG_DAT0 (REG_VPU_BASE+( 0x0014<<1))
263 #define VPU_REG_DCU_DBG_SEL (REG_VPU_BASE+( 0x0028<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maldives/vpu_v3/
H A DregVPU_EX.h229 #define REG_VPU_BASE (0x0300) macro
234 #define VPU_REG_EXPC_L (REG_VPU_BASE+(0x000a<<1))
235 #define VPU_REG_EXPC_H (REG_VPU_BASE+(0x000b<<1))
237 #define VPU_REG_CPU_SETTING (REG_VPU_BASE+( 0x0040<<1))
250 #define VPU_REG_ICU_SDR_BASE_L (REG_VPU_BASE+(0x0041<<1)) //byte address
251 #define VPU_REG_ICU_SDR_BASE_H (REG_VPU_BASE+(0x0042<<1))
252 #define VPU_REG_DCU_SDR_BASE_L (REG_VPU_BASE+(0x0043<<1)) //byte address
253 #define VPU_REG_DCU_SDR_BASE_H (REG_VPU_BASE+(0x0044<<1))
255 #define VPU_REG_SPI_BASE (REG_VPU_BASE+(0x0048<<1)) //REG ACCESS BASE32
258 #define VPU_REG_IQMEM_BASE_L (REG_VPU_BASE+(0x0049<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mustang/vpu_ex/
H A DregVPU_EX.h229 #define REG_VPU_BASE (0x0300) macro
234 #define VPU_REG_EXPC_L (REG_VPU_BASE+(0x000a<<1))
235 #define VPU_REG_EXPC_H (REG_VPU_BASE+(0x000b<<1))
237 #define VPU_REG_CPU_SETTING (REG_VPU_BASE+( 0x0040<<1))
250 #define VPU_REG_ICU_SDR_BASE_L (REG_VPU_BASE+(0x0041<<1)) //byte address
251 #define VPU_REG_ICU_SDR_BASE_H (REG_VPU_BASE+(0x0042<<1))
252 #define VPU_REG_DCU_SDR_BASE_L (REG_VPU_BASE+(0x0043<<1)) //byte address
253 #define VPU_REG_DCU_SDR_BASE_H (REG_VPU_BASE+(0x0044<<1))
255 #define VPU_REG_SPI_BASE (REG_VPU_BASE+(0x0048<<1)) //REG ACCESS BASE32
258 #define VPU_REG_IQMEM_BASE_L (REG_VPU_BASE+(0x0049<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mustang/vpu_v3/
H A DregVPU_EX.h229 #define REG_VPU_BASE (0x0300) macro
234 #define VPU_REG_EXPC_L (REG_VPU_BASE+(0x000a<<1))
235 #define VPU_REG_EXPC_H (REG_VPU_BASE+(0x000b<<1))
237 #define VPU_REG_CPU_SETTING (REG_VPU_BASE+( 0x0040<<1))
250 #define VPU_REG_ICU_SDR_BASE_L (REG_VPU_BASE+(0x0041<<1)) //byte address
251 #define VPU_REG_ICU_SDR_BASE_H (REG_VPU_BASE+(0x0042<<1))
252 #define VPU_REG_DCU_SDR_BASE_L (REG_VPU_BASE+(0x0043<<1)) //byte address
253 #define VPU_REG_DCU_SDR_BASE_H (REG_VPU_BASE+(0x0044<<1))
255 #define VPU_REG_SPI_BASE (REG_VPU_BASE+(0x0048<<1)) //REG ACCESS BASE32
258 #define VPU_REG_IQMEM_BASE_L (REG_VPU_BASE+(0x0049<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maldives/vpu_ex/
H A DregVPU_EX.h229 #define REG_VPU_BASE (0x0300) macro
234 #define VPU_REG_EXPC_L (REG_VPU_BASE+(0x000a<<1))
235 #define VPU_REG_EXPC_H (REG_VPU_BASE+(0x000b<<1))
237 #define VPU_REG_CPU_SETTING (REG_VPU_BASE+( 0x0040<<1))
250 #define VPU_REG_ICU_SDR_BASE_L (REG_VPU_BASE+(0x0041<<1)) //byte address
251 #define VPU_REG_ICU_SDR_BASE_H (REG_VPU_BASE+(0x0042<<1))
252 #define VPU_REG_DCU_SDR_BASE_L (REG_VPU_BASE+(0x0043<<1)) //byte address
253 #define VPU_REG_DCU_SDR_BASE_H (REG_VPU_BASE+(0x0044<<1))
255 #define VPU_REG_SPI_BASE (REG_VPU_BASE+(0x0048<<1)) //REG ACCESS BASE32
258 #define VPU_REG_IQMEM_BASE_L (REG_VPU_BASE+(0x0049<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/manhattan/vpu/
H A DregVPU.h229 #define REG_VPU_BASE (0x0300 ) macro
234 #define VPU_REG_EXPC_L (REG_VPU_BASE+(0x000a<<1))
235 #define VPU_REG_EXPC_H (REG_VPU_BASE+(0x000b<<1))
237 #define VPU_REG_CPU_SETTING (REG_VPU_BASE+( 0x0040<<1))
251 #define VPU_REG_ICU_SDR_BASE_L (REG_VPU_BASE+(0x0041<<1)) //byte address
252 #define VPU_REG_ICU_SDR_BASE_H (REG_VPU_BASE+(0x0042<<1))
253 #define VPU_REG_DCU_SDR_BASE_L (REG_VPU_BASE+( 0x0043<<1)) //byte address
254 #define VPU_REG_DCU_SDR_BASE_H (REG_VPU_BASE+(0x0044<<1))
256 #define VPU_REG_SPI_BASE (REG_VPU_BASE+(0x0048<<1)) //REG ACCESS BASE32
258 #define VPU_REG_IQMEM_BASE_L (REG_VPU_BASE+(0x0049<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/messi/vpu_ex/
H A DregVPU_EX.h229 #define REG_VPU_BASE (0x0300UL) macro
234 #define VPU_REG_EXPC_L (REG_VPU_BASE+(0x000a<<1))
235 #define VPU_REG_EXPC_H (REG_VPU_BASE+(0x000b<<1))
237 #define VPU_REG_CPU_SETTING (REG_VPU_BASE+( 0x0040<<1))
250 #define VPU_REG_ICU_SDR_BASE_L (REG_VPU_BASE+(0x0041<<1)) //byte address
251 #define VPU_REG_ICU_SDR_BASE_H (REG_VPU_BASE+(0x0042<<1))
252 #define VPU_REG_DCU_SDR_BASE_L (REG_VPU_BASE+(0x0043<<1)) //byte address
253 #define VPU_REG_DCU_SDR_BASE_H (REG_VPU_BASE+(0x0044<<1))
255 #define VPU_REG_SPI_BASE (REG_VPU_BASE+(0x0048<<1)) //REG ACCESS BASE32
258 #define VPU_REG_IQMEM_BASE_L (REG_VPU_BASE+(0x0049<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7821/vpu/
H A DregVPU.h229 #define REG_VPU_BASE (0x0300 ) macro
234 #define VPU_REG_EXPC_L (REG_VPU_BASE+(0x000a<<1))
235 #define VPU_REG_EXPC_H (REG_VPU_BASE+(0x000b<<1))
237 #define VPU_REG_CPU_SETTING (REG_VPU_BASE+( 0x0040<<1))
251 #define VPU_REG_ICU_SDR_BASE_L (REG_VPU_BASE+(0x0041<<1)) //byte address
252 #define VPU_REG_ICU_SDR_BASE_H (REG_VPU_BASE+(0x0042<<1))
253 #define VPU_REG_DCU_SDR_BASE_L (REG_VPU_BASE+( 0x0043<<1)) //byte address
254 #define VPU_REG_DCU_SDR_BASE_H (REG_VPU_BASE+(0x0044<<1))
256 #define VPU_REG_SPI_BASE (REG_VPU_BASE+(0x0048<<1)) //REG ACCESS BASE32
258 #define VPU_REG_IQMEM_BASE_L (REG_VPU_BASE+(0x0049<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mainz/vpu_ex/
H A DregVPU_EX.h229 #define REG_VPU_BASE (0x0300UL) macro
234 #define VPU_REG_EXPC_L (REG_VPU_BASE+(0x000a<<1))
235 #define VPU_REG_EXPC_H (REG_VPU_BASE+(0x000b<<1))
237 #define VPU_REG_CPU_SETTING (REG_VPU_BASE+( 0x0040<<1))
250 #define VPU_REG_ICU_SDR_BASE_L (REG_VPU_BASE+(0x0041<<1)) //byte address
251 #define VPU_REG_ICU_SDR_BASE_H (REG_VPU_BASE+(0x0042<<1))
252 #define VPU_REG_DCU_SDR_BASE_L (REG_VPU_BASE+(0x0043<<1)) //byte address
253 #define VPU_REG_DCU_SDR_BASE_H (REG_VPU_BASE+(0x0044<<1))
255 #define VPU_REG_SPI_BASE (REG_VPU_BASE+(0x0048<<1)) //REG ACCESS BASE32
258 #define VPU_REG_IQMEM_BASE_L (REG_VPU_BASE+(0x0049<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7621/vpu_ex/
H A DregVPU_EX.h229 #define REG_VPU_BASE (0x0300UL) macro
234 #define VPU_REG_EXPC_L (REG_VPU_BASE+(0x000a<<1))
235 #define VPU_REG_EXPC_H (REG_VPU_BASE+(0x000b<<1))
237 #define VPU_REG_CPU_SETTING (REG_VPU_BASE+( 0x0040<<1))
250 #define VPU_REG_ICU_SDR_BASE_L (REG_VPU_BASE+(0x0041<<1)) //byte address
251 #define VPU_REG_ICU_SDR_BASE_H (REG_VPU_BASE+(0x0042<<1))
252 #define VPU_REG_DCU_SDR_BASE_L (REG_VPU_BASE+(0x0043<<1)) //byte address
253 #define VPU_REG_DCU_SDR_BASE_H (REG_VPU_BASE+(0x0044<<1))
255 #define VPU_REG_SPI_BASE (REG_VPU_BASE+(0x0048<<1)) //REG ACCESS BASE32
258 #define VPU_REG_IQMEM_BASE_L (REG_VPU_BASE+(0x0049<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maxim/vpu_ex/
H A DregVPU_EX.h229 #define REG_VPU_BASE (0x0300UL) macro
234 #define VPU_REG_EXPC_L (REG_VPU_BASE+(0x000a<<1))
235 #define VPU_REG_EXPC_H (REG_VPU_BASE+(0x000b<<1))
237 #define VPU_REG_CPU_SETTING (REG_VPU_BASE+( 0x0040<<1))
250 #define VPU_REG_ICU_SDR_BASE_L (REG_VPU_BASE+(0x0041<<1)) //byte address
251 #define VPU_REG_ICU_SDR_BASE_H (REG_VPU_BASE+(0x0042<<1))
252 #define VPU_REG_DCU_SDR_BASE_L (REG_VPU_BASE+(0x0043<<1)) //byte address
253 #define VPU_REG_DCU_SDR_BASE_H (REG_VPU_BASE+(0x0044<<1))
255 #define VPU_REG_SPI_BASE (REG_VPU_BASE+(0x0048<<1)) //REG ACCESS BASE32
258 #define VPU_REG_IQMEM_BASE_L (REG_VPU_BASE+(0x0049<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7621/vpu/
H A DregVPU.h229 #define REG_VPU_BASE (0x0300 ) macro
234 #define VPU_REG_EXPC_L (REG_VPU_BASE+(0x000a<<1))
235 #define VPU_REG_EXPC_H (REG_VPU_BASE+(0x000b<<1))
237 #define VPU_REG_CPU_SETTING (REG_VPU_BASE+( 0x0040<<1))
251 #define VPU_REG_ICU_SDR_BASE_L (REG_VPU_BASE+(0x0041<<1)) //byte address
252 #define VPU_REG_ICU_SDR_BASE_H (REG_VPU_BASE+(0x0042<<1))
253 #define VPU_REG_DCU_SDR_BASE_L (REG_VPU_BASE+( 0x0043<<1)) //byte address
254 #define VPU_REG_DCU_SDR_BASE_H (REG_VPU_BASE+(0x0044<<1))
256 #define VPU_REG_SPI_BASE (REG_VPU_BASE+(0x0048<<1)) //REG ACCESS BASE32
258 #define VPU_REG_IQMEM_BASE_L (REG_VPU_BASE+(0x0049<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/macan/vpu_ex/
H A DregVPU_EX.h229 #define REG_VPU_BASE (0x0300UL) macro
234 #define VPU_REG_EXPC_L (REG_VPU_BASE+(0x000a<<1))
235 #define VPU_REG_EXPC_H (REG_VPU_BASE+(0x000b<<1))
237 #define VPU_REG_CPU_SETTING (REG_VPU_BASE+( 0x0040<<1))
250 #define VPU_REG_ICU_SDR_BASE_L (REG_VPU_BASE+(0x0041<<1)) //byte address
251 #define VPU_REG_ICU_SDR_BASE_H (REG_VPU_BASE+(0x0042<<1))
252 #define VPU_REG_DCU_SDR_BASE_L (REG_VPU_BASE+(0x0043<<1)) //byte address
253 #define VPU_REG_DCU_SDR_BASE_H (REG_VPU_BASE+(0x0044<<1))
255 #define VPU_REG_SPI_BASE (REG_VPU_BASE+(0x0048<<1)) //REG ACCESS BASE32
258 #define VPU_REG_IQMEM_BASE_L (REG_VPU_BASE+(0x0049<<1))
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/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/manhattan/vpu_ex/
H A DregVPU_EX.h229 #define REG_VPU_BASE (0x0300UL) macro
234 #define VPU_REG_EXPC_L (REG_VPU_BASE+(0x000a<<1))
235 #define VPU_REG_EXPC_H (REG_VPU_BASE+(0x000b<<1))
237 #define VPU_REG_CPU_SETTING (REG_VPU_BASE+( 0x0040<<1))
250 #define VPU_REG_ICU_SDR_BASE_L (REG_VPU_BASE+(0x0041<<1)) //byte address
251 #define VPU_REG_ICU_SDR_BASE_H (REG_VPU_BASE+(0x0042<<1))
252 #define VPU_REG_DCU_SDR_BASE_L (REG_VPU_BASE+(0x0043<<1)) //byte address
253 #define VPU_REG_DCU_SDR_BASE_H (REG_VPU_BASE+(0x0044<<1))
255 #define VPU_REG_SPI_BASE (REG_VPU_BASE+(0x0048<<1)) //REG ACCESS BASE32
258 #define VPU_REG_IQMEM_BASE_L (REG_VPU_BASE+(0x0049<<1))
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