| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/ |
| H A D | mhal_dip.c | 144 #define REG_TZPC_NONPM_DWIN0 (REG_TZPC_NONPM_BASE + (0x79<<1) ) macro
1846 MDrv_WriteRegBit(REG_TZPC_NONPM_DWIN0, 0, BMASK(9:8)); in HAL_XC_DIP_Enable()
1853 MDrv_WriteRegBit(REG_TZPC_NONPM_DWIN0, BMASK(9:8), BMASK(9:8)); in HAL_XC_DIP_Enable()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/ |
| H A D | mhal_dip.c | 150 #define REG_TZPC_NONPM_DWIN0 (REG_TZPC_NONPM_BASE + (0x79<<1) ) macro
2414 MDrv_WriteRegBit(REG_TZPC_NONPM_DWIN0, 0, BMASK(9:8)); in HAL_XC_DIP_Enable()
2421 MDrv_WriteRegBit(REG_TZPC_NONPM_DWIN0, BMASK(9:8), BMASK(9:8)); in HAL_XC_DIP_Enable()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_dip.c | 162 #define REG_TZPC_NONPM_DWIN0 (REG_TZPC_NONPM_BASE + (0x79<<1) ) macro
3418 MDrv_WriteRegBit(REG_TZPC_NONPM_DWIN0, BMASK(11:8), BMASK(11:8)); in HAL_XC_DIP_Enable()
3425 MDrv_WriteRegBit(REG_TZPC_NONPM_DWIN0, 0, BMASK(11:8)); in HAL_XC_DIP_Enable()
3432 MDrv_WriteRegBit(REG_TZPC_NONPM_DWIN0, BMASK(11:8), BMASK(11:8)); in HAL_XC_DIP_Enable()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_dip.c | 162 #define REG_TZPC_NONPM_DWIN0 (REG_TZPC_NONPM_BASE + (0x79<<1) ) macro
3422 MDrv_WriteRegBit(REG_TZPC_NONPM_DWIN0, BMASK(11:8), BMASK(11:8)); in HAL_XC_DIP_Enable()
3429 MDrv_WriteRegBit(REG_TZPC_NONPM_DWIN0, 0, BMASK(11:8)); in HAL_XC_DIP_Enable()
3436 MDrv_WriteRegBit(REG_TZPC_NONPM_DWIN0, BMASK(11:8), BMASK(11:8)); in HAL_XC_DIP_Enable()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_dip.c | 155 #define REG_TZPC_NONPM_DWIN0 (REG_TZPC_NONPM_BASE + (0x79<<1) ) macro
2589 MDrv_WriteRegBit(REG_TZPC_NONPM_DWIN0, 0, BMASK(11:8)); in HAL_XC_DIP_Enable()
2596 MDrv_WriteRegBit(REG_TZPC_NONPM_DWIN0, BMASK(11:8), BMASK(11:8)); in HAL_XC_DIP_Enable()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_dip.h | 101 #define REG_TZPC_NONPM_DWIN0 (REG_TZPC_NONPM_BASE + (0x79<<1) ) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_dip.c | 155 #define REG_TZPC_NONPM_DWIN0 (REG_TZPC_NONPM_BASE + (0x79<<1) ) macro
2951 MDrv_WriteRegBit(REG_TZPC_NONPM_DWIN0, 0, BMASK(9:8)); in HAL_XC_DIP_Enable()
2958 MDrv_WriteRegBit(REG_TZPC_NONPM_DWIN0, BMASK(9:8), BMASK(9:8)); in HAL_XC_DIP_Enable()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_dip.c | 155 #define REG_TZPC_NONPM_DWIN0 (REG_TZPC_NONPM_BASE + (0x79<<1) ) macro
2969 MDrv_WriteRegBit(REG_TZPC_NONPM_DWIN0, 0, BMASK(9:8)); in HAL_XC_DIP_Enable()
2976 MDrv_WriteRegBit(REG_TZPC_NONPM_DWIN0, BMASK(9:8), BMASK(9:8)); in HAL_XC_DIP_Enable()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_dip.c | 159 #define REG_TZPC_NONPM_DWIN0 (REG_TZPC_NONPM_BASE + (0x79<<1) ) macro
2805 MDrv_WriteRegBit(REG_TZPC_NONPM_DWIN0, 0, BMASK(11:8)); in HAL_XC_DIP_Enable()
2812 MDrv_WriteRegBit(REG_TZPC_NONPM_DWIN0, BMASK(11:8), BMASK(11:8)); in HAL_XC_DIP_Enable()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_dip.c | 161 #define REG_TZPC_NONPM_DWIN0 (REG_TZPC_NONPM_BASE + (0x79<<1) ) macro
3472 MDrv_WriteRegBit(REG_TZPC_NONPM_DWIN0, 0, BMASK(11:8)); in HAL_XC_DIP_Enable()
3479 MDrv_WriteRegBit(REG_TZPC_NONPM_DWIN0, BMASK(11:8), BMASK(11:8)); in HAL_XC_DIP_Enable()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_dip.c | 162 #define REG_TZPC_NONPM_DWIN0 (REG_TZPC_NONPM_BASE + (0x79<<1) ) macro
3474 MDrv_WriteRegBit(REG_TZPC_NONPM_DWIN0, 0, BMASK(11:8)); in HAL_XC_DIP_Enable()
3481 MDrv_WriteRegBit(REG_TZPC_NONPM_DWIN0, BMASK(11:8), BMASK(11:8)); in HAL_XC_DIP_Enable()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/ |
| H A D | mhal_dip.c | 165 #define REG_TZPC_NONPM_DWIN0 (REG_TZPC_NONPM_BASE + (0x79<<1) ) macro
3912 MDrv_WriteRegBit(REG_TZPC_NONPM_DWIN0, 0, BMASK(9:8)); in HAL_XC_DIP_Enable()
3919 MDrv_WriteRegBit(REG_TZPC_NONPM_DWIN0, BMASK(9:8), BMASK(9:8)); in HAL_XC_DIP_Enable()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/ |
| H A D | mhal_dip.c | 4393 MDrv_WriteRegBit(REG_TZPC_NONPM_DWIN0, 0, BMASK(9:8)); in HAL_XC_DIP_Enable()
4400 MDrv_WriteRegBit(REG_TZPC_NONPM_DWIN0, BMASK(9:8), BMASK(9:8)); in HAL_XC_DIP_Enable()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/ |
| H A D | mhal_dip.c | 151 #define REG_TZPC_NONPM_DWIN0 (REG_TZPC_NONPM_BASE + (0x79<<1) ) macro
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