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Searched refs:REG_TC_HDMITX_PLL_10_H (Results 1 – 23 of 23) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/
H A Dhal_dac_tbl.c446 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
479 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x66/*ALL*/, },
512 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x00/*ALL*/, },
545 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
977 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
1010 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x66/*ALL*/, },
1043 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x00/*ALL*/, },
1076 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
1512 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
1545 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x66/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/
H A Dhal_dac_tbl.c440 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
473 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x66/*ALL*/, },
506 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x00/*ALL*/, },
539 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
965 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
998 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x66/*ALL*/, },
1031 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x00/*ALL*/, },
1064 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
1494 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
1527 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x66/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/
H A Dhal_dac_tbl.c446 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
479 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x66/*ALL*/, },
512 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x00/*ALL*/, },
545 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
977 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
1010 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x66/*ALL*/, },
1043 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x00/*ALL*/, },
1076 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
1512 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
1545 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x66/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/include/
H A Dmdrv_dac_tbl.c425 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
458 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x66/*ALL*/, },
491 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x00/*ALL*/, },
524 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
935 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
968 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x66/*ALL*/, },
1001 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x00/*ALL*/, },
1034 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
1449 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
1482 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x66/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h7288 #define REG_TC_HDMITX_PLL_10_H (REG_TC_HDMITX_PLL_BASE + 0x21) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/include/
H A Dmdrv_dac_tbl.c425 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
458 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x66/*ALL*/, },
491 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x00/*ALL*/, },
524 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
935 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
968 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x66/*ALL*/, },
1001 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x00/*ALL*/, },
1034 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
1449 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
1482 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x66/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h7288 #define REG_TC_HDMITX_PLL_10_H (REG_TC_HDMITX_PLL_BASE + 0x21) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/
H A Dhal_dac_tbl.c440 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
473 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x66/*ALL*/, },
506 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x00/*ALL*/, },
539 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
965 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
998 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x66/*ALL*/, },
1031 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x00/*ALL*/, },
1064 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
1494 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
1527 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x66/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/
H A Dmdrv_dac_tbl.c425 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
458 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x66/*ALL*/, },
491 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x00/*ALL*/, },
524 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
935 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
968 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x66/*ALL*/, },
1001 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x00/*ALL*/, },
1034 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
1449 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
1482 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x66/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h7288 #define REG_TC_HDMITX_PLL_10_H (REG_TC_HDMITX_PLL_BASE + 0x21) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/include/
H A Dmdrv_dac_tbl.c425 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
458 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x66/*ALL*/, },
491 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x00/*ALL*/, },
524 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
935 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
968 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x66/*ALL*/, },
1001 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x00/*ALL*/, },
1034 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
1449 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x99/*ALL*/, },
1482 { DRV_DAC_REG(REG_TC_HDMITX_PLL_10_H), 0xFF, 0x66/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h7288 #define REG_TC_HDMITX_PLL_10_H (REG_TC_HDMITX_PLL_BASE + 0x21) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A Dmdrv_dac_tbl.h3349 #define REG_TC_HDMITX_PLL_10_H (REG_TC_HDMITX_PLL_BASE + 0x21) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A Dmdrv_dac_tbl.h3349 #define REG_TC_HDMITX_PLL_10_H (REG_TC_HDMITX_PLL_BASE + 0x21) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A Dmdrv_dac_tbl.h3349 #define REG_TC_HDMITX_PLL_10_H (REG_TC_HDMITX_PLL_BASE + 0x21) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A Dmdrv_dac_tbl.h3349 #define REG_TC_HDMITX_PLL_10_H (REG_TC_HDMITX_PLL_BASE + 0x21) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A Dmdrv_dac_tbl.h3349 #define REG_TC_HDMITX_PLL_10_H (REG_TC_HDMITX_PLL_BASE + 0x21) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A Dmdrv_dac_tbl.h3349 #define REG_TC_HDMITX_PLL_10_H (REG_TC_HDMITX_PLL_BASE + 0x21) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A Dmdrv_dac_tbl.h3349 #define REG_TC_HDMITX_PLL_10_H (REG_TC_HDMITX_PLL_BASE + 0x21) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A Dmdrv_dac_tbl.h3349 #define REG_TC_HDMITX_PLL_10_H (REG_TC_HDMITX_PLL_BASE + 0x21) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A Dmdrv_dac_tbl.h3349 #define REG_TC_HDMITX_PLL_10_H (REG_TC_HDMITX_PLL_BASE + 0x21) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A Dmdrv_dac_tbl.h3349 #define REG_TC_HDMITX_PLL_10_H (REG_TC_HDMITX_PLL_BASE + 0x21) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A Dmdrv_dac_tbl.h3349 #define REG_TC_HDMITX_PLL_10_H (REG_TC_HDMITX_PLL_BASE + 0x21) macro