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Searched refs:REG_TC_HDGEN_BK1_48_L (Results 1 – 23 of 23) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/
H A Dhal_dac_tbl.c357 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x15/*ALL*/, },
888 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x15/*ALL*/, },
1423 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x15/*ALL*/, },
1954 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x15/*ALL*/, },
2485 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0d/*ALL*/, },
3016 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0d/*ALL*/, },
3551 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0d/*ALL*/, },
4086 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0d/*ALL*/, },
4617 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0c/*ALL*/, },
5149 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0c/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/
H A Dhal_dac_tbl.c349 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x15/*ALL*/, },
874 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x15/*ALL*/, },
1403 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x15/*ALL*/, },
1928 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x15/*ALL*/, },
2453 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0d/*ALL*/, },
2978 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0d/*ALL*/, },
3507 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0d/*ALL*/, },
4036 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0d/*ALL*/, },
4561 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0c/*ALL*/, },
5086 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0c/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/
H A Dhal_dac_tbl.c357 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x15/*ALL*/, },
888 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x15/*ALL*/, },
1423 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x15/*ALL*/, },
1954 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x15/*ALL*/, },
2485 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0d/*ALL*/, },
3016 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0d/*ALL*/, },
3551 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0d/*ALL*/, },
4086 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0d/*ALL*/, },
4617 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0c/*ALL*/, },
5148 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0c/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/include/
H A Dmdrv_dac_tbl.c352 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x15/*ALL*/, },
862 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x15/*ALL*/, },
1376 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x15/*ALL*/, },
1886 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x15/*ALL*/, },
2396 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0d/*ALL*/, },
2906 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0d/*ALL*/, },
3420 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0d/*ALL*/, },
3934 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0d/*ALL*/, },
4444 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0c/*ALL*/, },
4954 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0c/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6885 #define REG_TC_HDGEN_BK1_48_L _PK_L_(0x1, 0x48) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/include/
H A Dmdrv_dac_tbl.c352 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x15/*ALL*/, },
862 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x15/*ALL*/, },
1376 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x15/*ALL*/, },
1886 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x15/*ALL*/, },
2396 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0d/*ALL*/, },
2906 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0d/*ALL*/, },
3420 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0d/*ALL*/, },
3934 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0d/*ALL*/, },
4444 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0c/*ALL*/, },
4954 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0c/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6885 #define REG_TC_HDGEN_BK1_48_L _PK_L_(0x1, 0x48) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/
H A Dhal_dac_tbl.c349 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x15/*ALL*/, },
874 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x15/*ALL*/, },
1403 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x15/*ALL*/, },
1928 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x15/*ALL*/, },
2453 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0d/*ALL*/, },
2978 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0d/*ALL*/, },
3507 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0d/*ALL*/, },
4036 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0d/*ALL*/, },
4561 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0c/*ALL*/, },
5086 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0c/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/
H A Dmdrv_dac_tbl.c352 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x15/*ALL*/, },
862 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x15/*ALL*/, },
1376 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x15/*ALL*/, },
1886 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x15/*ALL*/, },
2396 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0d/*ALL*/, },
2906 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0d/*ALL*/, },
3420 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0d/*ALL*/, },
3934 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0d/*ALL*/, },
4444 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0c/*ALL*/, },
4954 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0c/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6885 #define REG_TC_HDGEN_BK1_48_L _PK_L_(0x1, 0x48) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/include/
H A Dmdrv_dac_tbl.c352 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x15/*ALL*/, },
862 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x15/*ALL*/, },
1376 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x15/*ALL*/, },
1886 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x15/*ALL*/, },
2396 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0d/*ALL*/, },
2906 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0d/*ALL*/, },
3420 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0d/*ALL*/, },
3934 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0d/*ALL*/, },
4444 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0c/*ALL*/, },
4954 { DRV_DAC_REG(REG_TC_HDGEN_BK1_48_L), 0xFF, 0x0c/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6885 #define REG_TC_HDGEN_BK1_48_L _PK_L_(0x1, 0x48) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A Dmdrv_dac_tbl.h3203 #define REG_TC_HDGEN_BK1_48_L _PK_L_(0x1, 0x48) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A Dmdrv_dac_tbl.h3203 #define REG_TC_HDGEN_BK1_48_L _PK_L_(0x1, 0x48) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A Dmdrv_dac_tbl.h3203 #define REG_TC_HDGEN_BK1_48_L _PK_L_(0x1, 0x48) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A Dmdrv_dac_tbl.h3203 #define REG_TC_HDGEN_BK1_48_L _PK_L_(0x1, 0x48) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A Dmdrv_dac_tbl.h3203 #define REG_TC_HDGEN_BK1_48_L _PK_L_(0x1, 0x48) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A Dmdrv_dac_tbl.h3203 #define REG_TC_HDGEN_BK1_48_L _PK_L_(0x1, 0x48) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A Dmdrv_dac_tbl.h3203 #define REG_TC_HDGEN_BK1_48_L _PK_L_(0x1, 0x48) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A Dmdrv_dac_tbl.h3203 #define REG_TC_HDGEN_BK1_48_L _PK_L_(0x1, 0x48) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A Dmdrv_dac_tbl.h3203 #define REG_TC_HDGEN_BK1_48_L _PK_L_(0x1, 0x48) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A Dmdrv_dac_tbl.h3203 #define REG_TC_HDGEN_BK1_48_L _PK_L_(0x1, 0x48) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A Dmdrv_dac_tbl.h3203 #define REG_TC_HDGEN_BK1_48_L _PK_L_(0x1, 0x48) macro