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Searched refs:REG_TC_HDGEN_BK1_43_L (Results 1 – 23 of 23) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/
H A Dhal_dac_tbl.c347 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x18/*ALL*/, },
878 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x18/*ALL*/, },
1413 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x18/*ALL*/, },
1944 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x18/*ALL*/, },
2475 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2b/*ALL*/, },
3006 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2b/*ALL*/, },
3541 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2b/*ALL*/, },
4076 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2b/*ALL*/, },
4607 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2f/*ALL*/, },
5139 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2f/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/
H A Dhal_dac_tbl.c339 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x18/*ALL*/, },
864 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x18/*ALL*/, },
1393 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x18/*ALL*/, },
1918 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x18/*ALL*/, },
2443 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x00/*ALL*/, },
2968 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x00/*ALL*/, },
3497 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2b/*ALL*/, },
4026 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2b/*ALL*/, },
4551 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x00/*ALL*/, },
5076 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/
H A Dhal_dac_tbl.c347 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x18/*ALL*/, },
878 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x18/*ALL*/, },
1413 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x18/*ALL*/, },
1944 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x18/*ALL*/, },
2475 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2b/*ALL*/, },
3006 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2b/*ALL*/, },
3541 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2b/*ALL*/, },
4076 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2b/*ALL*/, },
4607 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2f/*ALL*/, },
5138 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2f/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/include/
H A Dmdrv_dac_tbl.c342 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x18/*ALL*/, },
852 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x18/*ALL*/, },
1366 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x18/*ALL*/, },
1876 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x18/*ALL*/, },
2386 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2b/*ALL*/, },
2896 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2b/*ALL*/, },
3410 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2b/*ALL*/, },
3924 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2b/*ALL*/, },
4434 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2f/*ALL*/, },
4944 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2f/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6875 #define REG_TC_HDGEN_BK1_43_L _PK_L_(0x1, 0x43) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/include/
H A Dmdrv_dac_tbl.c342 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x18/*ALL*/, },
852 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x18/*ALL*/, },
1366 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x18/*ALL*/, },
1876 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x18/*ALL*/, },
2386 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2b/*ALL*/, },
2896 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2b/*ALL*/, },
3410 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2b/*ALL*/, },
3924 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2b/*ALL*/, },
4434 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2f/*ALL*/, },
4944 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2f/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6875 #define REG_TC_HDGEN_BK1_43_L _PK_L_(0x1, 0x43) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/
H A Dhal_dac_tbl.c339 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x18/*ALL*/, },
864 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x18/*ALL*/, },
1393 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x18/*ALL*/, },
1918 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x18/*ALL*/, },
2443 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x00/*ALL*/, },
2968 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x00/*ALL*/, },
3497 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2b/*ALL*/, },
4026 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2b/*ALL*/, },
4551 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x00/*ALL*/, },
5076 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/
H A Dmdrv_dac_tbl.c342 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x18/*ALL*/, },
852 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x18/*ALL*/, },
1366 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x18/*ALL*/, },
1876 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x18/*ALL*/, },
2386 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2b/*ALL*/, },
2896 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2b/*ALL*/, },
3410 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2b/*ALL*/, },
3924 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2b/*ALL*/, },
4434 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2f/*ALL*/, },
4944 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2f/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6875 #define REG_TC_HDGEN_BK1_43_L _PK_L_(0x1, 0x43) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/include/
H A Dmdrv_dac_tbl.c342 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x18/*ALL*/, },
852 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x18/*ALL*/, },
1366 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x18/*ALL*/, },
1876 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x18/*ALL*/, },
2386 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2b/*ALL*/, },
2896 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2b/*ALL*/, },
3410 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2b/*ALL*/, },
3924 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2b/*ALL*/, },
4434 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2f/*ALL*/, },
4944 { DRV_DAC_REG(REG_TC_HDGEN_BK1_43_L), 0xFF, 0x2f/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6875 #define REG_TC_HDGEN_BK1_43_L _PK_L_(0x1, 0x43) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A Dmdrv_dac_tbl.h3193 #define REG_TC_HDGEN_BK1_43_L _PK_L_(0x1, 0x43) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A Dmdrv_dac_tbl.h3193 #define REG_TC_HDGEN_BK1_43_L _PK_L_(0x1, 0x43) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A Dmdrv_dac_tbl.h3193 #define REG_TC_HDGEN_BK1_43_L _PK_L_(0x1, 0x43) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A Dmdrv_dac_tbl.h3193 #define REG_TC_HDGEN_BK1_43_L _PK_L_(0x1, 0x43) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A Dmdrv_dac_tbl.h3193 #define REG_TC_HDGEN_BK1_43_L _PK_L_(0x1, 0x43) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A Dmdrv_dac_tbl.h3193 #define REG_TC_HDGEN_BK1_43_L _PK_L_(0x1, 0x43) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A Dmdrv_dac_tbl.h3193 #define REG_TC_HDGEN_BK1_43_L _PK_L_(0x1, 0x43) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A Dmdrv_dac_tbl.h3193 #define REG_TC_HDGEN_BK1_43_L _PK_L_(0x1, 0x43) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A Dmdrv_dac_tbl.h3193 #define REG_TC_HDGEN_BK1_43_L _PK_L_(0x1, 0x43) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A Dmdrv_dac_tbl.h3193 #define REG_TC_HDGEN_BK1_43_L _PK_L_(0x1, 0x43) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A Dmdrv_dac_tbl.h3193 #define REG_TC_HDGEN_BK1_43_L _PK_L_(0x1, 0x43) macro