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Searched refs:REG_TC_HDGEN_BK1_41_L (Results 1 – 23 of 23) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/
H A Dhal_dac_tbl.c343 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x01/*ALL*/, },
874 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x01/*ALL*/, },
1409 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x01/*ALL*/, },
1940 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x01/*ALL*/, },
2471 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x2b/*ALL*/, },
3002 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x2b/*ALL*/, },
3537 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x2b/*ALL*/, },
4072 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x2b/*ALL*/, },
4603 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x1b/*ALL*/, },
5135 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x1b/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/
H A Dhal_dac_tbl.c335 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x01/*ALL*/, },
860 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x01/*ALL*/, },
1389 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x01/*ALL*/, },
1914 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x01/*ALL*/, },
2439 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x00/*ALL*/, },
2964 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x00/*ALL*/, },
3493 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x2b/*ALL*/, },
4022 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x2b/*ALL*/, },
4547 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x00/*ALL*/, },
5072 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/
H A Dhal_dac_tbl.c343 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x01/*ALL*/, },
874 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x01/*ALL*/, },
1409 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x01/*ALL*/, },
1940 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x01/*ALL*/, },
2471 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x2b/*ALL*/, },
3002 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x2b/*ALL*/, },
3537 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x2b/*ALL*/, },
4072 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x2b/*ALL*/, },
4603 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x1b/*ALL*/, },
5134 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x1b/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/include/
H A Dmdrv_dac_tbl.c338 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x01/*ALL*/, },
848 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x01/*ALL*/, },
1362 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x01/*ALL*/, },
1872 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x01/*ALL*/, },
2382 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x2b/*ALL*/, },
2892 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x2b/*ALL*/, },
3406 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x2b/*ALL*/, },
3920 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x2b/*ALL*/, },
4430 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x1b/*ALL*/, },
4940 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x1b/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6871 #define REG_TC_HDGEN_BK1_41_L _PK_L_(0x1, 0x41) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/include/
H A Dmdrv_dac_tbl.c338 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x01/*ALL*/, },
848 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x01/*ALL*/, },
1362 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x01/*ALL*/, },
1872 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x01/*ALL*/, },
2382 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x2b/*ALL*/, },
2892 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x2b/*ALL*/, },
3406 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x2b/*ALL*/, },
3920 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x2b/*ALL*/, },
4430 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x1b/*ALL*/, },
4940 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x1b/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6871 #define REG_TC_HDGEN_BK1_41_L _PK_L_(0x1, 0x41) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/
H A Dhal_dac_tbl.c335 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x01/*ALL*/, },
860 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x01/*ALL*/, },
1389 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x01/*ALL*/, },
1914 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x01/*ALL*/, },
2439 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x00/*ALL*/, },
2964 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x00/*ALL*/, },
3493 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x2b/*ALL*/, },
4022 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x2b/*ALL*/, },
4547 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x00/*ALL*/, },
5072 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/
H A Dmdrv_dac_tbl.c338 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x01/*ALL*/, },
848 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x01/*ALL*/, },
1362 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x01/*ALL*/, },
1872 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x01/*ALL*/, },
2382 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x2b/*ALL*/, },
2892 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x2b/*ALL*/, },
3406 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x2b/*ALL*/, },
3920 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x2b/*ALL*/, },
4430 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x1b/*ALL*/, },
4940 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x1b/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6871 #define REG_TC_HDGEN_BK1_41_L _PK_L_(0x1, 0x41) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/include/
H A Dmdrv_dac_tbl.c338 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x01/*ALL*/, },
848 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x01/*ALL*/, },
1362 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x01/*ALL*/, },
1872 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x01/*ALL*/, },
2382 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x2b/*ALL*/, },
2892 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x2b/*ALL*/, },
3406 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x2b/*ALL*/, },
3920 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x2b/*ALL*/, },
4430 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x1b/*ALL*/, },
4940 { DRV_DAC_REG(REG_TC_HDGEN_BK1_41_L), 0xFF, 0x1b/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6871 #define REG_TC_HDGEN_BK1_41_L _PK_L_(0x1, 0x41) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A Dmdrv_dac_tbl.h3189 #define REG_TC_HDGEN_BK1_41_L _PK_L_(0x1, 0x41) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A Dmdrv_dac_tbl.h3189 #define REG_TC_HDGEN_BK1_41_L _PK_L_(0x1, 0x41) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A Dmdrv_dac_tbl.h3189 #define REG_TC_HDGEN_BK1_41_L _PK_L_(0x1, 0x41) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A Dmdrv_dac_tbl.h3189 #define REG_TC_HDGEN_BK1_41_L _PK_L_(0x1, 0x41) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A Dmdrv_dac_tbl.h3189 #define REG_TC_HDGEN_BK1_41_L _PK_L_(0x1, 0x41) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A Dmdrv_dac_tbl.h3189 #define REG_TC_HDGEN_BK1_41_L _PK_L_(0x1, 0x41) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A Dmdrv_dac_tbl.h3189 #define REG_TC_HDGEN_BK1_41_L _PK_L_(0x1, 0x41) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A Dmdrv_dac_tbl.h3189 #define REG_TC_HDGEN_BK1_41_L _PK_L_(0x1, 0x41) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A Dmdrv_dac_tbl.h3189 #define REG_TC_HDGEN_BK1_41_L _PK_L_(0x1, 0x41) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A Dmdrv_dac_tbl.h3189 #define REG_TC_HDGEN_BK1_41_L _PK_L_(0x1, 0x41) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A Dmdrv_dac_tbl.h3189 #define REG_TC_HDGEN_BK1_41_L _PK_L_(0x1, 0x41) macro