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Searched refs:REG_TC_HDGEN_BK1_3D_H (Results 1 – 23 of 23) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/
H A Dhal_dac_tbl.c334 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
865 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
1400 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x00/*ALL*/, },
1931 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
2462 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
2993 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
3528 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
4063 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
4594 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
5126 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/
H A Dhal_dac_tbl.c326 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
851 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
1380 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x00/*ALL*/, },
1905 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
2430 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
2955 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
3484 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
4013 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
4538 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
5063 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/
H A Dhal_dac_tbl.c334 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
865 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
1400 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x00/*ALL*/, },
1931 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
2462 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
2993 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
3528 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
4063 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
4594 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
5125 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/include/
H A Dmdrv_dac_tbl.c329 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
839 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
1353 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x00/*ALL*/, },
1863 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
2373 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
2883 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
3397 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
3911 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
4421 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
4931 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6864 #define REG_TC_HDGEN_BK1_3D_H _PK_H_(0x1, 0x3D) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/include/
H A Dmdrv_dac_tbl.c329 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
839 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
1353 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x00/*ALL*/, },
1863 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
2373 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
2883 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
3397 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
3911 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
4421 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
4931 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6864 #define REG_TC_HDGEN_BK1_3D_H _PK_H_(0x1, 0x3D) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/
H A Dhal_dac_tbl.c326 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
851 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
1380 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x00/*ALL*/, },
1905 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
2430 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
2955 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
3484 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
4013 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
4538 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
5063 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/
H A Dmdrv_dac_tbl.c329 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
839 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
1353 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x00/*ALL*/, },
1863 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
2373 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
2883 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
3397 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
3911 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
4421 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
4931 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6864 #define REG_TC_HDGEN_BK1_3D_H _PK_H_(0x1, 0x3D) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/include/
H A Dmdrv_dac_tbl.c329 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
839 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
1353 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x00/*ALL*/, },
1863 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
2373 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
2883 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
3397 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
3911 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
4421 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
4931 { DRV_DAC_REG(REG_TC_HDGEN_BK1_3D_H), 0xFF, 0x02/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6864 #define REG_TC_HDGEN_BK1_3D_H _PK_H_(0x1, 0x3D) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A Dmdrv_dac_tbl.h3182 #define REG_TC_HDGEN_BK1_3D_H _PK_H_(0x1, 0x3D) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A Dmdrv_dac_tbl.h3182 #define REG_TC_HDGEN_BK1_3D_H _PK_H_(0x1, 0x3D) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A Dmdrv_dac_tbl.h3182 #define REG_TC_HDGEN_BK1_3D_H _PK_H_(0x1, 0x3D) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A Dmdrv_dac_tbl.h3182 #define REG_TC_HDGEN_BK1_3D_H _PK_H_(0x1, 0x3D) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A Dmdrv_dac_tbl.h3182 #define REG_TC_HDGEN_BK1_3D_H _PK_H_(0x1, 0x3D) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A Dmdrv_dac_tbl.h3182 #define REG_TC_HDGEN_BK1_3D_H _PK_H_(0x1, 0x3D) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A Dmdrv_dac_tbl.h3182 #define REG_TC_HDGEN_BK1_3D_H _PK_H_(0x1, 0x3D) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A Dmdrv_dac_tbl.h3182 #define REG_TC_HDGEN_BK1_3D_H _PK_H_(0x1, 0x3D) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A Dmdrv_dac_tbl.h3182 #define REG_TC_HDGEN_BK1_3D_H _PK_H_(0x1, 0x3D) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A Dmdrv_dac_tbl.h3182 #define REG_TC_HDGEN_BK1_3D_H _PK_H_(0x1, 0x3D) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A Dmdrv_dac_tbl.h3182 #define REG_TC_HDGEN_BK1_3D_H _PK_H_(0x1, 0x3D) macro