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Searched refs:REG_TC_HDGEN_BK1_32_L (Results 1 – 23 of 23) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/
H A Dhal_dac_tbl.c311 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
842 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
1377 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
1908 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
2439 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
2970 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
3505 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
4040 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
4571 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
5103 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/
H A Dhal_dac_tbl.c303 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
828 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
1357 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
1882 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
2407 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
2932 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
3461 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
3990 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
4515 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
5040 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/
H A Dhal_dac_tbl.c311 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
842 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
1377 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
1908 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
2439 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
2970 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
3505 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
4040 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
4571 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
5102 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/include/
H A Dmdrv_dac_tbl.c306 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
816 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
1330 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
1840 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
2350 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
2860 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
3374 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
3888 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
4398 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
4908 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6841 #define REG_TC_HDGEN_BK1_32_L _PK_L_(0x1, 0x32) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/include/
H A Dmdrv_dac_tbl.c306 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
816 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
1330 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
1840 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
2350 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
2860 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
3374 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
3888 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
4398 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
4908 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6841 #define REG_TC_HDGEN_BK1_32_L _PK_L_(0x1, 0x32) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/
H A Dhal_dac_tbl.c303 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
828 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
1357 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
1882 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
2407 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
2932 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
3461 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
3990 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
4515 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
5040 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/
H A Dmdrv_dac_tbl.c306 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
816 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
1330 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
1840 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
2350 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
2860 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
3374 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
3888 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
4398 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
4908 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6841 #define REG_TC_HDGEN_BK1_32_L _PK_L_(0x1, 0x32) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/include/
H A Dmdrv_dac_tbl.c306 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
816 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
1330 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
1840 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
2350 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
2860 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
3374 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
3888 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
4398 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
4908 { DRV_DAC_REG(REG_TC_HDGEN_BK1_32_L), 0xFF, 0x91/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6841 #define REG_TC_HDGEN_BK1_32_L _PK_L_(0x1, 0x32) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A Dmdrv_dac_tbl.h3159 #define REG_TC_HDGEN_BK1_32_L _PK_L_(0x1, 0x32) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A Dmdrv_dac_tbl.h3159 #define REG_TC_HDGEN_BK1_32_L _PK_L_(0x1, 0x32) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A Dmdrv_dac_tbl.h3159 #define REG_TC_HDGEN_BK1_32_L _PK_L_(0x1, 0x32) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A Dmdrv_dac_tbl.h3159 #define REG_TC_HDGEN_BK1_32_L _PK_L_(0x1, 0x32) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A Dmdrv_dac_tbl.h3159 #define REG_TC_HDGEN_BK1_32_L _PK_L_(0x1, 0x32) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A Dmdrv_dac_tbl.h3159 #define REG_TC_HDGEN_BK1_32_L _PK_L_(0x1, 0x32) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A Dmdrv_dac_tbl.h3159 #define REG_TC_HDGEN_BK1_32_L _PK_L_(0x1, 0x32) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A Dmdrv_dac_tbl.h3159 #define REG_TC_HDGEN_BK1_32_L _PK_L_(0x1, 0x32) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A Dmdrv_dac_tbl.h3159 #define REG_TC_HDGEN_BK1_32_L _PK_L_(0x1, 0x32) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A Dmdrv_dac_tbl.h3159 #define REG_TC_HDGEN_BK1_32_L _PK_L_(0x1, 0x32) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A Dmdrv_dac_tbl.h3159 #define REG_TC_HDGEN_BK1_32_L _PK_L_(0x1, 0x32) macro