Home
last modified time | relevance | path

Searched refs:REG_TC_HDGEN_BK1_30_H (Results 1 – 23 of 23) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/
H A Dhal_dac_tbl.c308 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
839 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
1374 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
1905 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
2436 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
2967 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
3502 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
4037 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
4568 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
5100 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/
H A Dhal_dac_tbl.c300 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
825 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
1354 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
1879 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
2404 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
2929 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
3458 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
3987 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
4512 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
5037 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/
H A Dhal_dac_tbl.c308 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
839 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
1374 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
1905 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
2436 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
2967 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
3502 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
4037 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
4568 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
5099 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/include/
H A Dmdrv_dac_tbl.c303 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
813 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
1327 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
1837 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
2347 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
2857 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
3371 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
3885 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
4395 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
4905 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6838 #define REG_TC_HDGEN_BK1_30_H _PK_H_(0x1, 0x30) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/include/
H A Dmdrv_dac_tbl.c303 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
813 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
1327 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
1837 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
2347 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
2857 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
3371 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
3885 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
4395 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
4905 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6838 #define REG_TC_HDGEN_BK1_30_H _PK_H_(0x1, 0x30) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/
H A Dhal_dac_tbl.c300 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
825 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
1354 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
1879 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
2404 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
2929 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
3458 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
3987 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
4512 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
5037 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/
H A Dmdrv_dac_tbl.c303 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
813 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
1327 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
1837 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
2347 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
2857 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
3371 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
3885 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
4395 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
4905 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6838 #define REG_TC_HDGEN_BK1_30_H _PK_H_(0x1, 0x30) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/include/
H A Dmdrv_dac_tbl.c303 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
813 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
1327 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
1837 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
2347 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
2857 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
3371 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
3885 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
4395 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
4905 { DRV_DAC_REG(REG_TC_HDGEN_BK1_30_H), 0xFF, 0x01/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6838 #define REG_TC_HDGEN_BK1_30_H _PK_H_(0x1, 0x30) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A Dmdrv_dac_tbl.h3156 #define REG_TC_HDGEN_BK1_30_H _PK_H_(0x1, 0x30) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A Dmdrv_dac_tbl.h3156 #define REG_TC_HDGEN_BK1_30_H _PK_H_(0x1, 0x30) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A Dmdrv_dac_tbl.h3156 #define REG_TC_HDGEN_BK1_30_H _PK_H_(0x1, 0x30) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A Dmdrv_dac_tbl.h3156 #define REG_TC_HDGEN_BK1_30_H _PK_H_(0x1, 0x30) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A Dmdrv_dac_tbl.h3156 #define REG_TC_HDGEN_BK1_30_H _PK_H_(0x1, 0x30) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A Dmdrv_dac_tbl.h3156 #define REG_TC_HDGEN_BK1_30_H _PK_H_(0x1, 0x30) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A Dmdrv_dac_tbl.h3156 #define REG_TC_HDGEN_BK1_30_H _PK_H_(0x1, 0x30) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A Dmdrv_dac_tbl.h3156 #define REG_TC_HDGEN_BK1_30_H _PK_H_(0x1, 0x30) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A Dmdrv_dac_tbl.h3156 #define REG_TC_HDGEN_BK1_30_H _PK_H_(0x1, 0x30) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A Dmdrv_dac_tbl.h3156 #define REG_TC_HDGEN_BK1_30_H _PK_H_(0x1, 0x30) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A Dmdrv_dac_tbl.h3156 #define REG_TC_HDGEN_BK1_30_H _PK_H_(0x1, 0x30) macro