Home
last modified time | relevance | path

Searched refs:REG_TC_HDGEN_BK1_01_H (Results 1 – 23 of 23) sorted by relevance

/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/
H A Dhal_dac_tbl.c242 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x01/*ALL*/, },
773 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
1308 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x01/*ALL*/, },
1839 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
2370 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
2901 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
3436 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x01/*ALL*/, },
3971 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x01/*ALL*/, },
4502 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
5034 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/
H A Dhal_dac_tbl.c234 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x01/*ALL*/, },
759 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
1288 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x01/*ALL*/, },
1813 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
2338 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
2863 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
3392 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x01/*ALL*/, },
3921 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x01/*ALL*/, },
4446 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
4971 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/
H A Dhal_dac_tbl.c242 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x01/*ALL*/, },
773 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
1308 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x01/*ALL*/, },
1839 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
2370 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
2901 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
3436 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x01/*ALL*/, },
3971 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x01/*ALL*/, },
4502 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
5033 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/kano/dac/include/
H A Dmdrv_dac_tbl.c237 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x01/*ALL*/, },
747 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
1261 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x01/*ALL*/, },
1771 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
2281 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
2791 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
3305 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x01/*ALL*/, },
3819 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x01/*ALL*/, },
4329 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
4839 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6744 #define REG_TC_HDGEN_BK1_01_H _PK_H_(0x1, 0x01) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/curry/dac/include/
H A Dmdrv_dac_tbl.c237 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x01/*ALL*/, },
747 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
1261 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x01/*ALL*/, },
1771 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
2281 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
2791 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
3305 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x01/*ALL*/, },
3819 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x01/*ALL*/, },
4329 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
4839 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6744 #define REG_TC_HDGEN_BK1_01_H _PK_H_(0x1, 0x01) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/
H A Dhal_dac_tbl.c234 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x01/*ALL*/, },
759 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
1288 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x01/*ALL*/, },
1813 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
2338 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
2863 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
3392 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x01/*ALL*/, },
3921 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x01/*ALL*/, },
4446 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
4971 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
[all …]
/utopia/UTPA2-700.0.x/modules/dac/hal/k6/dac/include/
H A Dmdrv_dac_tbl.c237 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x01/*ALL*/, },
747 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
1261 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x01/*ALL*/, },
1771 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
2281 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
2791 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
3305 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x01/*ALL*/, },
3819 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x01/*ALL*/, },
4329 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
4839 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6744 #define REG_TC_HDGEN_BK1_01_H _PK_H_(0x1, 0x01) macro
/utopia/UTPA2-700.0.x/modules/dac/hal/k6lite/dac/include/
H A Dmdrv_dac_tbl.c237 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x01/*ALL*/, },
747 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
1261 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x01/*ALL*/, },
1771 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
2281 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
2791 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
3305 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x01/*ALL*/, },
3819 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x01/*ALL*/, },
4329 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
4839 { DRV_DAC_REG(REG_TC_HDGEN_BK1_01_H), 0xFF, 0x00/*ALL*/, },
[all …]
H A Dmdrv_dac_tbl.h6744 #define REG_TC_HDGEN_BK1_01_H _PK_H_(0x1, 0x01) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/pnl/
H A Dmdrv_dac_tbl.h3062 #define REG_TC_HDGEN_BK1_01_H _PK_H_(0x1, 0x01) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/pnl/
H A Dmdrv_dac_tbl.h3062 #define REG_TC_HDGEN_BK1_01_H _PK_H_(0x1, 0x01) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/pnl/
H A Dmdrv_dac_tbl.h3062 #define REG_TC_HDGEN_BK1_01_H _PK_H_(0x1, 0x01) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/pnl/
H A Dmdrv_dac_tbl.h3062 #define REG_TC_HDGEN_BK1_01_H _PK_H_(0x1, 0x01) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/pnl/
H A Dmdrv_dac_tbl.h3062 #define REG_TC_HDGEN_BK1_01_H _PK_H_(0x1, 0x01) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/pnl/
H A Dmdrv_dac_tbl.h3062 #define REG_TC_HDGEN_BK1_01_H _PK_H_(0x1, 0x01) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/pnl/
H A Dmdrv_dac_tbl.h3062 #define REG_TC_HDGEN_BK1_01_H _PK_H_(0x1, 0x01) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/pnl/
H A Dmdrv_dac_tbl.h3062 #define REG_TC_HDGEN_BK1_01_H _PK_H_(0x1, 0x01) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/pnl/
H A Dmdrv_dac_tbl.h3062 #define REG_TC_HDGEN_BK1_01_H _PK_H_(0x1, 0x01) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/pnl/
H A Dmdrv_dac_tbl.h3062 #define REG_TC_HDGEN_BK1_01_H _PK_H_(0x1, 0x01) macro
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/pnl/
H A Dmdrv_dac_tbl.h3062 #define REG_TC_HDGEN_BK1_01_H _PK_H_(0x1, 0x01) macro