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Searched refs:REG_SC_BK34_7E_L (Results 1 – 16 of 16) sorted by relevance

/utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/
H A Dmhal_dip.c1138 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L,BIT(0),BIT(0)); in HAL_XC_DIP_Init()
1155 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L, BMASK(7:4) , BMASK(7:4)); in HAL_XC_DIP_Init()
1282 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L, 0 , BMASK(7:4)); in HAL_XC_DIP_EnableCaptureStream()
1442 SC_W2BYTEMSK(0, REG_SC_BK34_7E_L, BMASK(7:4) , BMASK(7:4)); in HAL_XC_DIP_ClearIntr()
1552 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L, 0 , BMASK(7:4)); in HAL_XC_DIP_CpatureOneFrame2()
1928 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L,u8Data_Mux << 8,BMASK(11:8)); in HAL_XC_DIP_SetMux()
1933 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L,u8Data_Mux << 12,BMASK(15:12)); in HAL_XC_DIP_SetMux()
3297 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L, BMASK(7:4) , BMASK(7:4)); in HAL_XC_DIP_InterruptDetach()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/
H A Dmhal_dip.c1139 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L,BIT(0),BIT(0)); in HAL_XC_DIP_Init()
1156 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L, BMASK(7:4) , BMASK(7:4)); in HAL_XC_DIP_Init()
1283 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L, 0 , BMASK(7:4)); in HAL_XC_DIP_EnableCaptureStream()
1443 SC_W2BYTEMSK(0, REG_SC_BK34_7E_L, BMASK(7:4) , BMASK(7:4)); in HAL_XC_DIP_ClearIntr()
1553 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L, 0 , BMASK(7:4)); in HAL_XC_DIP_CpatureOneFrame2()
1929 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L,u8Data_Mux << 8,BMASK(11:8)); in HAL_XC_DIP_SetMux()
1934 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L,u8Data_Mux << 12,BMASK(15:12)); in HAL_XC_DIP_SetMux()
3299 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L, BMASK(7:4) , BMASK(7:4)); in HAL_XC_DIP_InterruptDetach()
/utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/
H A Dmhal_dip.c1139 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L,BIT(0),BIT(0)); in HAL_XC_DIP_Init()
1156 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L, BMASK(7:4) , BMASK(7:4)); in HAL_XC_DIP_Init()
1283 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L, 0 , BMASK(7:4)); in HAL_XC_DIP_EnableCaptureStream()
1521 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L, 0 , BMASK(7:4)); in HAL_XC_DIP_CpatureOneFrame2()
1894 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L,u8Data_Mux << 8,BMASK(11:8)); in HAL_XC_DIP_SetMux()
1899 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L,u8Data_Mux << 12,BMASK(15:12)); in HAL_XC_DIP_SetMux()
3248 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L, BMASK(7:4) , BMASK(7:4)); in HAL_XC_DIP_InterruptDetach()
/utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/
H A Dmhal_dip.c1139 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L,BIT(0),BIT(0)); in HAL_XC_DIP_Init()
1156 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L, BMASK(7:4) , BMASK(7:4)); in HAL_XC_DIP_Init()
1283 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L, 0 , BMASK(7:4)); in HAL_XC_DIP_EnableCaptureStream()
1521 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L, 0 , BMASK(7:4)); in HAL_XC_DIP_CpatureOneFrame2()
1894 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L,u8Data_Mux << 8,BMASK(11:8)); in HAL_XC_DIP_SetMux()
1899 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L,u8Data_Mux << 12,BMASK(15:12)); in HAL_XC_DIP_SetMux()
3252 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L, BMASK(7:4) , BMASK(7:4)); in HAL_XC_DIP_InterruptDetach()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/
H A Dmhal_dip.c1408 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L,BIT(0),BIT(0)); in HAL_XC_DIP_Init()
1437 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L, BMASK(7:4) , BMASK(7:4)); in HAL_XC_DIP_Init()
1548 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L, 0 , BMASK(7:4)); in HAL_XC_DIP_EnableCaptureStream()
1737 SC_W2BYTEMSK(0, REG_SC_BK34_7E_L, BMASK(7:4) , BMASK(7:4)); in HAL_XC_DIP_ClearIntr()
1835 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L, 0 , BMASK(7:4)); in HAL_XC_DIP_CpatureOneFrame2()
2166 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L,u8Data_Mux << 8,BMASK(11:8)); in HAL_XC_DIP_SetMux()
4246 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L, BMASK(7:4) , BMASK(7:4)); in HAL_XC_DIP_InterruptDetach()
/utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/
H A Dmhal_dip.c620 SC_W2BYTEMSK(0, REG_SC_BK34_7E_L,BIT(0),BIT(0)); in HAL_XC_DIP_Init()
1279 SC_W2BYTEMSK(0, REG_SC_BK34_7E_L,u8Data_Mux << 8,BMASK(11:8)); in HAL_XC_DIP_SetMux()
1284 SC_W2BYTEMSK(0, REG_SC_BK34_7E_L,u8Data_Mux << 12,BMASK(15:12)); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/
H A Dmhal_dip.c775 SC_W2BYTEMSK(0, REG_SC_BK34_7E_L,BIT(0),BIT(0)); in HAL_XC_DIP_Init()
1425 SC_W2BYTEMSK(0, REG_SC_BK34_7E_L,u8Data_Mux << 8,BMASK(11:8)); in HAL_XC_DIP_SetMux()
1430 SC_W2BYTEMSK(0, REG_SC_BK34_7E_L,u8Data_Mux << 12,BMASK(15:12)); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/
H A Dmhal_dip.c729 SC_W2BYTEMSK(0, REG_SC_BK34_7E_L,BIT(0),BIT(0)); in HAL_XC_DIP_Init()
1401 SC_W2BYTEMSK(0, REG_SC_BK34_7E_L,u8Data_Mux << 8,BMASK(11:8)); in HAL_XC_DIP_SetMux()
1406 SC_W2BYTEMSK(0, REG_SC_BK34_7E_L,u8Data_Mux << 12,BMASK(15:12)); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/
H A Dmhal_dip.c731 SC_W2BYTEMSK(0, REG_SC_BK34_7E_L,BIT(0),BIT(0)); in HAL_XC_DIP_Init()
1403 SC_W2BYTEMSK(0, REG_SC_BK34_7E_L,u8Data_Mux << 8,BMASK(11:8)); in HAL_XC_DIP_SetMux()
1408 SC_W2BYTEMSK(0, REG_SC_BK34_7E_L,u8Data_Mux << 12,BMASK(15:12)); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/
H A Dmhal_dip.c653 SC_W2BYTEMSK(0, REG_SC_BK34_7E_L,BIT(0),BIT(0)); in HAL_XC_DIP_Init()
1314 SC_W2BYTEMSK(0, REG_SC_BK34_7E_L,u8Data_Mux << 8,BMASK(11:8)); in HAL_XC_DIP_SetMux()
1319 SC_W2BYTEMSK(0, REG_SC_BK34_7E_L,u8Data_Mux << 12,BMASK(15:12)); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/
H A Dmhal_dip.c1356 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L,BIT(0),BIT(0)); in HAL_XC_DIP_Init()
2047 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L,u8Data_Mux << 8,BMASK(11:8)); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/
H A Dmhal_dip.c1007 SC_W2BYTEMSK(0, REG_SC_BK34_7E_L,u16Data_Mux << 8,BMASK(11:8)); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/
H A Dmhal_dip.c1026 SC_W2BYTEMSK(0, REG_SC_BK34_7E_L,u16Data_Mux << 8,BMASK(11:8)); in HAL_XC_DIP_SetMux()
/utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/
H A Dmhal_dip.c619 SC_W2BYTEMSK(0, REG_SC_BK34_7E_L,BIT(0),BIT(0)); in HAL_XC_DIP_Init()
/utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/
H A Dmhal_dip.c617 SC_W2BYTEMSK(0, REG_SC_BK34_7E_L,BIT(0),BIT(0)); in HAL_XC_DIP_Init()
/utopia/UTPA2-700.0.x/modules/xc/drv/xc/include/
H A Dhwreg_sc.h10766 #define REG_SC_BK34_7E_L _PK_L_(0x34, 0x7E) macro