| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/ |
| H A D | mhal_hdmi.c | 300 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
311 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
322 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
333 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(4), BIT(4)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
607 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_ClockStatusInitial()
616 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_ClockStatusInitial()
625 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_ClockStatusInitial()
634 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(4), BIT(4)); // Clear clock status in _Hal_tmds_ClockStatusInitial()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/ |
| H A D | mhal_hdmi.c | 320 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
331 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
342 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
353 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(4), BIT(4)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
679 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_ClockStatusInitial()
688 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_ClockStatusInitial()
697 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_ClockStatusInitial()
706 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(4), BIT(4)); // Clear clock status in _Hal_tmds_ClockStatusInitial()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/ |
| H A D | mhal_hdmi.c | 303 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
314 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
325 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
336 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(4), BIT(4)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
610 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_ClockStatusInitial()
619 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_ClockStatusInitial()
628 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_ClockStatusInitial()
637 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(4), BIT(4)); // Clear clock status in _Hal_tmds_ClockStatusInitial()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/ |
| H A D | mhal_hdmi.c | 303 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
314 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
325 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
336 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(4), BIT(4)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
610 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_ClockStatusInitial()
619 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_ClockStatusInitial()
628 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_ClockStatusInitial()
637 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(4), BIT(4)); // Clear clock status in _Hal_tmds_ClockStatusInitial()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7821/xc/ |
| H A D | mhal_hdmi.c | 386 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
397 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
408 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
419 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(4), BIT(4)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
745 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_ClockStatusInitial()
754 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_ClockStatusInitial()
763 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_ClockStatusInitial()
772 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(4), BIT(4)); // Clear clock status in _Hal_tmds_ClockStatusInitial()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/ |
| H A D | mhal_hdmi.c | 303 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
314 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
325 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
336 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(4), BIT(4)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
610 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_ClockStatusInitial()
619 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_ClockStatusInitial()
628 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_ClockStatusInitial()
637 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(4), BIT(4)); // Clear clock status in _Hal_tmds_ClockStatusInitial()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maserati/xc/ |
| H A D | mhal_hdmi.c | 386 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
397 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
408 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
419 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(4), BIT(4)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
745 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_ClockStatusInitial()
754 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_ClockStatusInitial()
763 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_ClockStatusInitial()
772 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(4), BIT(4)); // Clear clock status in _Hal_tmds_ClockStatusInitial()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/ |
| H A D | mhal_hdmi.c | 307 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
318 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
329 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
340 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(4), BIT(4)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
618 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1));// Clear clock status in _Hal_tmds_ClockStatusInitial()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/ |
| H A D | mhal_hdmi.c | 326 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
337 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
348 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
359 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(4), BIT(4)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
689 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1));// Clear clock status in _Hal_tmds_ClockStatusInitial()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/ |
| H A D | mhal_hdmi.c | 307 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
318 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
329 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
340 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(4), BIT(4)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
618 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1));// Clear clock status in _Hal_tmds_ClockStatusInitial()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/ |
| H A D | mhal_hdmi.c | 326 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
337 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(2), BIT(2)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
348 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(3), BIT(3)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
359 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(4), BIT(4)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
689 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1));// Clear clock status in _Hal_tmds_ClockStatusInitial()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/include/ |
| H A D | hwreg_pm_sleep.h | 105 #define REG_PM_SLEEP_02_L (REG_PM_SLEEP_BASE + 0x04) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mustang/xc/include/ |
| H A D | hwreg_pm_sleep.h | 106 #define REG_PM_SLEEP_02_L (REG_PM_SLEEP_BASE + 0x04) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maldives/xc/include/ |
| H A D | hwreg_pm_sleep.h | 106 #define REG_PM_SLEEP_02_L (REG_PM_SLEEP_BASE + 0x04) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mainz/xc/include/ |
| H A D | hwreg_pm_sleep.h | 105 #define REG_PM_SLEEP_02_L (REG_PM_SLEEP_BASE + 0x04) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/messi/xc/ |
| H A D | mhal_hdmi.c | 281 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_GetClockValidFlag()
354 W2BYTEMSK(REG_PM_SLEEP_02_L, BIT(1), BIT(1)); // Clear clock status in _Hal_tmds_ClockStatusInitial()
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| /utopia/UTPA2-700.0.x/modules/xc/hal/maxim/xc/include/ |
| H A D | hwreg_pm_sleep.h | 105 #define REG_PM_SLEEP_02_L (REG_PM_SLEEP_BASE + 0x04) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/manhattan/xc/include/ |
| H A D | hwreg_pm_sleep.h | 105 #define REG_PM_SLEEP_02_L (REG_PM_SLEEP_BASE + 0x04) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/curry/xc/include/ |
| H A D | hwreg_pm_sleep.h | 106 #define REG_PM_SLEEP_02_L (REG_PM_SLEEP_BASE + 0x04) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/mooney/xc/include/ |
| H A D | hwreg_pm_sleep.h | 105 #define REG_PM_SLEEP_02_L (REG_PM_SLEEP_BASE + 0x04) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/M7621/xc/include/ |
| H A D | hwreg_pm_sleep.h | 105 #define REG_PM_SLEEP_02_L (REG_PM_SLEEP_BASE + 0x04) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6lite/xc/include/ |
| H A D | hwreg_pm_sleep.h | 106 #define REG_PM_SLEEP_02_L (REG_PM_SLEEP_BASE + 0x04) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/k6/xc/include/ |
| H A D | hwreg_pm_sleep.h | 106 #define REG_PM_SLEEP_02_L (REG_PM_SLEEP_BASE + 0x04) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/macan/xc/include/ |
| H A D | hwreg_pm_sleep.h | 105 #define REG_PM_SLEEP_02_L (REG_PM_SLEEP_BASE + 0x04) macro
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| /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/ |
| H A D | hwreg_pm_sleep.h | 106 #define REG_PM_SLEEP_02_L (REG_PM_SLEEP_BASE + 0x04) macro
|