Searched refs:REG_MIU1_GROUP3_MASK (Results 1 – 1 of 1) sorted by relevance
5214 #define REG_MIU1_GROUP3_MASK (0x1006A6UL) macro5432 REG_WR(REG_MIU1_GROUP3_MASK, 0xFFFE); //enable miu counter in MDrv_GE_BitbltPerformance()