Searched refs:REG_MIU0_GROUP3_MASK (Results 1 – 1 of 1) sorted by relevance
5209 #define REG_MIU0_GROUP3_MASK (0x1012A6UL) macro5427 REG_WR(REG_MIU0_GROUP3_MASK, 0xFFFE); //enable miu counter in MDrv_GE_BitbltPerformance()