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Searched refs:REG_MAU1_BASE (Results 1 – 25 of 31) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maldives/vpu_v3/
H A DregVPU_EX.h231 #define REG_MAU1_BASE (0x0400) macro
331 #define MAU1_MIU_SEL (REG_MAU1_BASE+(0x0001<<1))
335 #define MAU1_CPU_RST (REG_MAU1_BASE+(0x0002<<1))
338 #define MAU1_ARB0_DBG0 (REG_MAU1_BASE+(0x0008<<1))
339 #define MAU1_ARB1_DBG0 (REG_MAU1_BASE+(0x000a<<1))
348 #define MAU1_REG_MIU_RW_TAG1 (REG_MAU1_BASE+(0x0010<<1)) //[7:0]=> read index, [15…
349 #define MAU1_REG_REGION_MASK0_L (REG_MAU1_BASE+(0x0013<<1))
350 #define MAU1_REG_REGION_MASK0_H (REG_MAU1_BASE+(0x0014<<1))
351 #define MAU1_REG_REGION_START0_L (REG_MAU1_BASE+(0x0015<<1))
352 #define MAU1_REG_REGION_START0_H (REG_MAU1_BASE+(0x0016<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mustang/vpu_ex/
H A DregVPU_EX.h231 #define REG_MAU1_BASE (0x0400) macro
331 #define MAU1_MIU_SEL (REG_MAU1_BASE+(0x0001<<1))
335 #define MAU1_CPU_RST (REG_MAU1_BASE+(0x0002<<1))
338 #define MAU1_ARB0_DBG0 (REG_MAU1_BASE+(0x0008<<1))
339 #define MAU1_ARB1_DBG0 (REG_MAU1_BASE+(0x000a<<1))
348 #define MAU1_REG_MIU_RW_TAG1 (REG_MAU1_BASE+(0x0010<<1)) //[7:0]=> read index, [15…
349 #define MAU1_REG_REGION_MASK0_L (REG_MAU1_BASE+(0x0013<<1))
350 #define MAU1_REG_REGION_MASK0_H (REG_MAU1_BASE+(0x0014<<1))
351 #define MAU1_REG_REGION_START0_L (REG_MAU1_BASE+(0x0015<<1))
352 #define MAU1_REG_REGION_START0_H (REG_MAU1_BASE+(0x0016<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mustang/vpu_v3/
H A DregVPU_EX.h231 #define REG_MAU1_BASE (0x0400) macro
331 #define MAU1_MIU_SEL (REG_MAU1_BASE+(0x0001<<1))
335 #define MAU1_CPU_RST (REG_MAU1_BASE+(0x0002<<1))
338 #define MAU1_ARB0_DBG0 (REG_MAU1_BASE+(0x0008<<1))
339 #define MAU1_ARB1_DBG0 (REG_MAU1_BASE+(0x000a<<1))
348 #define MAU1_REG_MIU_RW_TAG1 (REG_MAU1_BASE+(0x0010<<1)) //[7:0]=> read index, [15…
349 #define MAU1_REG_REGION_MASK0_L (REG_MAU1_BASE+(0x0013<<1))
350 #define MAU1_REG_REGION_MASK0_H (REG_MAU1_BASE+(0x0014<<1))
351 #define MAU1_REG_REGION_START0_L (REG_MAU1_BASE+(0x0015<<1))
352 #define MAU1_REG_REGION_START0_H (REG_MAU1_BASE+(0x0016<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maldives/vpu_ex/
H A DregVPU_EX.h231 #define REG_MAU1_BASE (0x0400) macro
331 #define MAU1_MIU_SEL (REG_MAU1_BASE+(0x0001<<1))
335 #define MAU1_CPU_RST (REG_MAU1_BASE+(0x0002<<1))
338 #define MAU1_ARB0_DBG0 (REG_MAU1_BASE+(0x0008<<1))
339 #define MAU1_ARB1_DBG0 (REG_MAU1_BASE+(0x000a<<1))
348 #define MAU1_REG_MIU_RW_TAG1 (REG_MAU1_BASE+(0x0010<<1)) //[7:0]=> read index, [15…
349 #define MAU1_REG_REGION_MASK0_L (REG_MAU1_BASE+(0x0013<<1))
350 #define MAU1_REG_REGION_MASK0_H (REG_MAU1_BASE+(0x0014<<1))
351 #define MAU1_REG_REGION_START0_L (REG_MAU1_BASE+(0x0015<<1))
352 #define MAU1_REG_REGION_START0_H (REG_MAU1_BASE+(0x0016<<1))
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/vpu_v3/
H A DregVPU_EX.h233 #define REG_MAU1_BASE (0x63400) macro
239 #define REG_MAU1_BASE (0x0400) macro
358 #define MAU1_CPU_RST (REG_MAU1_BASE+(0x0002<<1))
361 #define MAU1_ARB0_DBG0 (REG_MAU1_BASE+(0x0008<<1))
362 #define MAU1_ARB1_DBG0 (REG_MAU1_BASE+(0x000a<<1))
366 #define MAU1_MIU_SEL (REG_MAU1_BASE+(0x0001<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/vpu_v3/
H A DregVPU_EX.h233 #define REG_MAU1_BASE (0x63400) macro
239 #define REG_MAU1_BASE (0x0400) macro
366 #define MAU1_CPU_RST (REG_MAU1_BASE+(0x0002<<1))
369 #define MAU1_ARB0_DBG0 (REG_MAU1_BASE+(0x0008<<1))
370 #define MAU1_ARB1_DBG0 (REG_MAU1_BASE+(0x000a<<1))
374 #define MAU1_MIU_SEL (REG_MAU1_BASE+(0x0001<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/vpu_v3/
H A DregVPU_EX.h233 #define REG_MAU1_BASE (0x63400) macro
239 #define REG_MAU1_BASE (0x0400) macro
366 #define MAU1_CPU_RST (REG_MAU1_BASE+(0x0002<<1))
369 #define MAU1_ARB0_DBG0 (REG_MAU1_BASE+(0x0008<<1))
370 #define MAU1_ARB1_DBG0 (REG_MAU1_BASE+(0x000a<<1))
374 #define MAU1_MIU_SEL (REG_MAU1_BASE+(0x0001<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/vpu_v3/
H A DregVPU_EX.h233 #define REG_MAU1_BASE (0x63400) macro
239 #define REG_MAU1_BASE (0x0400) macro
366 #define MAU1_CPU_RST (REG_MAU1_BASE+(0x0002<<1))
369 #define MAU1_ARB0_DBG0 (REG_MAU1_BASE+(0x0008<<1))
370 #define MAU1_ARB1_DBG0 (REG_MAU1_BASE+(0x000a<<1))
374 #define MAU1_MIU_SEL (REG_MAU1_BASE+(0x0001<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/vpu_v3/
H A DregVPU_EX.h233 #define REG_MAU1_BASE (0x63400) macro
239 #define REG_MAU1_BASE (0x0400) macro
366 #define MAU1_CPU_RST (REG_MAU1_BASE+(0x0002<<1))
369 #define MAU1_ARB0_DBG0 (REG_MAU1_BASE+(0x0008<<1))
370 #define MAU1_ARB1_DBG0 (REG_MAU1_BASE+(0x000a<<1))
374 #define MAU1_MIU_SEL (REG_MAU1_BASE+(0x0001<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/vpu_v3/
H A DregVPU_EX.h233 #define REG_MAU1_BASE (0x63400) macro
239 #define REG_MAU1_BASE (0x0400) macro
366 #define MAU1_CPU_RST (REG_MAU1_BASE+(0x0002<<1))
369 #define MAU1_ARB0_DBG0 (REG_MAU1_BASE+(0x0008<<1))
370 #define MAU1_ARB1_DBG0 (REG_MAU1_BASE+(0x000a<<1))
374 #define MAU1_MIU_SEL (REG_MAU1_BASE+(0x0001<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/vpu_v3/
H A DregVPU_EX.h233 #define REG_MAU1_BASE (0x63400) macro
239 #define REG_MAU1_BASE (0x0400) macro
366 #define MAU1_CPU_RST (REG_MAU1_BASE+(0x0002<<1))
369 #define MAU1_ARB0_DBG0 (REG_MAU1_BASE+(0x0008<<1))
370 #define MAU1_ARB1_DBG0 (REG_MAU1_BASE+(0x000a<<1))
374 #define MAU1_MIU_SEL (REG_MAU1_BASE+(0x0001<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/vpu_v3/
H A DregVPU_EX.h233 #define REG_MAU1_BASE (0x63400) macro
239 #define REG_MAU1_BASE (0x0400) macro
366 #define MAU1_CPU_RST (REG_MAU1_BASE+(0x0002<<1))
369 #define MAU1_ARB0_DBG0 (REG_MAU1_BASE+(0x0008<<1))
370 #define MAU1_ARB1_DBG0 (REG_MAU1_BASE+(0x000a<<1))
374 #define MAU1_MIU_SEL (REG_MAU1_BASE+(0x0001<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/vpu_v3/
H A DregVPU_EX.h233 #define REG_MAU1_BASE (0x63400) macro
239 #define REG_MAU1_BASE (0x0400) macro
366 #define MAU1_CPU_RST (REG_MAU1_BASE+(0x0002<<1))
369 #define MAU1_ARB0_DBG0 (REG_MAU1_BASE+(0x0008<<1))
370 #define MAU1_ARB1_DBG0 (REG_MAU1_BASE+(0x000a<<1))
374 #define MAU1_MIU_SEL (REG_MAU1_BASE+(0x0001<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/vpu_v3/
H A DregVPU_EX.h233 #define REG_MAU1_BASE (0x63400) macro
239 #define REG_MAU1_BASE (0x0400) macro
366 #define MAU1_CPU_RST (REG_MAU1_BASE+(0x0002<<1))
369 #define MAU1_ARB0_DBG0 (REG_MAU1_BASE+(0x0008<<1))
370 #define MAU1_ARB1_DBG0 (REG_MAU1_BASE+(0x000a<<1))
374 #define MAU1_MIU_SEL (REG_MAU1_BASE+(0x0001<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/curry/vpu_v3/
H A DregVPU_EX.h233 #define REG_MAU1_BASE (0x63400) macro
239 #define REG_MAU1_BASE (0x0400) macro
366 #define MAU1_CPU_RST (REG_MAU1_BASE+(0x0002<<1))
369 #define MAU1_ARB0_DBG0 (REG_MAU1_BASE+(0x0008<<1))
370 #define MAU1_ARB1_DBG0 (REG_MAU1_BASE+(0x000a<<1))
374 #define MAU1_MIU_SEL (REG_MAU1_BASE+(0x0001<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6lite/vpu_v3/
H A DregVPU_EX.h233 #define REG_MAU1_BASE (0x63400) macro
239 #define REG_MAU1_BASE (0x0400) macro
366 #define MAU1_CPU_RST (REG_MAU1_BASE+(0x0002<<1))
369 #define MAU1_ARB0_DBG0 (REG_MAU1_BASE+(0x0008<<1))
370 #define MAU1_ARB1_DBG0 (REG_MAU1_BASE+(0x000a<<1))
374 #define MAU1_MIU_SEL (REG_MAU1_BASE+(0x0001<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/manhattan/vpu/
H A DregVPU.h231 #define REG_MAU1_BASE (0x0400) macro
321 #define MAU1_CPU_RST (REG_MAU1_BASE+(0x0002<<1))
323 #define MAU1_ARB0_DBG0 (REG_MAU1_BASE+(0x0008<<1))
324 #define MAU1_ARB1_DBG0 (REG_MAU1_BASE+(0x000a<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/messi/vpu_ex/
H A DregVPU_EX.h231 #define REG_MAU1_BASE (0x0400UL) macro
327 #define MAU1_CPU_RST (REG_MAU1_BASE+(0x0002<<1))
330 #define MAU1_ARB0_DBG0 (REG_MAU1_BASE+(0x0008<<1))
331 #define MAU1_ARB1_DBG0 (REG_MAU1_BASE+(0x000a<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7821/vpu/
H A DregVPU.h231 #define REG_MAU1_BASE (0x0400) macro
321 #define MAU1_CPU_RST (REG_MAU1_BASE+(0x0002<<1))
323 #define MAU1_ARB0_DBG0 (REG_MAU1_BASE+(0x0008<<1))
324 #define MAU1_ARB1_DBG0 (REG_MAU1_BASE+(0x000a<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/mainz/vpu_ex/
H A DregVPU_EX.h231 #define REG_MAU1_BASE (0x0400UL) macro
327 #define MAU1_CPU_RST (REG_MAU1_BASE+(0x0002<<1))
330 #define MAU1_ARB0_DBG0 (REG_MAU1_BASE+(0x0008<<1))
331 #define MAU1_ARB1_DBG0 (REG_MAU1_BASE+(0x000a<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/M7621/vpu_ex/
H A DregVPU_EX.h231 #define REG_MAU1_BASE (0x0400UL) macro
327 #define MAU1_CPU_RST (REG_MAU1_BASE+(0x0002<<1))
330 #define MAU1_ARB0_DBG0 (REG_MAU1_BASE+(0x0008<<1))
331 #define MAU1_ARB1_DBG0 (REG_MAU1_BASE+(0x000a<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/maxim/vpu_ex/
H A DregVPU_EX.h231 #define REG_MAU1_BASE (0x0400UL) macro
327 #define MAU1_CPU_RST (REG_MAU1_BASE+(0x0002<<1))
330 #define MAU1_ARB0_DBG0 (REG_MAU1_BASE+(0x0008<<1))
331 #define MAU1_ARB1_DBG0 (REG_MAU1_BASE+(0x000a<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v1/hal/M7621/vpu/
H A DregVPU.h231 #define REG_MAU1_BASE (0x0400) macro
321 #define MAU1_CPU_RST (REG_MAU1_BASE+(0x0002<<1))
323 #define MAU1_ARB0_DBG0 (REG_MAU1_BASE+(0x0008<<1))
324 #define MAU1_ARB1_DBG0 (REG_MAU1_BASE+(0x000a<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/macan/vpu_ex/
H A DregVPU_EX.h231 #define REG_MAU1_BASE (0x0400UL) macro
327 #define MAU1_CPU_RST (REG_MAU1_BASE+(0x0002<<1))
330 #define MAU1_ARB0_DBG0 (REG_MAU1_BASE+(0x0008<<1))
331 #define MAU1_ARB1_DBG0 (REG_MAU1_BASE+(0x000a<<1))
/utopia/UTPA2-700.0.x/modules/vdec_v2/hal/manhattan/vpu_ex/
H A DregVPU_EX.h231 #define REG_MAU1_BASE (0x0400UL) macro
327 #define MAU1_CPU_RST (REG_MAU1_BASE+(0x0002<<1))
330 #define MAU1_ARB0_DBG0 (REG_MAU1_BASE+(0x0008<<1))
331 #define MAU1_ARB1_DBG0 (REG_MAU1_BASE+(0x000a<<1))

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