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Searched refs:REG_ISP_CHIP_RST (Results 1 – 25 of 30) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/flash/hal/maldives/flash/serial/
H A DregSERFLASH.h221 #define REG_ISP_CHIP_RST 0x3F // SPI clock source [0]:gate [1]:inv [4:2]:clk_sel 000… macro
/utopia/UTPA2-700.0.x/modules/flash/hal/manhattan/flash/serial/
H A DregSERFLASH.h214 #define REG_ISP_CHIP_RST 0x3F // SPI clock source [0]:gate [1]:inv [4:2]:clk_sel 000… macro
H A DhalSERFLASH.c1380 ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_RESET, SFSH_CHIP_RESET_MASK); in _HAL_SPI_Rest()
1381 ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_NOTRESET, SFSH_CHIP_RESET_MASK); in _HAL_SPI_Rest()
/utopia/UTPA2-700.0.x/modules/flash/hal/macan/flash/serial/
H A DregSERFLASH.h214 #define REG_ISP_CHIP_RST 0x3F // SPI clock source [0]:gate [1]:inv [4:2]:clk_sel 000… macro
H A DhalSERFLASH.c1342 ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_RESET, SFSH_CHIP_RESET_MASK); in _HAL_SPI_Rest()
1343 ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_NOTRESET, SFSH_CHIP_RESET_MASK); in _HAL_SPI_Rest()
/utopia/UTPA2-700.0.x/modules/flash/hal/messi/flash/serial/
H A DregSERFLASH.h215 #define REG_ISP_CHIP_RST 0x3F // SPI clock source [0]:gate [1]:inv [4:2]:clk_sel 000… macro
H A DhalSERFLASH.c1350 ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_RESET, SFSH_CHIP_RESET_MASK); in _HAL_SPI_Rest()
1351 ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_NOTRESET, SFSH_CHIP_RESET_MASK); in _HAL_SPI_Rest()
/utopia/UTPA2-700.0.x/modules/flash/hal/maxim/flash/serial/
H A DregSERFLASH.h214 #define REG_ISP_CHIP_RST 0x3F // SPI clock source [0]:gate [1]:inv [4:2]:clk_sel 000… macro
H A DhalSERFLASH.c1379 ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_RESET, SFSH_CHIP_RESET_MASK); in _HAL_SPI_Rest()
1380 ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_NOTRESET, SFSH_CHIP_RESET_MASK); in _HAL_SPI_Rest()
/utopia/UTPA2-700.0.x/modules/flash/hal/maserati/flash/serial/
H A DregSERFLASH.h214 #define REG_ISP_CHIP_RST 0x3F // SPI clock source [0]:gate [1]:inv [4:2]:clk_sel 000… macro
H A DhalSERFLASH.c1379 ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_RESET, SFSH_CHIP_RESET_MASK); in _HAL_SPI_Rest()
1380 ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_NOTRESET, SFSH_CHIP_RESET_MASK); in _HAL_SPI_Rest()
/utopia/UTPA2-700.0.x/modules/flash/hal/M7821/flash/serial/
H A DregSERFLASH.h214 #define REG_ISP_CHIP_RST 0x3F // SPI clock source [0]:gate [1]:inv [4:2]:clk_sel 000… macro
H A DhalSERFLASH.c1379 ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_RESET, SFSH_CHIP_RESET_MASK); in _HAL_SPI_Rest()
1380 ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_NOTRESET, SFSH_CHIP_RESET_MASK); in _HAL_SPI_Rest()
/utopia/UTPA2-700.0.x/modules/flash/hal/M7621/flash/serial/
H A DregSERFLASH.h214 #define REG_ISP_CHIP_RST 0x3F // SPI clock source [0]:gate [1]:inv [4:2]:clk_sel 000… macro
H A DhalSERFLASH.c1379 ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_RESET, SFSH_CHIP_RESET_MASK); in _HAL_SPI_Rest()
1380 ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_NOTRESET, SFSH_CHIP_RESET_MASK); in _HAL_SPI_Rest()
/utopia/UTPA2-700.0.x/modules/flash/hal/mainz/flash/serial/
H A DregSERFLASH.h215 #define REG_ISP_CHIP_RST 0x3F // SPI clock source [0]:gate [1]:inv [4:2]:clk_sel 000… macro
H A DhalSERFLASH.c1350 ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_RESET, SFSH_CHIP_RESET_MASK); in _HAL_SPI_Rest()
1351 ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_NOTRESET, SFSH_CHIP_RESET_MASK); in _HAL_SPI_Rest()
/utopia/UTPA2-700.0.x/modules/flash/hal/mooney/flash/serial/
H A DregSERFLASH.h214 #define REG_ISP_CHIP_RST 0x3F // SPI clock source [0]:gate [1]:inv [4:2]:clk_sel 000… macro
H A DhalSERFLASH.c1342 ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_RESET, SFSH_CHIP_RESET_MASK); in _HAL_SPI_Rest()
1343 ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_NOTRESET, SFSH_CHIP_RESET_MASK); in _HAL_SPI_Rest()
/utopia/UTPA2-700.0.x/modules/flash/hal/k6lite/flash/serial/
H A DregSERFLASH.h223 #define REG_ISP_CHIP_RST 0x3F // SPI clock source [0]:gate [1]:inv [4:2]:clk_sel 000… macro
/utopia/UTPA2-700.0.x/modules/flash/hal/kano/flash/serial/
H A DregSERFLASH.h223 #define REG_ISP_CHIP_RST 0x3F // SPI clock source [0]:gate [1]:inv [4:2]:clk_sel 000… macro
H A DhalSERFLASH.c1193 ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_RESET, SFSH_CHIP_RESET_MASK); in _HAL_SPI_Rest()
1194 ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_NOTRESET, SFSH_CHIP_RESET_MASK); in _HAL_SPI_Rest()
/utopia/UTPA2-700.0.x/modules/flash/hal/curry/flash/serial/
H A DregSERFLASH.h223 #define REG_ISP_CHIP_RST 0x3F // SPI clock source [0]:gate [1]:inv [4:2]:clk_sel 000… macro
/utopia/UTPA2-700.0.x/modules/flash/hal/k6/flash/serial/
H A DregSERFLASH.h223 #define REG_ISP_CHIP_RST 0x3F // SPI clock source [0]:gate [1]:inv [4:2]:clk_sel 000… macro
/utopia/UTPA2-700.0.x/modules/flash/hal/mustang/flash/serial/
H A DregSERFLASH.h222 #define REG_ISP_CHIP_RST 0x3F // SPI clock source [0]:gate [1]:inv [4:2]:clk_sel 000… macro

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