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Searched refs:REG_HWI2C_DMA_CTL (Results 1 – 25 of 30) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/hwi2c/hal/maxim/hwi2c/
H A DhalHWI2C.c552 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_RETRIG, TRUE);
569 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_TXNOSTOP, bTxNoStop); in HAL_HWI2C_DMA_SetTxfrStop()
603 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_RDWTCMD, bRdWrt); in HAL_HWI2C_DMA_SetRdWrt()
621 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_MIUCHSEL, bMiuCh1); in HAL_HWI2C_DMA_SetMiuChannel()
1030 if (HAL_HWI2C_ReadByte(REG_HWI2C_DMA_CTL+u32Offset) & _DMA_CTL_RDWTCMD ) { in miic_handler()
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/M7621/hwi2c/
H A DhalHWI2C.c552 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_RETRIG, TRUE);
569 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_TXNOSTOP, bTxNoStop); in HAL_HWI2C_DMA_SetTxfrStop()
603 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_RDWTCMD, bRdWrt); in HAL_HWI2C_DMA_SetRdWrt()
621 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_MIUCHSEL, bMiuCh1); in HAL_HWI2C_DMA_SetMiuChannel()
1030 if (HAL_HWI2C_ReadByte(REG_HWI2C_DMA_CTL+u32Offset) & _DMA_CTL_RDWTCMD ) { in miic_handler()
H A DregHWI2C.h232 #define REG_HWI2C_DMA_CTL (HWI2C_REG_BASE+0x23*2) macro
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/manhattan/hwi2c/
H A DhalHWI2C.c552 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_RETRIG, TRUE);
569 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_TXNOSTOP, bTxNoStop); in HAL_HWI2C_DMA_SetTxfrStop()
603 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_RDWTCMD, bRdWrt); in HAL_HWI2C_DMA_SetRdWrt()
621 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_MIUCHSEL, bMiuCh1); in HAL_HWI2C_DMA_SetMiuChannel()
1027 if (HAL_HWI2C_ReadByte(REG_HWI2C_DMA_CTL+u32Offset) & _DMA_CTL_RDWTCMD ) { in miic_handler()
H A DregHWI2C.h232 #define REG_HWI2C_DMA_CTL (HWI2C_REG_BASE+0x23*2) macro
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/M7821/hwi2c/
H A DhalHWI2C.c552 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_RETRIG, TRUE);
569 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_TXNOSTOP, bTxNoStop); in HAL_HWI2C_DMA_SetTxfrStop()
603 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_RDWTCMD, bRdWrt); in HAL_HWI2C_DMA_SetRdWrt()
621 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_MIUCHSEL, bMiuCh1); in HAL_HWI2C_DMA_SetMiuChannel()
1030 if (HAL_HWI2C_ReadByte(REG_HWI2C_DMA_CTL+u32Offset) & _DMA_CTL_RDWTCMD ) { in miic_handler()
H A DregHWI2C.h232 #define REG_HWI2C_DMA_CTL (HWI2C_REG_BASE+0x23*2) macro
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/maserati/hwi2c/
H A DhalHWI2C.c552 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_RETRIG, TRUE);
569 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_TXNOSTOP, bTxNoStop); in HAL_HWI2C_DMA_SetTxfrStop()
603 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_RDWTCMD, bRdWrt); in HAL_HWI2C_DMA_SetRdWrt()
621 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_MIUCHSEL, bMiuCh1); in HAL_HWI2C_DMA_SetMiuChannel()
1030 if (HAL_HWI2C_ReadByte(REG_HWI2C_DMA_CTL+u32Offset) & _DMA_CTL_RDWTCMD ) { in miic_handler()
H A DregHWI2C.h232 #define REG_HWI2C_DMA_CTL (HWI2C_REG_BASE+0x23*2) macro
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/maldives/hwi2c/
H A DhalHWI2C.c523 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_RETRIG, TRUE);
540 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_TXNOSTOP, bTxNoStop); in HAL_HWI2C_DMA_SetTxfrStop()
574 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_RDWTCMD, bRdWrt); in HAL_HWI2C_DMA_SetRdWrt()
592 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_MIUCHSEL, bMiuCh1); in HAL_HWI2C_DMA_SetMiuChannel()
H A DregHWI2C.h212 #define REG_HWI2C_DMA_CTL (HWI2C_REG_BASE+0x23*2) macro
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/mainz/hwi2c/
H A DhalHWI2C.c530 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_RETRIG, TRUE);
547 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_TXNOSTOP, bTxNoStop); in HAL_HWI2C_DMA_SetTxfrStop()
581 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_RDWTCMD, bRdWrt); in HAL_HWI2C_DMA_SetRdWrt()
599 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_MIUCHSEL, bMiuCh1); in HAL_HWI2C_DMA_SetMiuChannel()
H A DregHWI2C.h192 #define REG_HWI2C_DMA_CTL (HWI2C_REG_BASE+0x23*2) macro
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/macan/hwi2c/
H A DhalHWI2C.c528 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_RETRIG, TRUE);
545 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_TXNOSTOP, bTxNoStop); in HAL_HWI2C_DMA_SetTxfrStop()
579 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_RDWTCMD, bRdWrt); in HAL_HWI2C_DMA_SetRdWrt()
597 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_MIUCHSEL, bMiuCh1); in HAL_HWI2C_DMA_SetMiuChannel()
H A DregHWI2C.h214 #define REG_HWI2C_DMA_CTL (HWI2C_REG_BASE+0x23*2) macro
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/mustang/hwi2c/
H A DhalHWI2C.c523 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_RETRIG, TRUE);
540 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_TXNOSTOP, bTxNoStop); in HAL_HWI2C_DMA_SetTxfrStop()
574 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_RDWTCMD, bRdWrt); in HAL_HWI2C_DMA_SetRdWrt()
592 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_MIUCHSEL, bMiuCh1); in HAL_HWI2C_DMA_SetMiuChannel()
H A DregHWI2C.h212 #define REG_HWI2C_DMA_CTL (HWI2C_REG_BASE+0x23*2) macro
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/messi/hwi2c/
H A DhalHWI2C.c530 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_RETRIG, TRUE);
547 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_TXNOSTOP, bTxNoStop); in HAL_HWI2C_DMA_SetTxfrStop()
581 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_RDWTCMD, bRdWrt); in HAL_HWI2C_DMA_SetRdWrt()
599 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_MIUCHSEL, bMiuCh1); in HAL_HWI2C_DMA_SetMiuChannel()
H A DregHWI2C.h214 #define REG_HWI2C_DMA_CTL (HWI2C_REG_BASE+0x23*2) macro
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/mooney/hwi2c/
H A DhalHWI2C.c528 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_RETRIG, TRUE);
545 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_TXNOSTOP, bTxNoStop); in HAL_HWI2C_DMA_SetTxfrStop()
579 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_RDWTCMD, bRdWrt); in HAL_HWI2C_DMA_SetRdWrt()
597 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u32PortOffset, _DMA_CTL_MIUCHSEL, bMiuCh1); in HAL_HWI2C_DMA_SetMiuChannel()
H A DregHWI2C.h214 #define REG_HWI2C_DMA_CTL (HWI2C_REG_BASE+0x23*2) macro
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/kano/hwi2c/
H A DhalHWI2C.c741 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_RETRIG, TRUE);
761 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_TXNOSTOP, bTxNoStop); in HAL_HWI2C_DMA_SetTxfrStop()
798 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_RDWTCMD, bRdWrt); in HAL_HWI2C_DMA_SetRdWrt()
819 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_MIUCHSEL, bMiuCh1); in HAL_HWI2C_DMA_SetMiuChannel()
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/curry/hwi2c/
H A DhalHWI2C.c741 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_RETRIG, TRUE);
761 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_TXNOSTOP, bTxNoStop); in HAL_HWI2C_DMA_SetTxfrStop()
798 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_RDWTCMD, bRdWrt); in HAL_HWI2C_DMA_SetRdWrt()
819 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_MIUCHSEL, bMiuCh1); in HAL_HWI2C_DMA_SetMiuChannel()
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/k6/hwi2c/
H A DhalHWI2C.c741 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_RETRIG, TRUE);
761 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_TXNOSTOP, bTxNoStop); in HAL_HWI2C_DMA_SetTxfrStop()
798 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_RDWTCMD, bRdWrt); in HAL_HWI2C_DMA_SetRdWrt()
819 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_MIUCHSEL, bMiuCh1); in HAL_HWI2C_DMA_SetMiuChannel()
/utopia/UTPA2-700.0.x/modules/hwi2c/hal/k6lite/hwi2c/
H A DhalHWI2C.c741 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_RETRIG, TRUE);
761 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_TXNOSTOP, bTxNoStop); in HAL_HWI2C_DMA_SetTxfrStop()
798 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_RDWTCMD, bRdWrt); in HAL_HWI2C_DMA_SetRdWrt()
819 return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_MIUCHSEL, bMiuCh1); in HAL_HWI2C_DMA_SetMiuChannel()

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